diff --git a/src/xenia/cpu/ppc/testing/instr_vcmpbfp.s b/src/xenia/cpu/ppc/testing/instr_vcmpbfp.s
new file mode 100644
index 000000000..d4942a3f6
--- /dev/null
+++ b/src/xenia/cpu/ppc/testing/instr_vcmpbfp.s
@@ -0,0 +1,53 @@
+test_vcmpbfp_1:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [3F800000, 3F800000, 3F800000, 3F800000]
+  vcmpbfp v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [3F800000, 3F800000, 3F800000, 3F800000]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vcmpbfp_2:
+  #_ REGISTER_IN v3 [3F800000, 3F800000, 3F800000, 3F800000]
+  #_ REGISTER_IN v4 [40000000, 40000000, 40000000, 40000000]
+  vcmpbfp v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [3F800000, 3F800000, 3F800000, 3F800000]
+  #_ REGISTER_OUT v4 [40000000, 40000000, 40000000, 40000000]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vcmpbfp_3:
+  #_ REGISTER_IN v3 [40400000, 40400000, 40400000, 40400000]
+  #_ REGISTER_IN v4 [40000000, 40000000, 40000000, 40000000]
+  vcmpbfp v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [40400000, 40400000, 40400000, 40400000]
+  #_ REGISTER_OUT v4 [40000000, 40000000, 40000000, 40000000]
+  #_ REGISTER_OUT v5 [80000000, 80000000, 80000000, 80000000]
+
+test_vcmpbfp_4:
+  #_ REGISTER_IN v3 [C0400000, C0400000, C0400000, C0400000]
+  #_ REGISTER_IN v4 [40000000, 40000000, 40000000, 40000000]
+  vcmpbfp v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [C0400000, C0400000, C0400000, C0400000]
+  #_ REGISTER_OUT v4 [40000000, 40000000, 40000000, 40000000]
+  #_ REGISTER_OUT v5 [40000000, 40000000, 40000000, 40000000]
+
+test_vcmpbfp_5:
+  #_ REGISTER_IN v3 [3F800000, C0000000, 40400000, 00000000]
+  #_ REGISTER_IN v4 [40000000, 40000000, 40000000, 40000000]
+  vcmpbfp v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [3F800000, C0000000, 40400000, 00000000]
+  #_ REGISTER_OUT v4 [40000000, 40000000, 40000000, 40000000]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 80000000, 00000000]
+
+test_vcmpbfp_6:
+  #_ REGISTER_IN v3 [BF800000, BF800000, BF800000, BF800000]
+  #_ REGISTER_IN v4 [40000000, 40000000, 40000000, 40000000]
+  vcmpbfp v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [BF800000, BF800000, BF800000, BF800000]
+  #_ REGISTER_OUT v4 [40000000, 40000000, 40000000, 40000000]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
diff --git a/src/xenia/cpu/ppc/testing/instr_vcmpeqfp.s b/src/xenia/cpu/ppc/testing/instr_vcmpeqfp.s
new file mode 100644
index 000000000..0e0120a27
--- /dev/null
+++ b/src/xenia/cpu/ppc/testing/instr_vcmpeqfp.s
@@ -0,0 +1,53 @@
+test_vcmpeqfp_1:
+  #_ REGISTER_IN v3 [3F800000, 40000000, 40400000, 40800000]
+  #_ REGISTER_IN v4 [3F800000, 40000000, 40400000, 40800000]
+  vcmpeqfp v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [3F800000, 40000000, 40400000, 40800000]
+  #_ REGISTER_OUT v4 [3F800000, 40000000, 40400000, 40800000]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vcmpeqfp_2:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vcmpeqfp v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vcmpeqfp_3:
+  #_ REGISTER_IN v3 [3F800000, 40000000, 40400000, 40800000]
+  #_ REGISTER_IN v4 [3F800000, 40000000, 40400000, 40A00000]
+  vcmpeqfp v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [3F800000, 40000000, 40400000, 40800000]
+  #_ REGISTER_OUT v4 [3F800000, 40000000, 40400000, 40A00000]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, 00000000]
+
+test_vcmpeqfp_4:
+  #_ REGISTER_IN v3 [BF800000, C0000000, C0400000, C0800000]
+  #_ REGISTER_IN v4 [BF800000, C0000000, C0400000, C0800000]
+  vcmpeqfp v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [BF800000, C0000000, C0400000, C0800000]
+  #_ REGISTER_OUT v4 [BF800000, C0000000, C0400000, C0800000]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vcmpeqfp_5:
+  #_ REGISTER_IN v3 [3F800000, BF800000, 40000000, C0000000]
+  #_ REGISTER_IN v4 [3F800001, BF800001, 40000001, C0000001]
+  vcmpeqfp v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [3F800000, BF800000, 40000000, C0000000]
+  #_ REGISTER_OUT v4 [3F800001, BF800001, 40000001, C0000001]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vcmpeqfp_6:
+  #_ REGISTER_IN v3 [80000000, 80000000, 80000000, 80000000]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vcmpeqfp v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 80000000]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
diff --git a/src/xenia/cpu/ppc/testing/instr_vcmpequb.s b/src/xenia/cpu/ppc/testing/instr_vcmpequb.s
new file mode 100644
index 000000000..45806e5b0
--- /dev/null
+++ b/src/xenia/cpu/ppc/testing/instr_vcmpequb.s
@@ -0,0 +1,53 @@
+test_vcmpequb_1:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vcmpequb v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vcmpequb_2:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vcmpequb v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vcmpequb_3:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vcmpequb v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vcmpequb_4:
+  #_ REGISTER_IN v3 [12345678, 9ABCDEF0, 11223344, 55667788]
+  #_ REGISTER_IN v4 [12345678, 9ABCDEF0, 11223344, 55667788]
+  vcmpequb v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [12345678, 9ABCDEF0, 11223344, 55667788]
+  #_ REGISTER_OUT v4 [12345678, 9ABCDEF0, 11223344, 55667788]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vcmpequb_5:
+  #_ REGISTER_IN v3 [12345678, 9ABCDEF0, 11223344, 55667788]
+  #_ REGISTER_IN v4 [12345679, 9ABCDEF0, 11223344, 55667788]
+  vcmpequb v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [12345678, 9ABCDEF0, 11223344, 55667788]
+  #_ REGISTER_OUT v4 [12345679, 9ABCDEF0, 11223344, 55667788]
+  #_ REGISTER_OUT v5 [FFFFFF00, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vcmpequb_6:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  vcmpequb v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
diff --git a/src/xenia/cpu/ppc/testing/instr_vcmpequh.s b/src/xenia/cpu/ppc/testing/instr_vcmpequh.s
new file mode 100644
index 000000000..8dcd86236
--- /dev/null
+++ b/src/xenia/cpu/ppc/testing/instr_vcmpequh.s
@@ -0,0 +1,53 @@
+test_vcmpequh_1:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vcmpequh v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vcmpequh_2:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vcmpequh v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vcmpequh_3:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
+  vcmpequh v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vcmpequh_4:
+  #_ REGISTER_IN v3 [12345678, 9ABCDEF0, 11223344, 55667788]
+  #_ REGISTER_IN v4 [12345678, 9ABCDEF0, 11223344, 55667788]
+  vcmpequh v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [12345678, 9ABCDEF0, 11223344, 55667788]
+  #_ REGISTER_OUT v4 [12345678, 9ABCDEF0, 11223344, 55667788]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vcmpequh_5:
+  #_ REGISTER_IN v3 [12345678, 9ABCDEF0, 11223344, 55667788]
+  #_ REGISTER_IN v4 [12345679, 9ABCDEF0, 11223344, 55667788]
+  vcmpequh v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [12345678, 9ABCDEF0, 11223344, 55667788]
+  #_ REGISTER_OUT v4 [12345679, 9ABCDEF0, 11223344, 55667788]
+  #_ REGISTER_OUT v5 [FFFF0000, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vcmpequh_6:
+  #_ REGISTER_IN v3 [00010002, 00030004, 00050006, 00070008]
+  #_ REGISTER_IN v4 [00010002, 00030004, 00050006, 00070008]
+  vcmpequh v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00010002, 00030004, 00050006, 00070008]
+  #_ REGISTER_OUT v4 [00010002, 00030004, 00050006, 00070008]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
diff --git a/src/xenia/cpu/ppc/testing/instr_vcmpequw.s b/src/xenia/cpu/ppc/testing/instr_vcmpequw.s
new file mode 100644
index 000000000..976c6038b
--- /dev/null
+++ b/src/xenia/cpu/ppc/testing/instr_vcmpequw.s
@@ -0,0 +1,53 @@
+test_vcmpequw_1:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vcmpequw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vcmpequw_2:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vcmpequw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vcmpequw_3:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
+  vcmpequw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vcmpequw_4:
+  #_ REGISTER_IN v3 [12345678, 9ABCDEF0, 11223344, 55667788]
+  #_ REGISTER_IN v4 [12345678, 9ABCDEF0, 11223344, 55667788]
+  vcmpequw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [12345678, 9ABCDEF0, 11223344, 55667788]
+  #_ REGISTER_OUT v4 [12345678, 9ABCDEF0, 11223344, 55667788]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vcmpequw_5:
+  #_ REGISTER_IN v3 [12345678, 9ABCDEF0, 11223344, 55667788]
+  #_ REGISTER_IN v4 [12345678, 9ABCDEF0, 11223344, 55667789]
+  vcmpequw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [12345678, 9ABCDEF0, 11223344, 55667788]
+  #_ REGISTER_OUT v4 [12345678, 9ABCDEF0, 11223344, 55667789]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, 00000000]
+
+test_vcmpequw_6:
+  #_ REGISTER_IN v3 [00000001, 00000002, 00000003, 00000004]
+  #_ REGISTER_IN v4 [00000001, 00000002, 00000003, 00000004]
+  vcmpequw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000001, 00000002, 00000003, 00000004]
+  #_ REGISTER_OUT v4 [00000001, 00000002, 00000003, 00000004]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
diff --git a/src/xenia/cpu/ppc/testing/instr_vcmpgefp.s b/src/xenia/cpu/ppc/testing/instr_vcmpgefp.s
new file mode 100644
index 000000000..b004f1cef
--- /dev/null
+++ b/src/xenia/cpu/ppc/testing/instr_vcmpgefp.s
@@ -0,0 +1,62 @@
+test_vcmpgefp_1:
+  #_ REGISTER_IN v3 [40000000, 40000000, 40000000, 40000000]
+  #_ REGISTER_IN v4 [3F800000, 3F800000, 3F800000, 3F800000]
+  vcmpgefp v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [40000000, 40000000, 40000000, 40000000]
+  #_ REGISTER_OUT v4 [3F800000, 3F800000, 3F800000, 3F800000]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vcmpgefp_2:
+  #_ REGISTER_IN v3 [3F800000, 3F800000, 3F800000, 3F800000]
+  #_ REGISTER_IN v4 [3F800000, 3F800000, 3F800000, 3F800000]
+  vcmpgefp v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [3F800000, 3F800000, 3F800000, 3F800000]
+  #_ REGISTER_OUT v4 [3F800000, 3F800000, 3F800000, 3F800000]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vcmpgefp_3:
+  #_ REGISTER_IN v3 [3F800000, 3F800000, 3F800000, 3F800000]
+  #_ REGISTER_IN v4 [40000000, 40000000, 40000000, 40000000]
+  vcmpgefp v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [3F800000, 3F800000, 3F800000, 3F800000]
+  #_ REGISTER_OUT v4 [40000000, 40000000, 40000000, 40000000]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vcmpgefp_4:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [BF800000, BF800000, BF800000, BF800000]
+  vcmpgefp v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [BF800000, BF800000, BF800000, BF800000]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vcmpgefp_5:
+  #_ REGISTER_IN v3 [C0000000, C0000000, C0000000, C0000000]
+  #_ REGISTER_IN v4 [BF800000, BF800000, BF800000, BF800000]
+  vcmpgefp v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [C0000000, C0000000, C0000000, C0000000]
+  #_ REGISTER_OUT v4 [BF800000, BF800000, BF800000, BF800000]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vcmpgefp_6:
+  #_ REGISTER_IN v3 [3F800000, 40000000, 40400000, 40800000]
+  #_ REGISTER_IN v4 [3F800000, 3F800000, 40400000, 40A00000]
+  vcmpgefp v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [3F800000, 40000000, 40400000, 40800000]
+  #_ REGISTER_OUT v4 [3F800000, 3F800000, 40400000, 40A00000]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, 00000000]
+
+test_vcmpgefp_7:
+  #_ REGISTER_IN v3 [80000000, 00000000, 00000000, 80000000]
+  #_ REGISTER_IN v4 [00000000, 80000000, 00000000, 80000000]
+  vcmpgefp v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [80000000, 00000000, 00000000, 80000000]
+  #_ REGISTER_OUT v4 [00000000, 80000000, 00000000, 80000000]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
diff --git a/src/xenia/cpu/ppc/testing/instr_vcmpgtfp.s b/src/xenia/cpu/ppc/testing/instr_vcmpgtfp.s
new file mode 100644
index 000000000..aa4e3136a
--- /dev/null
+++ b/src/xenia/cpu/ppc/testing/instr_vcmpgtfp.s
@@ -0,0 +1,62 @@
+test_vcmpgtfp_1:
+  #_ REGISTER_IN v3 [40000000, 40000000, 40000000, 40000000]
+  #_ REGISTER_IN v4 [3F800000, 3F800000, 3F800000, 3F800000]
+  vcmpgtfp v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [40000000, 40000000, 40000000, 40000000]
+  #_ REGISTER_OUT v4 [3F800000, 3F800000, 3F800000, 3F800000]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vcmpgtfp_2:
+  #_ REGISTER_IN v3 [3F800000, 3F800000, 3F800000, 3F800000]
+  #_ REGISTER_IN v4 [3F800000, 3F800000, 3F800000, 3F800000]
+  vcmpgtfp v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [3F800000, 3F800000, 3F800000, 3F800000]
+  #_ REGISTER_OUT v4 [3F800000, 3F800000, 3F800000, 3F800000]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vcmpgtfp_3:
+  #_ REGISTER_IN v3 [3F800000, 3F800000, 3F800000, 3F800000]
+  #_ REGISTER_IN v4 [40000000, 40000000, 40000000, 40000000]
+  vcmpgtfp v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [3F800000, 3F800000, 3F800000, 3F800000]
+  #_ REGISTER_OUT v4 [40000000, 40000000, 40000000, 40000000]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vcmpgtfp_4:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [BF800000, BF800000, BF800000, BF800000]
+  vcmpgtfp v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [BF800000, BF800000, BF800000, BF800000]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vcmpgtfp_5:
+  #_ REGISTER_IN v3 [C0000000, C0000000, C0000000, C0000000]
+  #_ REGISTER_IN v4 [BF800000, BF800000, BF800000, BF800000]
+  vcmpgtfp v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [C0000000, C0000000, C0000000, C0000000]
+  #_ REGISTER_OUT v4 [BF800000, BF800000, BF800000, BF800000]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vcmpgtfp_6:
+  #_ REGISTER_IN v3 [3F800000, 40000000, 40400000, 40800000]
+  #_ REGISTER_IN v4 [3F800000, 3F800000, 40400000, 40A00000]
+  vcmpgtfp v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [3F800000, 40000000, 40400000, 40800000]
+  #_ REGISTER_OUT v4 [3F800000, 3F800000, 40400000, 40A00000]
+  #_ REGISTER_OUT v5 [00000000, FFFFFFFF, 00000000, 00000000]
+
+test_vcmpgtfp_7:
+  #_ REGISTER_IN v3 [00000000, 00000000, 80000000, 80000000]
+  #_ REGISTER_IN v4 [00000000, 80000000, 00000000, 80000000]
+  vcmpgtfp v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 80000000, 80000000]
+  #_ REGISTER_OUT v4 [00000000, 80000000, 00000000, 80000000]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
diff --git a/src/xenia/cpu/ppc/testing/instr_vcmpgtsb.s b/src/xenia/cpu/ppc/testing/instr_vcmpgtsb.s
new file mode 100644
index 000000000..f307b9a59
--- /dev/null
+++ b/src/xenia/cpu/ppc/testing/instr_vcmpgtsb.s
@@ -0,0 +1,62 @@
+test_vcmpgtsb_1:
+  #_ REGISTER_IN v3 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vcmpgtsb v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vcmpgtsb_2:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vcmpgtsb v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vcmpgtsb_3:
+  #_ REGISTER_IN v3 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vcmpgtsb v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vcmpgtsb_4:
+  #_ REGISTER_IN v3 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F7F]
+  #_ REGISTER_IN v4 [7E7E7E7E, 7E7E7E7E, 7E7E7E7E, 7E7E7E7E]
+  vcmpgtsb v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F7F]
+  #_ REGISTER_OUT v4 [7E7E7E7E, 7E7E7E7E, 7E7E7E7E, 7E7E7E7E]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vcmpgtsb_5:
+  #_ REGISTER_IN v3 [80808080, 80808080, 80808080, 80808080]
+  #_ REGISTER_IN v4 [81818181, 81818181, 81818181, 81818181]
+  vcmpgtsb v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [80808080, 80808080, 80808080, 80808080]
+  #_ REGISTER_OUT v4 [81818181, 81818181, 81818181, 81818181]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vcmpgtsb_6:
+  #_ REGISTER_IN v3 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vcmpgtsb v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vcmpgtsb_7:
+  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vcmpgtsb v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v5 [00FFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
diff --git a/src/xenia/cpu/ppc/testing/instr_vcmpgtsh.s b/src/xenia/cpu/ppc/testing/instr_vcmpgtsh.s
new file mode 100644
index 000000000..483d3a1b9
--- /dev/null
+++ b/src/xenia/cpu/ppc/testing/instr_vcmpgtsh.s
@@ -0,0 +1,53 @@
+test_vcmpgtsh_1:
+  #_ REGISTER_IN v3 [00010001, 00010001, 00010001, 00010001]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vcmpgtsh v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00010001, 00010001, 00010001, 00010001]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vcmpgtsh_2:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
+  vcmpgtsh v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vcmpgtsh_3:
+  #_ REGISTER_IN v3 [00010001, 00010001, 00010001, 00010001]
+  #_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
+  vcmpgtsh v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00010001, 00010001, 00010001, 00010001]
+  #_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vcmpgtsh_4:
+  #_ REGISTER_IN v3 [7FFF7FFF, 7FFF7FFF, 7FFF7FFF, 7FFF7FFF]
+  #_ REGISTER_IN v4 [7FFE7FFE, 7FFE7FFE, 7FFE7FFE, 7FFE7FFE]
+  vcmpgtsh v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [7FFF7FFF, 7FFF7FFF, 7FFF7FFF, 7FFF7FFF]
+  #_ REGISTER_OUT v4 [7FFE7FFE, 7FFE7FFE, 7FFE7FFE, 7FFE7FFE]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vcmpgtsh_5:
+  #_ REGISTER_IN v3 [80008000, 80008000, 80008000, 80008000]
+  #_ REGISTER_IN v4 [80018001, 80018001, 80018001, 80018001]
+  vcmpgtsh v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [80008000, 80008000, 80008000, 80008000]
+  #_ REGISTER_OUT v4 [80018001, 80018001, 80018001, 80018001]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vcmpgtsh_6:
+  #_ REGISTER_IN v3 [00010001, 00010001, 00010001, 00010001]
+  #_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vcmpgtsh v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00010001, 00010001, 00010001, 00010001]
+  #_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
diff --git a/src/xenia/cpu/ppc/testing/instr_vcmpgtsw.s b/src/xenia/cpu/ppc/testing/instr_vcmpgtsw.s
new file mode 100644
index 000000000..63674262c
--- /dev/null
+++ b/src/xenia/cpu/ppc/testing/instr_vcmpgtsw.s
@@ -0,0 +1,53 @@
+test_vcmpgtsw_1:
+  #_ REGISTER_IN v3 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vcmpgtsw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vcmpgtsw_2:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
+  vcmpgtsw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vcmpgtsw_3:
+  #_ REGISTER_IN v3 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
+  vcmpgtsw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vcmpgtsw_4:
+  #_ REGISTER_IN v3 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF]
+  #_ REGISTER_IN v4 [7FFFFFFE, 7FFFFFFE, 7FFFFFFE, 7FFFFFFE]
+  vcmpgtsw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF]
+  #_ REGISTER_OUT v4 [7FFFFFFE, 7FFFFFFE, 7FFFFFFE, 7FFFFFFE]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vcmpgtsw_5:
+  #_ REGISTER_IN v3 [80000000, 80000000, 80000000, 80000000]
+  #_ REGISTER_IN v4 [80000001, 80000001, 80000001, 80000001]
+  vcmpgtsw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 80000000]
+  #_ REGISTER_OUT v4 [80000001, 80000001, 80000001, 80000001]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vcmpgtsw_6:
+  #_ REGISTER_IN v3 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  vcmpgtsw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
diff --git a/src/xenia/cpu/ppc/testing/instr_vcmpgtub.s b/src/xenia/cpu/ppc/testing/instr_vcmpgtub.s
new file mode 100644
index 000000000..53701d5e1
--- /dev/null
+++ b/src/xenia/cpu/ppc/testing/instr_vcmpgtub.s
@@ -0,0 +1,53 @@
+test_vcmpgtub_1:
+  #_ REGISTER_IN v3 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vcmpgtub v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vcmpgtub_2:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vcmpgtub v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vcmpgtub_3:
+  #_ REGISTER_IN v3 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vcmpgtub v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vcmpgtub_4:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  vcmpgtub v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vcmpgtub_5:
+  #_ REGISTER_IN v3 [80808080, 80808080, 80808080, 80808080]
+  #_ REGISTER_IN v4 [81818181, 81818181, 81818181, 81818181]
+  vcmpgtub v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [80808080, 80808080, 80808080, 80808080]
+  #_ REGISTER_OUT v4 [81818181, 81818181, 81818181, 81818181]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vcmpgtub_6:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vcmpgtub v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
diff --git a/src/xenia/cpu/ppc/testing/instr_vcmpgtuh.s b/src/xenia/cpu/ppc/testing/instr_vcmpgtuh.s
new file mode 100644
index 000000000..56c34e404
--- /dev/null
+++ b/src/xenia/cpu/ppc/testing/instr_vcmpgtuh.s
@@ -0,0 +1,53 @@
+test_vcmpgtuh_1:
+  #_ REGISTER_IN v3 [00010001, 00010001, 00010001, 00010001]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vcmpgtuh v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00010001, 00010001, 00010001, 00010001]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vcmpgtuh_2:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
+  vcmpgtuh v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vcmpgtuh_3:
+  #_ REGISTER_IN v3 [00010001, 00010001, 00010001, 00010001]
+  #_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
+  vcmpgtuh v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00010001, 00010001, 00010001, 00010001]
+  #_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vcmpgtuh_4:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [FFFEFFFE, FFFEFFFE, FFFEFFFE, FFFEFFFE]
+  vcmpgtuh v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [FFFEFFFE, FFFEFFFE, FFFEFFFE, FFFEFFFE]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vcmpgtuh_5:
+  #_ REGISTER_IN v3 [80008000, 80008000, 80008000, 80008000]
+  #_ REGISTER_IN v4 [80018001, 80018001, 80018001, 80018001]
+  vcmpgtuh v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [80008000, 80008000, 80008000, 80008000]
+  #_ REGISTER_OUT v4 [80018001, 80018001, 80018001, 80018001]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vcmpgtuh_6:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vcmpgtuh v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
diff --git a/src/xenia/cpu/ppc/testing/instr_vcmpgtuw.s b/src/xenia/cpu/ppc/testing/instr_vcmpgtuw.s
new file mode 100644
index 000000000..8878c9cd1
--- /dev/null
+++ b/src/xenia/cpu/ppc/testing/instr_vcmpgtuw.s
@@ -0,0 +1,62 @@
+test_vcmpgtuw_1:
+  #_ REGISTER_IN v3 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vcmpgtuw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vcmpgtuw_2:
+  #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
+  vcmpgtuw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vcmpgtuw_3:
+  #_ REGISTER_IN v3 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
+  vcmpgtuw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vcmpgtuw_4:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [FFFFFFFE, FFFFFFFE, FFFFFFFE, FFFFFFFE]
+  vcmpgtuw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [FFFFFFFE, FFFFFFFE, FFFFFFFE, FFFFFFFE]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vcmpgtuw_5:
+  #_ REGISTER_IN v3 [80000000, 80000000, 80000000, 80000000]
+  #_ REGISTER_IN v4 [80000001, 80000001, 80000001, 80000001]
+  vcmpgtuw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 80000000]
+  #_ REGISTER_OUT v4 [80000001, 80000001, 80000001, 80000001]
+  #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
+
+test_vcmpgtuw_6:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vcmpgtuw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+  #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vcmpgtuw_7:
+  #_ REGISTER_IN v3 [12345678, 9ABCDEF0, 11223344, 55667788]
+  #_ REGISTER_IN v4 [12345677, 9ABCDEF0, 11223344, 55667788]
+  vcmpgtuw v5, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [12345678, 9ABCDEF0, 11223344, 55667788]
+  #_ REGISTER_OUT v4 [12345677, 9ABCDEF0, 11223344, 55667788]
+  #_ REGISTER_OUT v5 [FFFFFFFF, 00000000, 00000000, 00000000]
diff --git a/src/xenia/cpu/ppc/testing/instr_vrlb.s b/src/xenia/cpu/ppc/testing/instr_vrlb.s
new file mode 100644
index 000000000..62b286f39
--- /dev/null
+++ b/src/xenia/cpu/ppc/testing/instr_vrlb.s
@@ -0,0 +1,63 @@
+test_vrlb_1:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vrlb v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+
+test_vrlb_2:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vrlb v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
+
+test_vrlb_3:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [07070707, 07070707, 07070707, 07070707]
+  vrlb v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [07070707, 07070707, 07070707, 07070707]
+
+test_vrlb_4:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [08080808, 08080808, 08080808, 08080808]
+  vrlb v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [08080808, 08080808, 08080808, 08080808]
+
+test_vrlb_5:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [09090909, 09090909, 09090909, 09090909]
+  vrlb v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [09090909, 09090909, 09090909, 09090909]
+
+test_vrlb_6:
+  #_ REGISTER_IN v3 [80808080, 80808080, 80808080, 80808080]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vrlb v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
+
+test_vrlb_7:
+  #_ REGISTER_IN v3 [01010101, 01010101, 01010101, 01010101]
+  #_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
+  vrlb v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [02020202, 02020202, 02020202, 02020202]
+  #_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
+
+test_vrlb_8:
+  #_ REGISTER_IN v3 [C3C3C3C3, C3C3C3C3, C3C3C3C3, C3C3C3C3]
+  #_ REGISTER_IN v4 [04040404, 04040404, 04040404, 04040404]
+  vrlb v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [3C3C3C3C, 3C3C3C3C, 3C3C3C3C, 3C3C3C3C]
+  #_ REGISTER_OUT v4 [04040404, 04040404, 04040404, 04040404]
diff --git a/src/xenia/cpu/ppc/testing/instr_vrlh.s b/src/xenia/cpu/ppc/testing/instr_vrlh.s
index 1ea7f6241..e72aa12be 100644
--- a/src/xenia/cpu/ppc/testing/instr_vrlh.s
+++ b/src/xenia/cpu/ppc/testing/instr_vrlh.s
@@ -1,4 +1,60 @@
 test_vrlh_1:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vrlh v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+
+test_vrlh_2:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
+  vrlh v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
+
+test_vrlh_3:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [000F000F, 000F000F, 000F000F, 000F000F]
+  vrlh v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [000F000F, 000F000F, 000F000F, 000F000F]
+
+test_vrlh_4:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00100010, 00100010, 00100010, 00100010]
+  vrlh v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00100010, 00100010, 00100010, 00100010]
+
+test_vrlh_5:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00110011, 00110011, 00110011, 00110011]
+  vrlh v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00110011, 00110011, 00110011, 00110011]
+
+test_vrlh_6:
+  #_ REGISTER_IN v3 [80008000, 80008000, 80008000, 80008000]
+  #_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
+  vrlh v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00010001, 00010001, 00010001, 00010001]
+  #_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
+
+test_vrlh_7:
+  #_ REGISTER_IN v3 [00010001, 00010001, 00010001, 00010001]
+  #_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
+  vrlh v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00020002, 00020002, 00020002, 00020002]
+  #_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
+
+test_vrlh_8:
   #_ REGISTER_IN v3 [12345678, 87654321, 11223344, 55667788]
   #_ REGISTER_IN v4 [000D000D, 000D000D, 000D000D, 000D000D]
   vrlh v5, v3, v4
@@ -6,3 +62,11 @@ test_vrlh_1:
   #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788]
   #_ REGISTER_OUT v4 [000D000D, 000D000D, 000D000D, 000D000D]
   #_ REGISTER_OUT v5 [82460ACF, B0EC2864, 42248668, CAAC0EF1]
+
+test_vrlh_9:
+  #_ REGISTER_IN v3 [C003C003, C003C003, C003C003, C003C003]
+  #_ REGISTER_IN v4 [00040004, 00040004, 00040004, 00040004]
+  vrlh v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [003C003C, 003C003C, 003C003C, 003C003C]
+  #_ REGISTER_OUT v4 [00040004, 00040004, 00040004, 00040004]
diff --git a/src/xenia/cpu/ppc/testing/instr_vrlw.s b/src/xenia/cpu/ppc/testing/instr_vrlw.s
new file mode 100644
index 000000000..54eb1040e
--- /dev/null
+++ b/src/xenia/cpu/ppc/testing/instr_vrlw.s
@@ -0,0 +1,71 @@
+test_vrlw_1:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
+  vrlw v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
+
+test_vrlw_2:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
+  vrlw v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
+
+test_vrlw_3:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [0000001F, 0000001F, 0000001F, 0000001F]
+  vrlw v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [0000001F, 0000001F, 0000001F, 0000001F]
+
+test_vrlw_4:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000020, 00000020, 00000020, 00000020]
+  vrlw v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00000020, 00000020, 00000020, 00000020]
+
+test_vrlw_5:
+  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_IN v4 [00000021, 00000021, 00000021, 00000021]
+  vrlw v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+  #_ REGISTER_OUT v4 [00000021, 00000021, 00000021, 00000021]
+
+test_vrlw_6:
+  #_ REGISTER_IN v3 [80000000, 80000000, 80000000, 80000000]
+  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
+  vrlw v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
+
+test_vrlw_7:
+  #_ REGISTER_IN v3 [00000001, 00000001, 00000001, 00000001]
+  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
+  vrlw v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [00000002, 00000002, 00000002, 00000002]
+  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
+
+test_vrlw_8:
+  #_ REGISTER_IN v3 [12345678, 87654321, ABCDEF01, FEDCBA98]
+  #_ REGISTER_IN v4 [00000008, 00000010, 00000004, 0000000C]
+  vrlw v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [34567812, 43218765, BCDEF01A, CBA98FED]
+  #_ REGISTER_OUT v4 [00000008, 00000010, 00000004, 0000000C]
+
+test_vrlw_9:
+  #_ REGISTER_IN v3 [C0000003, C0000003, C0000003, C0000003]
+  #_ REGISTER_IN v4 [00000004, 00000004, 00000004, 00000004]
+  vrlw v3, v3, v4
+  blr
+  #_ REGISTER_OUT v3 [0000003C, 0000003C, 0000003C, 0000003C]
+  #_ REGISTER_OUT v4 [00000004, 00000004, 00000004, 00000004]