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Swapping around vec128 to match AVX order.

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Was really hoping all this would fix some bugs, but no luck :(
This commit is contained in:
Ben Vanik
2014-08-29 20:39:26 -07:00
parent 8ca7642226
commit f74aafeb8a
27 changed files with 2845 additions and 821 deletions
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7
src/alloy/frontend/ppc/ppc_emit_alu.cc
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@@ -1072,7 +1072,7 @@ XEEMITTER(sradx, 0x7C000634, X)(PPCHIRBuilder& f, InstrData& i) {
Value* v = f.LoadGPR(i.X.RT);
Value* sh = f.And(f.Truncate(f.LoadGPR(i.X.RB), INT8_TYPE),
f.LoadConstant((int8_t)0x7F));
f.LoadConstant((int8_t)0x3F));
// CA is set if any bits are shifted out of the right and if the result
// is negative. Start tracking that here.
@@ -1137,14 +1137,15 @@ XEEMITTER(srawx, 0x7C000630, X)(PPCHIRBuilder& f, InstrData& i) {
// if n >= 32: rA <- 64 sign bits of rS, XER[CA] = sign bit of lo_32(rS)
Value* v = f.Truncate(f.LoadGPR(i.X.RT), INT32_TYPE);
Value* sh =
f.And(f.Truncate(f.LoadGPR(i.X.RB), INT32_TYPE), f.LoadConstant(0x7F));
f.And(f.Truncate(f.LoadGPR(i.X.RB), INT32_TYPE), f.LoadConstant(0x1F));
// CA is set if any bits are shifted out of the right and if the result
// is negative.
Value* mask = f.Not(f.Shl(f.LoadConstant(-1), sh));
Value* ca =
f.And(f.Truncate(f.Shr(v, 31), INT8_TYPE), f.IsTrue(f.And(v, mask)));
f.StoreCA(ca);
v = f.Sha(v, sh), v = f.SignExtend(v, INT64_TYPE);
v = f.Sha(v, sh);
v = f.SignExtend(v, INT64_TYPE);
f.StoreGPR(i.X.RA, v);
if (i.X.Rc) {
f.UpdateCR(0, v);