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[GPU] Refactor: Register structs in D3D12CommandProcessor and some other places

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This commit is contained in:
Triang3l
2019-10-19 23:30:53 +03:00
parent 3481f739a1
commit f83269cf8c
17 changed files with 716 additions and 498 deletions
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47
src/xenia/gpu/vulkan/pipeline_cache.cc
View File

@@ -364,7 +364,7 @@ VkPipeline PipelineCache::GetPipeline(const RenderState* render_state,
}
bool PipelineCache::TranslateShader(VulkanShader* shader,
xenos::xe_gpu_program_cntl_t cntl) {
reg::SQ_PROGRAM_CNTL cntl) {
// Perform translation.
// If this fails the shader will be marked as invalid and ignored later.
if (!shader_translator_->Translate(shader, PrimitiveType::kNone, cntl)) {
@@ -808,8 +808,8 @@ bool PipelineCache::SetDynamicState(VkCommandBuffer command_buffer,
}
bool push_constants_dirty = full_update || viewport_state_dirty;
push_constants_dirty |=
SetShadowRegister(&regs.sq_program_cntl, XE_GPU_REG_SQ_PROGRAM_CNTL);
push_constants_dirty |= SetShadowRegister(&regs.sq_program_cntl.value,
XE_GPU_REG_SQ_PROGRAM_CNTL);
push_constants_dirty |=
SetShadowRegister(&regs.sq_context_misc, XE_GPU_REG_SQ_CONTEXT_MISC);
push_constants_dirty |=
@@ -827,25 +827,14 @@ bool PipelineCache::SetDynamicState(VkCommandBuffer command_buffer,
push_constants_dirty |=
SetShadowRegister(&regs.pa_su_point_size, XE_GPU_REG_PA_SU_POINT_SIZE);
if (push_constants_dirty) {
xenos::xe_gpu_program_cntl_t program_cntl;
program_cntl.dword_0 = regs.sq_program_cntl;
// Normal vertex shaders only, for now.
// TODO(benvanik): transform feedback/memexport.
// https://github.com/freedreno/freedreno/blob/master/includes/a2xx.xml.h
// Draw calls skipped if they have unsupported export modes.
// 0 = positionOnly
// 1 = unused
// 2 = sprite
// 3 = edge
// 4 = kill
// 5 = spriteKill
// 6 = edgeKill
// 7 = multipass
assert_true(program_cntl.vs_export_mode == 0 ||
program_cntl.vs_export_mode == 2 ||
program_cntl.vs_export_mode == 7);
assert_false(program_cntl.gen_index_vtx);
assert_true(regs.sq_program_cntl.vs_export_mode ==
xenos::VertexShaderExportMode::kPosition1Vector ||
regs.sq_program_cntl.vs_export_mode ==
xenos::VertexShaderExportMode::kPosition2VectorsSprite ||
regs.sq_program_cntl.vs_export_mode ==
xenos::VertexShaderExportMode::kMultipass);
assert_false(regs.sq_program_cntl.gen_index_vtx);
SpirvPushConstants push_constants = {};
@@ -909,7 +898,8 @@ bool PipelineCache::SetDynamicState(VkCommandBuffer command_buffer,
// Whether to populate a register in the pixel shader with frag coord.
int ps_param_gen = (regs.sq_context_misc >> 8) & 0xFF;
push_constants.ps_param_gen = program_cntl.param_gen ? ps_param_gen : -1;
push_constants.ps_param_gen =
regs.sq_program_cntl.param_gen ? ps_param_gen : -1;
vkCmdPushConstants(command_buffer, pipeline_layout_,
VK_SHADER_STAGE_VERTEX_BIT |
@@ -1061,7 +1051,8 @@ PipelineCache::UpdateStatus PipelineCache::UpdateShaderStages(
bool dirty = false;
dirty |= SetShadowRegister(&regs.pa_su_sc_mode_cntl,
XE_GPU_REG_PA_SU_SC_MODE_CNTL);
dirty |= SetShadowRegister(&regs.sq_program_cntl, XE_GPU_REG_SQ_PROGRAM_CNTL);
dirty |= SetShadowRegister(&regs.sq_program_cntl.value,
XE_GPU_REG_SQ_PROGRAM_CNTL);
dirty |= regs.vertex_shader != vertex_shader;
dirty |= regs.pixel_shader != pixel_shader;
dirty |= regs.primitive_type != primitive_type;
@@ -1073,17 +1064,14 @@ PipelineCache::UpdateStatus PipelineCache::UpdateShaderStages(
return UpdateStatus::kCompatible;
}
xenos::xe_gpu_program_cntl_t sq_program_cntl;
sq_program_cntl.dword_0 = regs.sq_program_cntl;
if (!vertex_shader->is_translated() &&
!TranslateShader(vertex_shader, sq_program_cntl)) {
!TranslateShader(vertex_shader, regs.sq_program_cntl)) {
XELOGE("Failed to translate the vertex shader!");
return UpdateStatus::kError;
}
if (pixel_shader && !pixel_shader->is_translated() &&
!TranslateShader(pixel_shader, sq_program_cntl)) {
!TranslateShader(pixel_shader, regs.sq_program_cntl)) {
XELOGE("Failed to translate the pixel shader!");
return UpdateStatus::kError;
}
@@ -1513,7 +1501,6 @@ PipelineCache::UpdateStatus PipelineCache::UpdateColorBlendState() {
auto& state_info = update_color_blend_state_info_;
bool dirty = false;
dirty |= SetShadowRegister(&regs.rb_colorcontrol, XE_GPU_REG_RB_COLORCONTROL);
dirty |= SetShadowRegister(&regs.rb_color_mask, XE_GPU_REG_RB_COLOR_MASK);
dirty |=
SetShadowRegister(&regs.rb_blendcontrol[0], XE_GPU_REG_RB_BLENDCONTROL_0);
@@ -1568,7 +1555,7 @@ PipelineCache::UpdateStatus PipelineCache::UpdateColorBlendState() {
for (int i = 0; i < 4; ++i) {
uint32_t blend_control = regs.rb_blendcontrol[i];
auto& attachment_state = attachment_states[i];
attachment_state.blendEnable = !(regs.rb_colorcontrol & 0x20);
attachment_state.blendEnable = (blend_control & 0x1FFF1FFF) != 0x00010001;
// A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND
attachment_state.srcColorBlendFactor =
kBlendFactorMap[(blend_control & 0x0000001F) >> 0];

7
src/xenia/gpu/vulkan/pipeline_cache.h
View File

@@ -79,7 +79,7 @@ class PipelineCache {
// state.
VkPipeline GetPipeline(const RenderState* render_state, uint64_t hash_key);
bool TranslateShader(VulkanShader* shader, xenos::xe_gpu_program_cntl_t cntl);
bool TranslateShader(VulkanShader* shader, reg::SQ_PROGRAM_CNTL cntl);
void DumpShaderDisasmAMD(VkPipeline pipeline);
void DumpShaderDisasmNV(const VkGraphicsPipelineCreateInfo& info);
@@ -170,7 +170,7 @@ class PipelineCache {
struct UpdateShaderStagesRegisters {
PrimitiveType primitive_type;
uint32_t pa_su_sc_mode_cntl;
uint32_t sq_program_cntl;
reg::SQ_PROGRAM_CNTL sq_program_cntl;
VulkanShader* vertex_shader;
VulkanShader* pixel_shader;
@@ -256,7 +256,6 @@ class PipelineCache {
VkPipelineDepthStencilStateCreateInfo update_depth_stencil_state_info_;
struct UpdateColorBlendStateRegisters {
uint32_t rb_colorcontrol;
uint32_t rb_color_mask;
uint32_t rb_blendcontrol[4];
uint32_t rb_modecontrol;
@@ -290,7 +289,7 @@ class PipelineCache {
float rb_blend_rgba[4];
uint32_t rb_stencilrefmask;
uint32_t sq_program_cntl;
reg::SQ_PROGRAM_CNTL sq_program_cntl;
uint32_t sq_context_misc;
uint32_t rb_colorcontrol;
uint32_t rb_color_info;