xb format --all (we are now format clean). Buildbot will yell at you.
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Ben Vanik
@@ -265,33 +265,31 @@ inline uint32_t CpuToGpu(uint32_t p) { return p & 0x1FFFFFFF; }
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// XE_GPU_REG_SQ_PROGRAM_CNTL
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typedef union {
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XEPACKEDSTRUCTANONYMOUS({
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uint32_t vs_regs : 6;
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uint32_t : 2;
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uint32_t ps_regs : 6;
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uint32_t : 2;
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uint32_t vs_resource : 1;
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uint32_t ps_resource : 1;
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uint32_t param_gen : 1;
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uint32_t unknown0 : 1;
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uint32_t vs_export_count : 4;
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uint32_t vs_export_mode : 3;
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uint32_t ps_export_depth : 1;
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uint32_t ps_export_count : 3;
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uint32_t gen_index_vtx : 1;
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});
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XEPACKEDSTRUCTANONYMOUS({
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uint32_t dword_0;
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uint32_t vs_regs : 6;
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uint32_t unk_0 : 2;
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uint32_t ps_regs : 6;
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uint32_t unk_1 : 2;
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uint32_t vs_resource : 1;
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uint32_t ps_resource : 1;
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uint32_t param_gen : 1;
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uint32_t unknown0 : 1;
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uint32_t vs_export_count : 4;
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uint32_t vs_export_mode : 3;
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uint32_t ps_export_depth : 1;
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uint32_t ps_export_count : 3;
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uint32_t gen_index_vtx : 1;
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});
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XEPACKEDSTRUCTANONYMOUS({ uint32_t dword_0; });
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} xe_gpu_program_cntl_t;
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// XE_GPU_REG_SHADER_CONSTANT_FETCH_*
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XEPACKEDUNION(xe_gpu_vertex_fetch_t, {
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XEPACKEDSTRUCTANONYMOUS({
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uint32_t type : 2;
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uint32_t address : 30;
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uint32_t endian : 2;
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uint32_t size : 24;
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uint32_t unk1 : 6;
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uint32_t type : 2;
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uint32_t address : 30;
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uint32_t endian : 2;
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uint32_t size : 24;
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uint32_t unk1 : 6;
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});
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XEPACKEDSTRUCTANONYMOUS({
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uint32_t dword_0;
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@@ -302,57 +300,57 @@ XEPACKEDUNION(xe_gpu_vertex_fetch_t, {
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// XE_GPU_REG_SHADER_CONSTANT_FETCH_*
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XEPACKEDUNION(xe_gpu_texture_fetch_t, {
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XEPACKEDSTRUCTANONYMOUS({
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uint32_t type : 2; // dword_0
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uint32_t sign_x : 2;
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uint32_t sign_y : 2;
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uint32_t sign_z : 2;
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uint32_t sign_w : 2;
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uint32_t clamp_x : 3;
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uint32_t clamp_y : 3;
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uint32_t clamp_z : 3;
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uint32_t unk0 : 3;
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uint32_t pitch : 9;
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uint32_t tiled : 1;
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uint32_t format : 6; // dword_1
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uint32_t endianness : 2;
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uint32_t unk1 : 4;
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uint32_t address : 20;
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union { // dword_2
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uint32_t type : 2; // dword_0
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uint32_t sign_x : 2;
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uint32_t sign_y : 2;
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uint32_t sign_z : 2;
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uint32_t sign_w : 2;
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uint32_t clamp_x : 3;
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uint32_t clamp_y : 3;
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uint32_t clamp_z : 3;
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uint32_t unk0 : 3;
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uint32_t pitch : 9;
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uint32_t tiled : 1;
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uint32_t format : 6; // dword_1
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uint32_t endianness : 2;
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uint32_t unk1 : 4;
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uint32_t address : 20;
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union { // dword_2
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struct {
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uint32_t width : 24;
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uint32_t unused : 8;
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uint32_t width : 24;
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uint32_t unused : 8;
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} size_1d;
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struct {
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uint32_t width : 13;
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uint32_t height : 13;
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uint32_t unused : 6;
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uint32_t width : 13;
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uint32_t height : 13;
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uint32_t unused : 6;
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} size_2d;
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struct {
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uint32_t width : 13;
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uint32_t height : 13;
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uint32_t depth : 6;
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uint32_t width : 13;
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uint32_t height : 13;
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uint32_t depth : 6;
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} size_stack;
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struct {
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uint32_t width : 11;
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uint32_t height : 11;
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uint32_t depth : 10;
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uint32_t width : 11;
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uint32_t height : 11;
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uint32_t depth : 10;
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} size_3d;
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};
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uint32_t unk3_0 : 1; // dword_3
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uint32_t swizzle : 12; // xyzw, 3b each (XE_GPU_SWIZZLE)
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uint32_t unk3_1 : 6;
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uint32_t mag_filter : 2;
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uint32_t min_filter : 2;
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uint32_t mip_filter : 2;
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uint32_t unk3_2 : 6;
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uint32_t border : 1;
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uint32_t unk4_0 : 2; // dword_4
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uint32_t mip_min_level : 4;
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uint32_t mip_max_level : 4;
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uint32_t unk4_1 : 22;
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uint32_t unk5 : 9; // dword_5
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uint32_t dimension : 2;
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uint32_t unk5b : 21;
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uint32_t unk3_0 : 1; // dword_3
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uint32_t swizzle : 12; // xyzw, 3b each (XE_GPU_SWIZZLE)
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uint32_t unk3_1 : 6;
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uint32_t mag_filter : 2;
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uint32_t min_filter : 2;
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uint32_t mip_filter : 2;
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uint32_t unk3_2 : 6;
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uint32_t border : 1;
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uint32_t unk4_0 : 2; // dword_4
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uint32_t mip_min_level : 4;
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uint32_t mip_max_level : 4;
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uint32_t unk4_1 : 22;
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uint32_t unk5 : 9; // dword_5
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uint32_t dimension : 2;
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uint32_t unk5b : 21;
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});
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XEPACKEDSTRUCTANONYMOUS({
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uint32_t dword_0;
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@@ -382,20 +380,21 @@ XEPACKEDUNION(xe_gpu_fetch_group_t, {
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});
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XEPACKEDSTRUCTANONYMOUS({
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uint32_t type_0 : 2;
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uint32_t : 30;
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uint32_t : 32;
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uint32_t data_0_a : 30;
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uint32_t data_0_b : 32;
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uint32_t type_1 : 2;
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uint32_t : 30;
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uint32_t : 32;
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uint32_t data_1_a : 30;
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uint32_t data_1_b : 32;
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uint32_t type_2 : 2;
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uint32_t : 30;
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uint32_t : 32;
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uint32_t data_2_a : 30;
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uint32_t data_2_b : 32;
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});
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});
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// Opcodes (IT_OPCODE) for Type-3 commands in the ringbuffer.
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// https://github.com/freedreno/amd-gpu/blob/master/include/api/gsl_pm4types.h
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// Not sure if all of these are used.
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// clang-format off
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enum Type3Opcode {
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PM4_ME_INIT = 0x48, // initialize CP's micro-engine
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@@ -459,16 +458,18 @@ enum Type3Opcode {
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PM4_SET_BIN_SELECT_LO = 0x62,
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PM4_SET_BIN_SELECT_HI = 0x63,
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};
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// clang-format on
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template<uint16_t index, uint16_t count, bool one_reg = false>
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template <uint16_t index, uint16_t count, bool one_reg = false>
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constexpr inline uint32_t MakePacketType0() {
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// ttcccccc cccccccc oiiiiiii iiiiiiii
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static_assert(index <= 0x7FFF, "index must be <= 0x7FFF");
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static_assert(count >= 1 && count <= 0x4000, "count must be >= 1 and <= 0x4000");
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static_assert(count >= 1 && count <= 0x4000,
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"count must be >= 1 and <= 0x4000");
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return (0u << 30) | (((count - 1) & 0x3FFF) << 16) | (index & 0x7FFF);
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}
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template<uint16_t index_1, uint16_t index_2>
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template <uint16_t index_1, uint16_t index_2>
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constexpr inline uint32_t MakePacketType1() {
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// tt?????? ??222222 22222111 11111111
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static_assert(index_1 <= 0x7FF, "index_1 must be <= 0x7FF");
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@@ -481,12 +482,14 @@ constexpr inline uint32_t MakePacketType2() {
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return (2u << 30);
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}
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template<Type3Opcode opcode, uint16_t count, bool predicate = false>
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template <Type3Opcode opcode, uint16_t count, bool predicate = false>
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constexpr inline uint32_t MakePacketType3() {
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// ttcccccc cccccccc ?ooooooo ???????p
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static_assert(opcode <= 0x7F, "opcode must be <= 0x7F");
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static_assert(count >= 1 && count <= 0x4000, "count must be >= 1 and <= 0x4000");
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return (3u << 30) | (((count - 1) & 0x3FFF) << 16) | ((opcode & 0x7F) << 8) | (predicate ? 1 : 0);
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static_assert(count >= 1 && count <= 0x4000,
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"count must be >= 1 and <= 0x4000");
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return (3u << 30) | (((count - 1) & 0x3FFF) << 16) | ((opcode & 0x7F) << 8) |
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(predicate ? 1 : 0);
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}
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} // namespace xenos
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