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lvsl/lvsr tests.

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This commit is contained in:
Ben Vanik
2015-01-11 16:00:16 -08:00
parent 18e458e99a
commit fc39745634
8 changed files with 80 additions and 0 deletions
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src/alloy/frontend/ppc/test/bin/instr_lvsl.bin Normal file
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src/alloy/frontend/ppc/test/bin/instr_lvsl.dis Normal file
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/vagrant/src/alloy/frontend/ppc/test/bin//instr_lvsl.o: file format elf64-powerpc
Disassembly of section .text:
0000000000100000 <test_lvsl_1>:
100000: 7c 64 00 0c lvsl v3,r4,r0
100004: 4e 80 00 20 blr
0000000000100008 <test_lvsl_2>:
100008: 7c 64 00 0c lvsl v3,r4,r0
10000c: 4e 80 00 20 blr
0000000000100010 <test_lvsl_3>:
100010: 7c 64 00 0c lvsl v3,r4,r0
100014: 4e 80 00 20 blr

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src/alloy/frontend/ppc/test/bin/instr_lvsl.map Normal file
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0000000000000000 t test_lvsl_1
0000000000000008 t test_lvsl_2
0000000000000010 t test_lvsl_3

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src/alloy/frontend/ppc/test/bin/instr_lvsr.bin Normal file
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src/alloy/frontend/ppc/test/bin/instr_lvsr.dis Normal file
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/vagrant/src/alloy/frontend/ppc/test/bin//instr_lvsr.o: file format elf64-powerpc
Disassembly of section .text:
0000000000100000 <test_lvsr_1>:
100000: 7c 64 00 4c lvsr v3,r4,r0
100004: 4e 80 00 20 blr
0000000000100008 <test_lvsr_2>:
100008: 7c 64 00 4c lvsr v3,r4,r0
10000c: 4e 80 00 20 blr
0000000000100010 <test_lvsr_3>:
100010: 7c 64 00 4c lvsr v3,r4,r0
100014: 4e 80 00 20 blr

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src/alloy/frontend/ppc/test/bin/instr_lvsr.map Normal file
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0000000000000000 t test_lvsr_1
0000000000000008 t test_lvsr_2
0000000000000010 t test_lvsr_3