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[x64] Remove AVX512 optimization for vrefp

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The precision is too low so it's more trouble than it's worth.
This commit is contained in:
Herman S.
2025-10-25 16:53:31 +09:00
parent 77e320f79a
commit fdb32b909f
1 changed files with 9 additions and 18 deletions
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27
src/xenia/cpu/backend/x64/x64_sequences.cc
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@@ -2156,36 +2156,27 @@ struct RECIP_F32 : Sequence<RECIP_F32, I<OPCODE_RECIP, F32Op, F32Op>> {
static void Emit(X64Emitter& e, const EmitArgType& i) { static void Emit(X64Emitter& e, const EmitArgType& i) {
e.ChangeMxcsrMode(MXCSRMode::Fpu); e.ChangeMxcsrMode(MXCSRMode::Fpu);
Xmm src1 = GetInputRegOrConstant(e, i.src1, e.xmm3); Xmm src1 = GetInputRegOrConstant(e, i.src1, e.xmm3);
if (e.IsFeatureEnabled(kX64EmitAVX512Ortho)) { // AVX512's vrcp14ss has precision issues, division gives exact results
e.vrcp14ss(i.dest, src1, src1); e.vmovaps(e.xmm0, e.GetXmmConstPtr(XMMOne));
} else { e.vdivss(i.dest, e.xmm0, src1);
e.vmovaps(e.xmm0, e.GetXmmConstPtr(XMMOne));
e.vdivss(i.dest, e.xmm0, src1);
}
} }
}; };
struct RECIP_F64 : Sequence<RECIP_F64, I<OPCODE_RECIP, F64Op, F64Op>> { struct RECIP_F64 : Sequence<RECIP_F64, I<OPCODE_RECIP, F64Op, F64Op>> {
static void Emit(X64Emitter& e, const EmitArgType& i) { static void Emit(X64Emitter& e, const EmitArgType& i) {
e.ChangeMxcsrMode(MXCSRMode::Fpu); e.ChangeMxcsrMode(MXCSRMode::Fpu);
Xmm src1 = GetInputRegOrConstant(e, i.src1, e.xmm3); Xmm src1 = GetInputRegOrConstant(e, i.src1, e.xmm3);
if (e.IsFeatureEnabled(kX64EmitAVX512Ortho)) { // AVX512's vrcp14ss has precision issues, division gives exact results
e.vrcp14sd(i.dest, src1, src1); e.vmovapd(e.xmm0, e.GetXmmConstPtr(XMMOnePD));
} else { e.vdivsd(i.dest, e.xmm0, src1);
e.vmovapd(e.xmm0, e.GetXmmConstPtr(XMMOnePD));
e.vdivsd(i.dest, e.xmm0, src1);
}
} }
}; };
struct RECIP_V128 : Sequence<RECIP_V128, I<OPCODE_RECIP, V128Op, V128Op>> { struct RECIP_V128 : Sequence<RECIP_V128, I<OPCODE_RECIP, V128Op, V128Op>> {
static void Emit(X64Emitter& e, const EmitArgType& i) { static void Emit(X64Emitter& e, const EmitArgType& i) {
e.ChangeMxcsrMode(MXCSRMode::Vmx); e.ChangeMxcsrMode(MXCSRMode::Vmx);
Xmm src1 = GetInputRegOrConstant(e, i.src1, e.xmm3); Xmm src1 = GetInputRegOrConstant(e, i.src1, e.xmm3);
if (e.IsFeatureEnabled(kX64EmitAVX512Ortho)) { // AVX512's vrcp14ps has precision issues, devision gives exact results
e.vrcp14ps(i.dest, src1); e.vmovaps(e.xmm0, e.GetXmmConstPtr(XMMOne));
} else { e.vdivps(i.dest, e.xmm0, src1);
e.vmovaps(e.xmm0, e.GetXmmConstPtr(XMMOne));
e.vdivps(i.dest, e.xmm0, src1);
}
} }
}; };
EMITTER_OPCODE_TABLE(OPCODE_RECIP, RECIP_F32, RECIP_F64, RECIP_V128); EMITTER_OPCODE_TABLE(OPCODE_RECIP, RECIP_F32, RECIP_F64, RECIP_V128);