Initial Alloy implementation.
This is a regression in functionality and performance, but a much better foundation for the future of the project (I think). It can run basic apps under an SSA interpreter but doesn't support some of the features required to do real 360 apps yet.
This commit is contained in:
Ben Vanik
577
src/alloy/frontend/ppc/ppc_emit_control.cc
Normal file
577
src/alloy/frontend/ppc/ppc_emit_control.cc
Normal file
@@ -0,0 +1,577 @@
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/*
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******************************************************************************
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* Xenia : Xbox 360 Emulator Research Project *
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******************************************************************************
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* Copyright 2013 Ben Vanik. All rights reserved. *
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* Released under the BSD license - see LICENSE in the root for more details. *
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******************************************************************************
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*/
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#include <alloy/frontend/ppc/ppc_emit-private.h>
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#include <alloy/frontend/ppc/ppc_context.h>
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#include <alloy/frontend/ppc/ppc_function_builder.h>
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using namespace alloy::frontend::ppc;
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using namespace alloy::hir;
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using namespace alloy::runtime;
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namespace alloy {
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namespace frontend {
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namespace ppc {
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int InstrEmit_branch(
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PPCFunctionBuilder& f, const char* src, uint64_t cia,
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Value* nia, bool lk, Value* cond = NULL, bool expect_true = true) {
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uint32_t call_flags = 0;
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// TODO(benvanik): this may be wrong and overwrite LRs when not desired!
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// The docs say always, though...
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// Note that we do the update before we branch/call as we need it to
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// be correct for returns.
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if (lk) {
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f.StoreLR(f.LoadConstant(cia + 4));
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}
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if (!lk) {
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// If LR is not set this call will never return here.
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call_flags |= CALL_TAIL;
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}
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// TODO(benvanik): set CALL_TAIL if !lk and the last block in the fn.
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// This is almost always a jump to restore gpr.
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// TODO(benvanik): detect call-self.
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if (nia->IsConstant()) {
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// Direct branch to address.
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// If it's a block inside of ourself, setup a fast jump.
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uint64_t nia_value = nia->AsUint64() & 0xFFFFFFFF;
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Label* label = f.LookupLabel(nia_value);
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if (label) {
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// Branch to label.
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uint32_t branch_flags = 0;
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if (cond) {
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if (expect_true) {
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f.BranchTrue(cond, label, branch_flags);
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} else {
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f.BranchFalse(cond, label, branch_flags);
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}
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} else {
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f.Branch(label, branch_flags);
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}
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} else {
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// Call function.
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FunctionInfo* symbol_info = f.LookupFunction(nia_value);
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if (cond) {
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if (!expect_true) {
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cond = f.IsFalse(cond);
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}
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f.CallTrue(cond, symbol_info, call_flags);
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} else {
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f.Call(symbol_info, call_flags);
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}
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}
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} else {
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// Indirect branch to pointer.
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if (cond) {
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if (!expect_true) {
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cond = f.IsFalse(cond);
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}
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f.CallIndirectTrue(cond, nia, call_flags);
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} else {
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f.CallIndirect(nia, call_flags);
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}
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}
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return 0;
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}
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XEEMITTER(bx, 0x48000000, I )(PPCFunctionBuilder& f, InstrData& i) {
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// if AA then
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// NIA <- EXTS(LI || 0b00)
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// else
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// NIA <- CIA + EXTS(LI || 0b00)
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// if LK then
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// LR <- CIA + 4
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uint32_t nia;
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if (i.I.AA) {
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nia = (uint32_t)XEEXTS26(i.I.LI << 2);
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} else {
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nia = (uint32_t)(i.address + XEEXTS26(i.I.LI << 2));
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}
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return InstrEmit_branch(
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f, "bx", i.address, f.LoadConstant(nia), i.I.LK);
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}
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XEEMITTER(bcx, 0x40000000, B )(PPCFunctionBuilder& f, InstrData& i) {
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// if ¬BO[2] then
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// CTR <- CTR - 1
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// ctr_ok <- BO[2] | ((CTR[0:63] != 0) XOR BO[3])
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// cond_ok <- BO[0] | (CR[BI+32] ≡ BO[1])
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// if ctr_ok & cond_ok then
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// if AA then
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// NIA <- EXTS(BD || 0b00)
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// else
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// NIA <- CIA + EXTS(BD || 0b00)
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// if LK then
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// LR <- CIA + 4
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// NOTE: the condition bits are reversed!
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// 01234 (docs)
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// 43210 (real)
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Value* ctr_ok = NULL;
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if (XESELECTBITS(i.B.BO, 2, 2)) {
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// Ignore ctr.
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} else {
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// Decrement counter.
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Value* ctr = f.LoadCTR();
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ctr = f.Sub(ctr, f.LoadConstant((int64_t)1));
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f.StoreCTR(ctr);
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// Ctr check.
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// TODO(benvanik): could do something similar to cond and avoid the
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// is_true/branch_true pairing.
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if (XESELECTBITS(i.B.BO, 1, 1)) {
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ctr_ok = f.IsFalse(ctr);
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} else {
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ctr_ok = f.IsTrue(ctr);
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}
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}
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Value* cond_ok = NULL;
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bool not_cond_ok = false;
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if (XESELECTBITS(i.B.BO, 4, 4)) {
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// Ignore cond.
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} else {
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Value* cr = f.LoadCRField(i.B.BI >> 2, i.B.BI & 3);
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cond_ok = cr;
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if (XESELECTBITS(i.B.BO, 3, 3)) {
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// Expect true.
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not_cond_ok = false;
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} else {
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// Expect false.
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not_cond_ok = true;
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}
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}
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// We do a bit of optimization here to make the llvm assembly easier to read.
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Value* ok = NULL;
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bool expect_true = true;
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if (ctr_ok && cond_ok) {
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if (not_cond_ok) {
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cond_ok = f.IsFalse(cond_ok);
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}
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ok = f.And(ctr_ok, cond_ok);
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} else if (ctr_ok) {
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ok = ctr_ok;
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} else if (cond_ok) {
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ok = cond_ok;
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expect_true = !not_cond_ok;
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}
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uint32_t nia;
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if (i.B.AA) {
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nia = (uint32_t)XEEXTS16(i.B.BD << 2);
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} else {
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nia = (uint32_t)(i.address + XEEXTS16(i.B.BD << 2));
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}
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return InstrEmit_branch(
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f, "bcx", i.address, f.LoadConstant(nia), i.B.LK, ok, expect_true);
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}
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XEEMITTER(bcctrx, 0x4C000420, XL )(PPCFunctionBuilder& f, InstrData& i) {
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// cond_ok <- BO[0] | (CR[BI+32] ≡ BO[1])
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// if cond_ok then
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// NIA <- CTR[0:61] || 0b00
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// if LK then
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// LR <- CIA + 4
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// NOTE: the condition bits are reversed!
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// 01234 (docs)
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// 43210 (real)
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Value* cond_ok = NULL;
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bool not_cond_ok = false;
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if (XESELECTBITS(i.XL.BO, 4, 4)) {
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// Ignore cond.
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} else {
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Value* cr = f.LoadCRField(i.XL.BI >> 2, i.XL.BI & 3);
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cond_ok = cr;
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if (XESELECTBITS(i.XL.BO, 3, 3)) {
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// Expect true.
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not_cond_ok = false;
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} else {
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// Expect false.
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not_cond_ok = true;
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}
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}
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bool expect_true = !not_cond_ok;
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return InstrEmit_branch(
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f, "bcctrx", i.address, f.LoadCTR(), i.XL.LK, cond_ok, expect_true);
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}
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XEEMITTER(bclrx, 0x4C000020, XL )(PPCFunctionBuilder& f, InstrData& i) {
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// if ¬BO[2] then
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// CTR <- CTR - 1
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// ctr_ok <- BO[2] | ((CTR[0:63] != 0) XOR BO[3]
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// cond_ok <- BO[0] | (CR[BI+32] ≡ BO[1])
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// if ctr_ok & cond_ok then
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// NIA <- LR[0:61] || 0b00
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// if LK then
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// LR <- CIA + 4
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// NOTE: the condition bits are reversed!
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// 01234 (docs)
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// 43210 (real)
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Value* ctr_ok = NULL;
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if (XESELECTBITS(i.XL.BO, 2, 2)) {
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// Ignore ctr.
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} else {
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// Decrement counter.
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Value* ctr = f.LoadCTR();
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ctr = f.Sub(ctr, f.LoadConstant((int64_t)1));
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f.StoreCTR(ctr);
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// Ctr check.
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// TODO(benvanik): could do something similar to cond and avoid the
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// is_true/branch_true pairing.
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if (XESELECTBITS(i.XL.BO, 1, 1)) {
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ctr_ok = f.IsFalse(ctr);
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} else {
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ctr_ok = f.IsTrue(ctr);
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}
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}
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Value* cond_ok = NULL;
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bool not_cond_ok = false;
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if (XESELECTBITS(i.XL.BO, 4, 4)) {
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// Ignore cond.
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} else {
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Value* cr = f.LoadCRField(i.XL.BI >> 2, i.XL.BI & 3);
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cond_ok = cr;
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if (XESELECTBITS(i.XL.BO, 3, 3)) {
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// Expect true.
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not_cond_ok = false;
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} else {
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// Expect false.
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not_cond_ok = true;
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}
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}
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// We do a bit of optimization here to make the llvm assembly easier to read.
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Value* ok = NULL;
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bool expect_true = true;
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if (ctr_ok && cond_ok) {
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if (not_cond_ok) {
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cond_ok = f.IsFalse(cond_ok);
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}
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ok = f.And(ctr_ok, cond_ok);
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} else if (ctr_ok) {
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ok = ctr_ok;
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} else if (cond_ok) {
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ok = cond_ok;
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expect_true = !not_cond_ok;
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}
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// TODO(benvanik): run a DFA pass to see if we can detect whether this is
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// a normal function return that is pulling the LR from the stack that
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// it set in the prolog. If so, we can omit the dynamic check!
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//// Dynamic test when branching to LR, which is usually used for the return.
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//// We only do this if LK=0 as returns wouldn't set LR.
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//// Ideally it's a return and we can just do a simple ret and be done.
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//// If it's not, we fall through to the full indirection logic.
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//if (!lk && reg == kXEPPCRegLR) {
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// // The return block will spill registers for us.
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// // TODO(benvanik): 'lr_mismatch' debug info.
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// // Note: we need to test on *only* the 32-bit target, as the target ptr may
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// // have garbage in the upper 32 bits.
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// c.cmp(target.r32(), c.getGpArg(1).r32());
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// // TODO(benvanik): evaluate hint here.
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// c.je(e.GetReturnLabel(), kCondHintLikely);
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//}
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if (!i.XL.LK && !ok) {
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// Return (most likely).
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// TODO(benvanik): test? ReturnCheck()?
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f.Return();
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return 0;
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}
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return InstrEmit_branch(
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f, "bclrx", i.address, f.LoadLR(), i.XL.LK, ok, expect_true);
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}
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// Condition register logical (A-23)
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XEEMITTER(crand, 0x4C000202, XL )(PPCFunctionBuilder& f, InstrData& i) {
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XEINSTRNOTIMPLEMENTED();
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return 1;
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}
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XEEMITTER(crandc, 0x4C000102, XL )(PPCFunctionBuilder& f, InstrData& i) {
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XEINSTRNOTIMPLEMENTED();
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return 1;
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}
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XEEMITTER(creqv, 0x4C000242, XL )(PPCFunctionBuilder& f, InstrData& i) {
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XEINSTRNOTIMPLEMENTED();
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return 1;
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}
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XEEMITTER(crnand, 0x4C0001C2, XL )(PPCFunctionBuilder& f, InstrData& i) {
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XEINSTRNOTIMPLEMENTED();
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return 1;
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}
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XEEMITTER(crnor, 0x4C000042, XL )(PPCFunctionBuilder& f, InstrData& i) {
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XEINSTRNOTIMPLEMENTED();
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return 1;
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}
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XEEMITTER(cror, 0x4C000382, XL )(PPCFunctionBuilder& f, InstrData& i) {
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XEINSTRNOTIMPLEMENTED();
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return 1;
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}
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XEEMITTER(crorc, 0x4C000342, XL )(PPCFunctionBuilder& f, InstrData& i) {
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XEINSTRNOTIMPLEMENTED();
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return 1;
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}
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XEEMITTER(crxor, 0x4C000182, XL )(PPCFunctionBuilder& f, InstrData& i) {
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XEINSTRNOTIMPLEMENTED();
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return 1;
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}
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XEEMITTER(mcrf, 0x4C000000, XL )(PPCFunctionBuilder& f, InstrData& i) {
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XEINSTRNOTIMPLEMENTED();
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return 1;
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}
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// System linkage (A-24)
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XEEMITTER(sc, 0x44000002, SC )(PPCFunctionBuilder& f, InstrData& i) {
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XEINSTRNOTIMPLEMENTED();
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return 1;
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}
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// Trap (A-25)
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int InstrEmit_trap(PPCFunctionBuilder& f, InstrData& i,
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Value* va, Value* vb, uint32_t TO) {
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// if (a < b) & TO[0] then TRAP
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// if (a > b) & TO[1] then TRAP
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// if (a = b) & TO[2] then TRAP
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// if (a <u b) & TO[3] then TRAP
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// if (a >u b) & TO[4] then TRAP
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// Bits swapped:
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// 01234
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// 43210
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if (!TO) {
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return 0;
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}
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if (TO & (1 << 4)) {
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// a < b
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f.TrapTrue(f.CompareSLT(va, vb));
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}
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if (TO & (1 << 3)) {
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// a > b
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f.TrapTrue(f.CompareSGT(va, vb));
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}
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if (TO & (1 << 2)) {
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// a = b
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f.TrapTrue(f.CompareEQ(va, vb));
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}
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||||
if (TO & (1 << 1)) {
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||||
// a <u b
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||||
f.TrapTrue(f.CompareULT(va, vb));
|
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}
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if (TO & (1 << 0)) {
|
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// a >u b
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f.TrapTrue(f.CompareUGT(va, vb));
|
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}
|
||||
return 0;
|
||||
}
|
||||
|
||||
XEEMITTER(td, 0x7C000088, X )(PPCFunctionBuilder& f, InstrData& i) {
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// a <- (RA)
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// b <- (RB)
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// if (a < b) & TO[0] then TRAP
|
||||
// if (a > b) & TO[1] then TRAP
|
||||
// if (a = b) & TO[2] then TRAP
|
||||
// if (a <u b) & TO[3] then TRAP
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||||
// if (a >u b) & TO[4] then TRAP
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Value* ra = f.LoadGPR(i.X.RA);
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Value* rb = f.LoadGPR(i.X.RB);
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return InstrEmit_trap(f, i, ra, rb, i.X.RT);
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||||
}
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||||
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XEEMITTER(tdi, 0x08000000, D )(PPCFunctionBuilder& f, InstrData& i) {
|
||||
// a <- (RA)
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// if (a < EXTS(SI)) & TO[0] then TRAP
|
||||
// if (a > EXTS(SI)) & TO[1] then TRAP
|
||||
// if (a = EXTS(SI)) & TO[2] then TRAP
|
||||
// if (a <u EXTS(SI)) & TO[3] then TRAP
|
||||
// if (a >u EXTS(SI)) & TO[4] then TRAP
|
||||
Value* ra = f.LoadGPR(i.D.RA);
|
||||
Value* rb = f.LoadConstant(XEEXTS16(i.D.DS));
|
||||
return InstrEmit_trap(f, i, ra, rb, i.D.RT);
|
||||
}
|
||||
|
||||
XEEMITTER(tw, 0x7C000008, X )(PPCFunctionBuilder& f, InstrData& i) {
|
||||
// a <- EXTS((RA)[32:63])
|
||||
// b <- EXTS((RB)[32:63])
|
||||
// if (a < b) & TO[0] then TRAP
|
||||
// if (a > b) & TO[1] then TRAP
|
||||
// if (a = b) & TO[2] then TRAP
|
||||
// if (a <u b) & TO[3] then TRAP
|
||||
// if (a >u b) & TO[4] then TRAP
|
||||
Value* ra = f.SignExtend(f.Truncate(
|
||||
f.LoadGPR(i.X.RA), INT32_TYPE), INT64_TYPE);
|
||||
Value* rb = f.SignExtend(f.Truncate(
|
||||
f.LoadGPR(i.X.RB), INT32_TYPE), INT64_TYPE);
|
||||
return InstrEmit_trap(f, i, ra, rb, i.X.RT);
|
||||
}
|
||||
|
||||
XEEMITTER(twi, 0x0C000000, D )(PPCFunctionBuilder& f, InstrData& i) {
|
||||
// a <- EXTS((RA)[32:63])
|
||||
// if (a < EXTS(SI)) & TO[0] then TRAP
|
||||
// if (a > EXTS(SI)) & TO[1] then TRAP
|
||||
// if (a = EXTS(SI)) & TO[2] then TRAP
|
||||
// if (a <u EXTS(SI)) & TO[3] then TRAP
|
||||
// if (a >u EXTS(SI)) & TO[4] then TRAP
|
||||
Value* ra = f.SignExtend(f.Truncate(
|
||||
f.LoadGPR(i.D.RA), INT32_TYPE), INT64_TYPE);
|
||||
Value* rb = f.LoadConstant(XEEXTS16(i.D.DS));
|
||||
return InstrEmit_trap(f, i, ra, rb, i.D.RT);
|
||||
}
|
||||
|
||||
|
||||
// Processor control (A-26)
|
||||
|
||||
XEEMITTER(mfcr, 0x7C000026, X )(PPCFunctionBuilder& f, InstrData& i) {
|
||||
XEINSTRNOTIMPLEMENTED();
|
||||
return 1;
|
||||
}
|
||||
|
||||
XEEMITTER(mfspr, 0x7C0002A6, XFX)(PPCFunctionBuilder& f, InstrData& i) {
|
||||
// n <- spr[5:9] || spr[0:4]
|
||||
// if length(SPR(n)) = 64 then
|
||||
// RT <- SPR(n)
|
||||
// else
|
||||
// RT <- i32.0 || SPR(n)
|
||||
Value* v;
|
||||
const uint32_t n = ((i.XFX.spr & 0x1F) << 5) | ((i.XFX.spr >> 5) & 0x1F);
|
||||
switch (n) {
|
||||
case 1:
|
||||
// XER
|
||||
v = f.LoadXER();
|
||||
break;
|
||||
case 8:
|
||||
// LR
|
||||
v = f.LoadLR();
|
||||
break;
|
||||
case 9:
|
||||
// CTR
|
||||
v = f.LoadCTR();
|
||||
break;
|
||||
// 268 + 269 = TB + TBU
|
||||
default:
|
||||
XEINSTRNOTIMPLEMENTED();
|
||||
return 1;
|
||||
}
|
||||
f.StoreGPR(i.XFX.RT, v);
|
||||
return 0;
|
||||
}
|
||||
|
||||
XEEMITTER(mftb, 0x7C0002E6, XFX)(PPCFunctionBuilder& f, InstrData& i) {
|
||||
Value* time;
|
||||
LARGE_INTEGER counter;
|
||||
if (QueryPerformanceCounter(&counter)) {
|
||||
time = f.LoadConstant(counter.QuadPart);
|
||||
} else {
|
||||
time = f.LoadZero(INT64_TYPE);
|
||||
}
|
||||
f.StoreGPR(i.XFX.RT, time);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
XEEMITTER(mtcrf, 0x7C000120, XFX)(PPCFunctionBuilder& f, InstrData& i) {
|
||||
XEINSTRNOTIMPLEMENTED();
|
||||
return 1;
|
||||
}
|
||||
|
||||
XEEMITTER(mtspr, 0x7C0003A6, XFX)(PPCFunctionBuilder& f, InstrData& i) {
|
||||
// n <- spr[5:9] || spr[0:4]
|
||||
// if length(SPR(n)) = 64 then
|
||||
// SPR(n) <- (RS)
|
||||
// else
|
||||
// SPR(n) <- (RS)[32:63]
|
||||
|
||||
Value* rt = f.LoadGPR(i.XFX.RT);
|
||||
|
||||
const uint32_t n = ((i.XFX.spr & 0x1F) << 5) | ((i.XFX.spr >> 5) & 0x1F);
|
||||
switch (n) {
|
||||
case 1:
|
||||
// XER
|
||||
f.StoreXER(rt);
|
||||
break;
|
||||
case 8:
|
||||
// LR
|
||||
f.StoreLR(rt);
|
||||
break;
|
||||
case 9:
|
||||
// CTR
|
||||
f.StoreCTR(rt);
|
||||
break;
|
||||
default:
|
||||
XEINSTRNOTIMPLEMENTED();
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
void RegisterEmitCategoryControl() {
|
||||
XEREGISTERINSTR(bx, 0x48000000);
|
||||
XEREGISTERINSTR(bcx, 0x40000000);
|
||||
XEREGISTERINSTR(bcctrx, 0x4C000420);
|
||||
XEREGISTERINSTR(bclrx, 0x4C000020);
|
||||
XEREGISTERINSTR(crand, 0x4C000202);
|
||||
XEREGISTERINSTR(crandc, 0x4C000102);
|
||||
XEREGISTERINSTR(creqv, 0x4C000242);
|
||||
XEREGISTERINSTR(crnand, 0x4C0001C2);
|
||||
XEREGISTERINSTR(crnor, 0x4C000042);
|
||||
XEREGISTERINSTR(cror, 0x4C000382);
|
||||
XEREGISTERINSTR(crorc, 0x4C000342);
|
||||
XEREGISTERINSTR(crxor, 0x4C000182);
|
||||
XEREGISTERINSTR(mcrf, 0x4C000000);
|
||||
XEREGISTERINSTR(sc, 0x44000002);
|
||||
XEREGISTERINSTR(td, 0x7C000088);
|
||||
XEREGISTERINSTR(tdi, 0x08000000);
|
||||
XEREGISTERINSTR(tw, 0x7C000008);
|
||||
XEREGISTERINSTR(twi, 0x0C000000);
|
||||
XEREGISTERINSTR(mfcr, 0x7C000026);
|
||||
XEREGISTERINSTR(mfspr, 0x7C0002A6);
|
||||
XEREGISTERINSTR(mftb, 0x7C0002E6);
|
||||
XEREGISTERINSTR(mtcrf, 0x7C000120);
|
||||
XEREGISTERINSTR(mtspr, 0x7C0003A6);
|
||||
}
|
||||
|
||||
|
||||
} // namespace ppc
|
||||
} // namespace frontend
|
||||
} // namespace alloy
|
||||
Reference in New Issue
Block a user