Triang3l
|
c8f3c93802
|
[D3D12] Don't create multiple command lists as they're just encoders
|
2019-11-06 08:06:12 +03:00 |
|
Triang3l
|
c499229455
|
[GPU] Store an EDRAM snapshot in traces
|
2019-11-04 17:30:20 +03:00 |
|
Triang3l
|
9deb710607
|
[D3D12] CP: Framework for multiple command lists per frame
|
2019-10-31 23:33:11 +03:00 |
|
Triang3l
|
6e5a0ebf7b
|
[D3D12] CP: Separate guest frame and non-frame submissions
|
2019-10-28 22:00:59 +03:00 |
|
Triang3l
|
d3b6f71ae1
|
[D3D12] Don't use D3D12Context for command processor fence
|
2019-10-28 10:49:32 +03:00 |
|
Triang3l
|
b4af63fe31
|
[D3D12] Detach UploadBufferPool and DescriptorHeapPool from D3D12Context
|
2019-10-27 20:53:53 +03:00 |
|
Triang3l
|
f23ba862f6
|
[D3D12] Trace viewer entry point
|
2019-10-27 00:37:33 +03:00 |
|
Triang3l
|
f75d927cc5
|
[D3D12] Resolve fetch memory read tracing
|
2019-10-25 09:17:08 +03:00 |
|
Triang3l
|
c057b5a032
|
[D3D12] Make trace dump partially work
|
2019-10-25 08:38:06 +03:00 |
|
Triang3l
|
4623b41023
|
[D3D12] Trace guest memory operations
|
2019-10-23 23:33:50 +03:00 |
|
Triang3l
|
a9ed73bdd1
|
[GPU] Remove most hardcoded register/instruction layouts from common and D3D12 code
|
2019-10-20 19:40:37 +03:00 |
|
Triang3l
|
f83269cf8c
|
[GPU] Refactor: Register structs in D3D12CommandProcessor and some other places
|
2019-10-19 23:32:38 +03:00 |
|
Triang3l
|
352f12f92e
|
[D3D12] Switch from gflags to cvars
|
2019-08-03 16:53:23 +03:00 |
|
Triang3l
|
90c9c24ca5
|
[D3D12] Add d3d12_readback_resolve gflag
|
2019-08-01 08:55:47 +03:00 |
|
Triang3l
|
7a88789ebd
|
[D3D12] RB_STENCILREFMASK_BF and stencil constants cleanup
|
2019-07-14 23:49:30 +03:00 |
|
Triang3l
|
4825e69fda
|
[D3D12] Cleanup primitive types and front/back facing
|
2019-07-13 22:25:03 +03:00 |
|
Triang3l
|
35c8b66c93
|
[D3D12] Add forgotten shader implicit early Z check
|
2019-07-11 10:15:33 +03:00 |
|
Triang3l
|
6672997108
|
[D3D12] ROV early Z and full rewrite, shader scalar optimizations
|
2019-07-11 09:31:58 +03:00 |
|
Triang3l
|
8f51855c8f
|
Revert "[D3D12] Re-add accidentally deleted RT update trigger and treat Z test and write bits separately"
This reverts commit 25cc189e99.
|
2019-04-12 20:04:50 +03:00 |
|
Triang3l
|
25cc189e99
|
[D3D12] Re-add accidentally deleted RT update trigger and treat Z test and write bits separately
|
2019-04-12 19:13:03 +03:00 |
|
Triang3l
|
ecc056912d
|
[D3D12] Don't drop draw calls with no render targets
|
2019-04-12 16:59:45 +03:00 |
|
Triang3l
|
93a18a517b
|
[D3D12] Place UAV barriers for the EDRAM ROV when layout changes
|
2019-04-12 15:59:09 +03:00 |
|
Triang3l
|
5e30f3a947
|
[D3D12] User clip planes and constant/signature refactoring
|
2019-04-10 16:37:06 +03:00 |
|
Triang3l
|
57e8f05234
|
[D3D12] Make RG16/RGBA16 RTVs range switchable
|
2019-01-29 14:39:04 +03:00 |
|
Triang3l
|
ba7b6d6081
|
[D3D12] Memexport CPU readback, disabled by default
|
2019-01-25 16:33:25 +03:00 |
|
Triang3l
|
0a9feb5eca
|
[D3D12] ROV: Alpha to coverage (without dithering)
|
2019-01-21 21:28:26 +03:00 |
|
Triang3l
|
b7bcdf3e8b
|
[D3D12] Pre-create EDRAM and shared memory buffer descriptors
|
2019-01-17 16:39:51 +03:00 |
|
Triang3l
|
a1a1110784
|
[D3D12] Non-indexed line loops
|
2019-01-15 14:19:59 +03:00 |
|
Triang3l
|
17dfd84f71
|
[D3D12] Free two alphatest-related system constant dwords
|
2019-01-15 12:58:36 +03:00 |
|
Triang3l
|
ef523823d5
|
[D3D12] Force early Z with DSV, fix blend disabled flag in rb_colorcontrol ignored
|
2019-01-11 17:07:33 +03:00 |
|
Triang3l
|
8ad12480a4
|
[D3D12] Copy index buffer to a scratch buffer for memexporting draws
|
2019-01-09 13:19:49 +03:00 |
|
Triang3l
|
890228b6f3
|
[D3D12] Prototype multithreaded PSO creation
|
2019-01-04 00:30:11 +03:00 |
|
Triang3l
|
364cae6cc8
|
[D3D12] Use deferred command list
|
2019-01-03 15:08:49 +03:00 |
|
Triang3l
|
1cea4062c0
|
[D3D12] Rewrite pipeline cache for compact storage of pipeline descriptions
|
2019-01-01 22:20:50 +03:00 |
|
Triang3l
|
928e46c8b2
|
[D3D12] Adaptive tessellation of triangle patches
|
2018-12-29 20:53:41 +03:00 |
|
Triang3l
|
ed09cac440
|
[D3D12] DXBC: vfetch RoundIndex, vertex index signedness fixes
|
2018-12-28 08:11:34 +03:00 |
|
Triang3l
|
e803ee84d5
|
[D3D12] Bind shared memory as UAV with memexport
|
2018-12-22 15:39:47 +03:00 |
|
Triang3l
|
6025599d3b
|
[D3D12] Request memory for memexport in shared memory
|
2018-12-22 00:57:31 +03:00 |
|
Triang3l
|
090bf8e353
|
[D3D12] Change RT in the title to something less ambiguous and more googlable
|
2018-12-20 20:48:15 +03:00 |
|
Triang3l
|
c84511a5f1
|
[GPU/D3D12] Update tessellation enums
|
2018-12-19 18:23:54 +03:00 |
|
Triang3l
|
2b646ff425
|
[D3D12] Fake per-edge tessellation with continuous
|
2018-12-12 22:12:32 +03:00 |
|
Triang3l
|
7698944673
|
[D3D12] Swap red and blue in 8bpp gamma ramp
|
2018-12-09 15:53:57 +03:00 |
|
Triang3l
|
9427667a27
|
[D3D12] Experimental 2x resolution scale
|
2018-12-06 10:38:13 +03:00 |
|
Triang3l
|
355d33dadd
|
[D3D12] Rename feature gflags
|
2018-11-25 23:25:56 +03:00 |
|
Triang3l
|
9a58841219
|
[D3D12] ROV: Use MSAA instead of SSAA
|
2018-11-25 16:37:38 +03:00 |
|
Triang3l
|
c061836649
|
[D3D12] Enable ROV by default
|
2018-11-20 21:30:36 +03:00 |
|
Triang3l
|
66a37c0cc3
|
[D3D12] ROV: Aliasing and bounds checking, retc instead of discard
|
2018-11-17 17:15:15 +03:00 |
|
Triang3l
|
5e51306660
|
[D3D12] Integer texture comment and UpdateSystemConstantValues cleanup
|
2018-11-14 16:45:31 +03:00 |
|
Triang3l
|
5a79f675bd
|
[D3D12] ROV: Unbind resolve RT after using
|
2018-11-01 22:13:45 +03:00 |
|
Triang3l
|
cabffea4d7
|
[D3D12] Write pixel, not sample, position to ps_param_gen
|
2018-10-24 17:08:15 +03:00 |
|