Commit Graph

83 Commits

Author SHA1 Message Date
goldislead
d119505289 [GPU] Texture integer scaling fetches; 8_8_8_8_GAMMA resolve
Integer num_format fetches now get their scale CPU-side instead of trying to guess in the shader. This is authoritative; no cvar. Both translators now use texture_integer_scale_bits after signs/gamma and before exponent bias. This alone fixes black screens and a bunch of rendering bugs across at least several dozen titles.

This new information lives in the updated FormatInfo table, including fixed component widths.

Resolve also has two new fixes.

8_8_8_8_GAMMA EDRAM sources can now decode through the PWL curve while still in linear space, before MSAA resolve or format conversion, then re-encoded for gamma destinations. This is also now default enabled via gamma_decode_pwl_resolve and has improved blowout in at least 4 titles, with no obvious regressions thus far.

Full resolve can also now pack fixed destinations according to copy_dest_number.
2026-07-06 20:51:02 +02:00
Herman S.
fdd583eced [GPU/WGF] Fix resolve_fast_32bpp_4xmsaa sample addressing
For 4xMSAA 32bpp, samples 2/3 add a +4 byte horizontal offset to the
EDRAM address. The old typed buffer code (Buffer<uint4>) implicitly
truncated this offset via integer division (>> 2), and the .yw swizzle
compensated by selecting odd elements within the aligned uint4 load.

After the ByteAddressBuffer conversion, Load4 uses the exact byte
address including the +4 offset, shifting the load window by one dword.
The .yw swizzle then picks samples from the wrong pixels, causing
visual artifacts like vertical streaks in Resident Evil 5.

Fix by aligning the load address down to 16 bytes and selecting the
swizzle based on whether the address was offset.
2026-03-15 17:24:16 +09:00
Herman S.
5845f3437b [GPU] Async shader compilation for D3D12 and Vulkan
Adds async_shader_compilation cvar (default true) that forces new
pipelines to be created async from the main thread, skips draws entirely
on D3D12 and on vulkan replaces pixel shader with placeholder until the
real one is ready. Causes some visual artifacts on first load but
greatly reduces load times and stutter.
2026-03-10 00:24:26 +09:00
Herman S.
65d42843b6 Merge remote-tracking branch 'xenia-master/master' into canary_experimental 2026-03-06 23:05:24 +09:00
Herman S.
16d2cc05c5 [GPU] Use UNorm not signed EDRAM encoding in k_16_16 resolve packing.
The original commit (2eea146b) correctly added kXenosFormat_16_16_EDRAM
case labels and fixed the unpack clamp from -1.0 to -32.0, but
incorrectly changed the resolve pack functions from UNorm to signed EDRAM
encoding. The resolve destination is a regular texture sampled as UNorm
[0,1], not EDRAM. Using EDRAM packing double-encodes the [-32,32]
scaling, crushing all values by ~64x and caused visual issues
particularly in UE3 titles.

The bytecode submitted with the change was actually correct, but the
source had additional incorrect pieces that only manifested when shaders
were rebuilt.
2026-03-05 15:11:22 +09:00
Herman S.
f2ac39cfd9 [Build] Generate shaders on build instead of having them checked in 2026-03-03 16:21:30 +09:00
Ylederman153
2eea146b1b [GPU] Fix k_16_16 and k_16_16_16_16 EDRAM packing clamping (#898)
Replaces the UNorm packing functions with custom Edram functions to preserve the native [-32.0, 32.0] float range and scale mathematically instead of using saturate(). Fixes displaced water meshes in games like Mercenaries 2.
2026-03-03 14:27:04 +09:00
Triang3l
80dad41454 [GPU/WGF] Use ByteAddressBuffer in precompiled shaders
Drivers and hardware may provide more optimal paths for untyped buffers
compared to typed.

Also, ByteAddressBuffer may be bound via a root descriptor in Direct3D 12,
greatly simplifying the binding logic.

ByteAddressBuffer also doesn't have the 128 * 2^20 element count limit that
typed and structured buffers have, and doesn't require the structure stride
to be specified at resource creation time in Direct3D 11.
2026-02-17 23:28:42 +03:00
Herman S.
83d776fa39 [Vulkan] Add tesselation support
Pretty much just following the D3D12 implementation
2026-02-18 00:02:21 +09:00
Triang3l
cec9ca0ef2 [GPU] 8-bit PWL gamma RT as linear 16-bit UNorm on the host
With render target HLE, directly store linear values as R16G16B16A16_UNORM
without gamma conversion, as this format provides more than enough bits
(need at least 11 per component due to the maximum scale being 2^3 in the
piecewise linear gamma curve) to represent linear values without precision
loss.

This makes blending work correctly in linear space, improving quality of
transparency, lighting passes, and fixing issues such as transparent parts
of impact and footstep decals in 4D5307E6 being bright instead.

The new behavior is enabled by default, as it hugely improves the accuracy
of emulation of this format, that is pretty commonplace in Xbox 360 games,
with likely just a small GPU memory and bandwidth usage increase, compared
to the alternatives that were previously available on the HLE RB path.

It's currently implemented only on Direct3D 12, as most of the current GPU
emulation code is planned to be phased out and redone, and no methods other
than 8-bit with pre-conversion were implemented on Vulkan previously.

To implement on Vulkan later, same conversion as in the Direct3D 12
implementation will need to be done in ownership transfer and resolve
shaders. Currently it's somewhat inconvenient to decouple the conversion
functions in `SpirvShaderTranslator` from an instance of the translator due
to vector constant usage. Later, simpler SPIR-V generation functions may be
added (`spv::Builder` usage in general is overly verbose).

The previously default method (8-bit storage with pre-conversion in shaders
and incorrect blending) can be re-enabled by setting the
"gamma_render_target_as_unorm16" configuration option to `false`. This may
be useful if the game, for instance, switches between 8_8_8_8_GAMMA and
8_8_8_8 formats for the same data frequently, as switching will result in
EDRAM range ownership transfer data copying now. Also, the old path is
preserved for Vulkan devices not supporting R16G16B16A16_UNORM with
blending.

The other workaround that was available previously, replacing the PWL
encoding with host hardware sRGB with linear-space blending in render
target management and in texture fetching, was also inherently inaccurate
in many ways (especially when games have their own PWL encoding math, like
4541080F that displayed incorrect colors on the loading screen), and
required tracking of the encoding needed for ranges in the memory.

The sRGB workaround therefore was deleted in this commit, greatly
simplifying the code in the parts of render target, texture and memory
management and shader generation that were involved in it.
2026-01-18 16:22:22 +03:00
Triang3l
f2fabfdf04 [GPU] Change "bpe" to "bpb" (bytes per block) in comments
Forgotten in the other "element" to "block" change.
2026-01-15 20:48:26 +03:00
Triang3l
88f95a8bd6 [GPU] Change "element" name back to "block" in texture addressing
The 32_32_32_FLOAT format seems to be vertex-only, so it looks like there
can't be storage elements smaller than a single texel.

So, use a more precise name that can't be confused with "picture element"
(pixel) or "texture element" (texel) that represents a single logical pixel
rather than a storage block of pixels.
2026-01-15 11:56:45 +03:00
Triang3l
9535e610b0 [GPU] Change texture address local X offsetting back to addition
More likely to be emitted as an immediate load/store offset in host
hardware shaders.
2026-01-14 00:15:08 +03:00
Triang3l
6db6192170 [GPU] Use XOR to flip X texel group in all load/resolve shaders
For visual consistency (missed in the commit that added LocalXAddressXor).
2026-01-13 23:37:01 +03:00
Triang3l
7db772bfeb [GPU] XeResolveLocalXAddressXor comment typo correction 2026-01-13 23:22:30 +03:00
Triang3l
0f23f05683 [GPU] Simplify local X offsetting with resolution scaling
Switch between even and odd 16-byte element sequences along X by simply
flipping a bit rather than going to a different resolution-scaled group of
pixels, by increasing the size of the group within the constraints imposed
by tiling.
2026-01-13 23:14:15 +03:00
Triang3l
76c531bff2 [GPU] Rename AddressTiled in TiledAddress in shaders
There will possibly be more `XenosTextureTiled*` functions in the future
where the word "Address" would make the names excessively long.
2026-01-13 21:20:26 +03:00
Triang3l
80a9af4277 [GPU] Add macro tile size constants to texture addressing headers 2026-01-13 21:18:25 +03:00
Triang3l
28b69c21be [GPU] Document tiled texture address bits
Will be useful for calculating memory extents more precisely in the future.
2026-01-06 17:47:19 +03:00
Triang3l
cbbaae8ead [Vulkan] Recompile internal shaders with Vulkan SDK 1.4.335.0
spirv-remap was replaced with spirv-opt --canonicalize-ids, and debug
information is preserved now.
2026-01-04 17:03:37 +03:00
Triang3l
0b2ffa3148 [GPU] Change texture load cbuffer to push constants
Simplify the code, eliminating the need for supporting requesting cbuffers
for anything other than guest draw command execution.
2025-08-20 12:46:26 +03:00
Triang3l
04d5c40d0d [GPU/UI] XeSL readability improvements + float suffix
Use the _xe suffix instead of the xesl_ prefix for quicker visual
recognition of identifiers, also switch to snake_case for consistency.

Also add the f suffix to float32 literals because the Metal Shading
Language is based on C++.
2025-08-19 21:36:06 +03:00
Triang3l
37579d3bf0 [GPU] Treat non-adaptive-tessellated patches as 1-control-point 2022-07-24 17:38:26 +03:00
Triang3l
3c12814276 [GPU] EDRAM looped addressing (resolves #2031) 2022-07-22 23:51:50 +03:00
Triang3l
1a95bef8b3 [GPU] Eliminate unused shader I/O, UCP culling, centroid on Vulkan
For more optimal usage of exports and the parameter cache on the host regardless of how effective the optimizations in the host GPU driver are. Also reserve space for Vulkan/Metal/D3D11-specific HostVertexShaderTypes to use one more bit for the host vertex shader type in the shader modification bits, so that won't have to be done in the future as that would require invalidating shader storages (which are invalidated by this commit) again.
2022-07-21 12:32:28 +03:00
Triang3l
14fdf4b270 [GPU] Up to 7x7 resolution scaling 2022-07-17 20:41:50 +03:00
Triang3l
4b4205ba00 [Vulkan] Frontbuffer presentation 2022-06-25 14:33:43 +03:00
Triang3l
3fc7d8753c Merge branch 'master' into vulkan 2022-06-24 23:38:04 +03:00
Triang3l
f4a634c617 [XeSL] xesl_write*Store > xesl_*Store 2022-06-24 23:37:29 +03:00
Triang3l
7a4732e14f [GPU] XeSL swap shaders 2022-06-24 23:24:30 +03:00
Triang3l
0d8bd0e0c6 Merge branch 'master' into vulkan 2022-06-22 13:15:50 +03:00
Triang3l
7869b080d3 [D3D12] Truncate depth to float24 in EDRAM range ownership transfers and resolves by default
Doesn't ruin the "greater or equal" depth test in subsequent rendering passes if precision is lost, unlike rounding to the nearest
2022-06-22 12:53:09 +03:00
Triang3l
61c4c49d76 Merge branch 'master' into vulkan 2022-06-20 12:34:41 +03:00
Triang3l
b61953374e [GPU] Make resolve EDRAM binding DS 0 and rename it
Ordering the descriptor sets by the change frequency on Vulkan, in increasing order (the opposite of D3D12 root signatures). The EDRAM binding never changes there (always one storage buffer), while the destination buffer binding may become changeable in the future (to split dispatches if exceeding `maxStorageBufferRange`, for example).
2022-06-20 12:15:52 +03:00
Triang3l
1200b205cf Merge branch 'master' into vulkan 2022-06-19 17:52:28 +03:00
Triang3l
9b83d3d0f4 [GPU] XeSL resolve shaders + host depth store width fix 2022-06-19 17:50:21 +03:00
Triang3l
166be463be [XeSL] Metal Shading Language definitions 2022-06-16 21:39:16 +03:00
Triang3l
1ce45ee150 Merge branch 'master' into vulkan 2022-06-02 22:50:14 +03:00
Triang3l
84fcd5defa [GPU] Fix resolve destination offset and extent calculation 2022-06-02 21:47:30 +03:00
Triang3l
4c2f8764d6 Merge branch 'master' into vulkan 2022-05-23 12:36:35 +03:00
Triang3l
c1f15c86a3 [GPU] Decompress GBGR/BGRG into RGBB, not RGB1
While the alpha of the texture data is not used at all (replaced with blue using the view swizzle), still make the shader code state the intention more explicitly if the format is decompressed for use as signed. Unsigned 1.0 is 0xFF, while signed 1.0 is 0x7F.
2022-05-23 12:31:45 +03:00
Triang3l
888d5044e0 [GPU] 2x1-subsampled texture RGBA8 conversion shader 2022-05-22 21:07:38 +03:00
Triang3l
d3561d2f47 [D3D12] Pre-swizzle 2x1-subsampled formats 2022-05-22 20:31:48 +03:00
Triang3l
5de825e3a0 [GPU] Prevent multiple evaluation of XE_TEXTURE_LOAD_TRANSFORM arguments 2022-05-22 19:48:23 +03:00
Triang3l
2f0a884438 [GPU] Add k prefix to texture load group size constants 2022-05-22 19:35:25 +03:00
Triang3l
6aa30ed074 [GPU] 128-thread groups in all texture load shaders
Vulkan's minimum requirement (maxComputeWorkGroupInvocations) is 128.
2022-05-22 18:03:09 +03:00
Triang3l
73d574a046 [Vulkan] Rectangle and quad list geometry shader generation 2022-05-10 21:48:18 +03:00
Triang3l
b9256fcdbd Merge branch 'master' into vulkan 2022-05-10 15:57:50 +03:00
Triang3l
8f0e751909 [D3D12] Runtime geometry shader generation 2022-05-09 19:16:22 +03:00
Triang3l
c794d0d538 [GPU] DC_LUT_RW_INDEX/WRITE_EN_MASK + gamma ramp and registers in traces 2022-05-05 13:10:29 +03:00