Commit Graph

13 Commits

Author SHA1 Message Date
goldislead
d119505289 [GPU] Texture integer scaling fetches; 8_8_8_8_GAMMA resolve
Integer num_format fetches now get their scale CPU-side instead of trying to guess in the shader. This is authoritative; no cvar. Both translators now use texture_integer_scale_bits after signs/gamma and before exponent bias. This alone fixes black screens and a bunch of rendering bugs across at least several dozen titles.

This new information lives in the updated FormatInfo table, including fixed component widths.

Resolve also has two new fixes.

8_8_8_8_GAMMA EDRAM sources can now decode through the PWL curve while still in linear space, before MSAA resolve or format conversion, then re-encoded for gamma destinations. This is also now default enabled via gamma_decode_pwl_resolve and has improved blowout in at least 4 titles, with no obvious regressions thus far.

Full resolve can also now pack fixed destinations according to copy_dest_number.
2026-07-06 20:51:02 +02:00
Triang3l
80dad41454 [GPU/WGF] Use ByteAddressBuffer in precompiled shaders
Drivers and hardware may provide more optimal paths for untyped buffers
compared to typed.

Also, ByteAddressBuffer may be bound via a root descriptor in Direct3D 12,
greatly simplifying the binding logic.

ByteAddressBuffer also doesn't have the 128 * 2^20 element count limit that
typed and structured buffers have, and doesn't require the structure stride
to be specified at resource creation time in Direct3D 11.
2026-02-17 23:28:42 +03:00
Triang3l
88f95a8bd6 [GPU] Change "element" name back to "block" in texture addressing
The 32_32_32_FLOAT format seems to be vertex-only, so it looks like there
can't be storage elements smaller than a single texel.

So, use a more precise name that can't be confused with "picture element"
(pixel) or "texture element" (texel) that represents a single logical pixel
rather than a storage block of pixels.
2026-01-15 11:56:45 +03:00
Triang3l
9535e610b0 [GPU] Change texture address local X offsetting back to addition
More likely to be emitted as an immediate load/store offset in host
hardware shaders.
2026-01-14 00:15:08 +03:00
Triang3l
7db772bfeb [GPU] XeResolveLocalXAddressXor comment typo correction 2026-01-13 23:22:30 +03:00
Triang3l
0f23f05683 [GPU] Simplify local X offsetting with resolution scaling
Switch between even and odd 16-byte element sequences along X by simply
flipping a bit rather than going to a different resolution-scaled group of
pixels, by increasing the size of the group within the constraints imposed
by tiling.
2026-01-13 23:14:15 +03:00
Triang3l
76c531bff2 [GPU] Rename AddressTiled in TiledAddress in shaders
There will possibly be more `XenosTextureTiled*` functions in the future
where the word "Address" would make the names excessively long.
2026-01-13 21:20:26 +03:00
Triang3l
28b69c21be [GPU] Document tiled texture address bits
Will be useful for calculating memory extents more precisely in the future.
2026-01-06 17:47:19 +03:00
Triang3l
04d5c40d0d [GPU/UI] XeSL readability improvements + float suffix
Use the _xe suffix instead of the xesl_ prefix for quicker visual
recognition of identifiers, also switch to snake_case for consistency.

Also add the f suffix to float32 literals because the Metal Shading
Language is based on C++.
2025-08-19 21:36:06 +03:00
Triang3l
3c12814276 [GPU] EDRAM looped addressing (resolves #2031) 2022-07-22 23:51:50 +03:00
Triang3l
14fdf4b270 [GPU] Up to 7x7 resolution scaling 2022-07-17 20:41:50 +03:00
Triang3l
b61953374e [GPU] Make resolve EDRAM binding DS 0 and rename it
Ordering the descriptor sets by the change frequency on Vulkan, in increasing order (the opposite of D3D12 root signatures). The EDRAM binding never changes there (always one storage buffer), while the destination buffer binding may become changeable in the future (to split dispatches if exceeding `maxStorageBufferRange`, for example).
2022-06-20 12:15:52 +03:00
Triang3l
9b83d3d0f4 [GPU] XeSL resolve shaders + host depth store width fix 2022-06-19 17:50:21 +03:00