* Add unit tests
* Use `dc zva` to zero out entire cache-lines worth of data, when possible
* Special instruction that zaps an entire cache-line into being zero-values, typically 64-bytes at a time
* Statically read and initialize the `DCZID_EL0` register value since reading registers with `mrs` can be kinda slow and isn't worth doing redundantly at JIT-time when it never changes.
* Update store-instructions to use inline post-increments to avoid an additional `add` instruction and keep encoded instruction immediates small
Pretty much every arm processor has a cache line size of 64 bytes, so a typical `dcbz128` to clear 128-bytes of data now results in:
```
dc zva, x0
add x0, x0, 64
dc zva, x0
```
rather than a sequence of 8 `stp xzr, xzr, ...` instructions
Adds `platform_arm64` similar to `platform_arm64` to populate a 64-bit feature-flag value and creates a `a64_extension_mask` configuration-mask for the detection and utilization of certain arm ISA features. The first feature being `FEAT_LSE` which maps to `XBYAK_AARCH64_HWCAP_ATOMIC`.
Just like the x64 backend, implements `IsFeatureEnabled` to the emitter for checking if the host processor supports a certain subset of feature flag(s) at once.
Optimizes `OPCODE_ATOMIC_EXCHANGE`, `OPCODE_ATOMIC_COMPARE_EXCHANGE`,
and `OPCODE_RESERVED_STORE` with `FEAT_LSE` instructions.
Reserves x19 to permanently hold the A64BackendContext pointer
(x20 - sizeof(A64BackendContext)), set once in the HostToGuestThunk.
Since x19 is AAPCS64 callee-saved, it survives all host calls for free.
Eliminates repeated 2-instruction mov+sub sequences in stackpoint
push/pop, stack synchronization, FPCR management, and reserved
load/store paths.
Reduces allocatable GPRs from 8 to 7 (like on x64).
Based entirely off existing xbyak x86 implementation and available
tests. Still needs a lot of optimization and testing on non-Windows
platforms.
So far passes all tests and boots at least some games on Windows.
