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3ad80810b5ab11248580d71bf0b04a8754d0ab46
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143 Commits

Author SHA1 Message Date
chrisps
3ad80810b5 Optimized CONVERT_I64_TO_F64 with neat overflow trick 
Reduced instruction count from 11 to 8, eliminated a movq stall.
 2022-06-17 11:10:48 +02:00
Joel Linn
00e7de9297 [CPU] Improve vrsqrtefp accuracy 2022-02-16 17:09:28 -06:00
Joel Linn
d64848245d [CPU] Improve vrefp accuracy 2022-02-16 17:09:28 -06:00
Wunkolo
37aa3d129c [x64] Explicitly handle AND_NOT dest == src1 
This addresses a JIT-issue in the case that the `src1` and `dest`
register are both the same. This issue only happens in the "generic"
x86 path but not in the BMI1-accelerated path.

Thanks Rick for the extensive debugging help.

When `src1` and `dest` were the same, then the `addc` instruction at
`82099A08` in title `584108FF` might emit the following assembly:
```
.text:82099A08                 andc      r11, r10, r11
  |
  | Jitted
  |
  V
00000000A0011B15  mov         rbx,r10
00000000A0011B18  not         rbx
00000000A0011B1B  and         rbx,rbx
```

This was due to the src1 operand and the destination register being the
same, which used to call the "else" case in the x64 emitter when it
needs to be handled explicitly due to register aliasing/allocation.

Addresses issue #1945
 2022-01-10 15:48:49 -06:00
Wunkolo
4303f6b200 [x64] Fix OPCODE_AND_NOT src1-constant case 
Fix the the case where src1 is constant and src2 is non-constant causing
an assert due to trying to call `.constant()` on the src2 operand.
Interfaces with an issue Gliniak was encountering where title `4D53082D`
encounters an assert. Also includes a BMI1-acceleration in the 64-bit
case where a temporary register is needed(the `and` x86 instruction only
supports immediate constants up to 32-bits).
 2022-01-06 13:00:58 -06:00
Wunkolo
24d4e1e0e5 [x64] Add BMI1-based acceleration for AndNot 
In the case of having two register operands for `AndNot`, the `andn` instruction can be used when the host supports `BMI1`. `andn` only supports 32-bit and 64-bit operands, so some register up-casting is needed.
 2022-01-04 16:16:49 -06:00
Wunkolo
0fdb855a11 [JIT, x64] Add and implement OPCODE_AND_NOT 
Verified the x64 implementation using `xenia-cpu-ppc-tests`.
 2022-01-04 16:16:49 -06:00
gibbed
326220309b [x64] Handle constant in LOG2_F32/F64/V128. 2020-11-27 05:34:08 -06:00
gibbed
a48bb71c2f Overhaul logging. 2020-04-07 16:09:41 -05:00
gibbed
aa28430786 [x64] NAN up vmsum3fp128/vmsum4fp128. 
It seems vmsum3fp128/vmsum4fp128 need to output a NAN on overflow.

Do so. Probably inefficiently.
 2020-02-24 18:13:07 -06:00
gibbed
a6e6f0f7bf Lint cleanup. 2020-02-22 13:29:07 -06:00
Joel Linn
922f1f220a [CPU] Implement mftb instruction natively. 
When the cvars clock_no_scaling and clock_source_raw are set, tick counts will be directly calculated in the emitted code.
 2019-12-01 17:11:58 -06:00
Dr. Chat
b3d509eb01 [x64] Swap to using anchor variables instead of dummy function calls 2018-11-23 18:02:04 -06:00
Dr. Chat
b57bb74965 [x64] Change the parameters to host_to_guest_thunk 
Shuffle some code around in x64_backend.cc
Add GetNativeParam to avoid hardcoding parameters
 2018-11-23 18:02:04 -06:00
Dr. Chat
b2f9d54e7e [x64] Factor out memory handling code 2018-11-23 18:02:03 -06:00
Dr. Chat
bb74114cab [x64] Factor out control code 2018-11-23 18:02:03 -06:00
Dr. Chat
c318009733 [x64] Factor out vector handling code 2018-11-23 18:02:03 -06:00
Dr. Chat
6861cce492 [x64] Factor out a lot of the opcode handling code 2018-11-23 18:02:02 -06:00
Dr. Chat
696c3cd439 [x64] Remove most of RegisterSequences 2018-11-23 18:02:02 -06:00
gibbed
4c53bc5c9a [x64] Fix Travis whining. 2018-11-23 12:03:09 -06:00
gibbed
996093e499 [x64] Support constant src1 for Int32 VECTOR_SHL_V128/VECTOR_SHR_V128. 2018-11-23 09:33:30 -06:00
Margen67
896ac4a682 Update documentation. 
- Convert http to https, provide archive link when possible.
- Made CPU-JIT.png more readable on dark themes;
Added a white background so there isn't black text on a black
background.
 2018-11-22 09:20:09 -06:00
gibbed
4436616e6d [x64] Use constant a bit earlier in VECTOR_SHL_V128. 2018-11-18 08:17:04 -06:00
gibbed
44f194be35 [x64] Fix constant access in VECTOR_SHL_V128. 2018-11-18 08:13:37 -06:00
Triang3l
dd19701dc4 [CPU] Unify constant operand checks in pack/unpack 2018-06-18 13:55:46 +03:00
Triang3l
c89cc6a229 [CPU] vupkd3d: NaN on negative overflow and tests 2018-06-11 21:34:13 +03:00
Triang3l
0378f532ab [CPU] Fix W in 2101010 vupkd3d and revert untested saturation 2018-06-11 17:22:15 +03:00
Triang3l
06fcdef968 [CPU] Bring back saturation in D3DCOLOR vpkd3d128 2018-05-31 16:17:27 +03:00
Triang3l
d61aff4389 [CPU] v(u)pkd3d128: Support UINT_2101010 and don't saturate D3DCOLOR 
Fix broken mesh polygons in the Call of Duty series. Also remove saturation of D3DCOLOR when packing because values near 3 may be accepted, while unpacking D3DCOLOR gives values near 1.
 2018-05-31 14:42:11 +03:00
DrChat
157c7780af [JIT] Add V128 ADD/SUB (fixes #1095) 2018-03-03 18:24:57 -06:00
DrChat
1c1fdb4ccd [JIT] Properly mask NaNs in vctsxs 2018-03-03 14:06:45 -06:00
DrChat
3a8f8f2ecb [JIT] Fix OPCODE_SELECT V128 with certain combinations of constants 2018-03-02 18:56:28 -06:00
DrChat
fd0d2185ef [JIT] Full support for vcfux 2018-03-02 15:11:29 -06:00
DrChat
b0b920c040 Linting. 2018-03-02 12:14:09 -06:00
DrChat
6c97dbaf81 [JIT] Simplify VECTOR_ADD/SUB i32 with saturate 2018-03-02 11:48:19 -06:00
DrChat
131fcd1320 [JIT] Kill a couple instructions in VECTOR_CONVERT_F2I 2018-03-02 11:41:04 -06:00
DrChat
0577b6c9be [JIT] Full vctuxs support 2018-03-01 23:49:44 -06:00
DrChat
6fd75cea91 [CPU] Handle constant multiply in fmadd/fmsub in constant propagation pass 2018-03-01 20:04:56 -06:00
DrChat
43f9cebb0c [JIT] Rewrite CNTLZ and remove one branch 2018-02-16 12:51:39 -06:00
DrChat
e54c24e150 [JIT] New opcodes: OPCODE_LOAD_OFFSET and OPCODE_STORE_OFFSET 
These take full advantage of x86 addressing, and eliminate extra add operations.
 2018-02-14 16:26:49 -06:00
DrChat
1d0b290c3d [JIT] Remove all calls to ReloadMembase / ReloadContext (rcx/rdx free now) 2018-02-13 13:33:39 -06:00
DrChat
e2bbae3896 [JIT] Don't bother using a temp for constant addresses < 0x80000000 2018-02-13 13:09:40 -06:00
DrChat
9e79babde0 Formatting. 2018-02-07 18:55:26 -06:00
DrChat
26212bffb0 [x64 seq] Reuse the source variable rather than re-specifying the destination (to make things less confusing) 2018-01-24 20:57:11 -06:00
DrChat
aaf281351d Format all code with new clang-format 2017-12-14 20:44:43 -06:00
Dr. Chat
8d261ca73d x64 JIT: Simplify splats 2017-08-08 00:12:38 -05:00
Dr. Chat
7a3af9b2c4 PPC: Fix vsl[b/h/w] and vsr[b/h/w] with variable shift amounts. 2017-05-15 11:08:09 -05:00
Dr. Chat
6ea6b8b51d x64: Change binary strings to actual binary numbers. 2017-05-14 09:28:58 -05:00
Dr. Chat
d3ed53c43e PPC: Support v[u]pkd3d128 VPACK_NORMSHORT4 2017-05-12 17:55:52 -05:00
Dr. Chat
82efbd7bc5 HIR: Add opcode SET_ROUNDING_MODE (taking FPSCR as an argument) 2017-05-12 14:05:27 -05:00