Commit Graph

170 Commits

Author SHA1 Message Date
Triang3l
53f98d1fe6 [GPU/D3D12] Memexport from anywhere in control flow + 8/16bpp memexport
There's no limit on the number of memory exports in a shader on the real
Xenos, and exports can be done anywhere, including in loops. Now, instead
of deferring the exports to the end of the shader, and assuming that export
allocs are executed only once, Xenia flushes exports when it reaches an
alloc (allocs terminate memory exports on Xenos, as well as individual ALU
instructions with `serialize`, but not handling this case for simplicity,
it's only truly mandatory to flush memory exports before starting a new
one), the end of the shader, or a pixel with outstanding exports is killed.

To know which eM# registers need to be flushed to the memory, traversing
the successors of each exec potentially writing any eM#, and specifying
that certain eM# registers might have potentially been written before each
reached control flow instruction, until a flush point or the end of the
shader is reached.

Also, some games export to sub-32bpp formats. These are now supported via
atomic AND clearing the bits of the dword to replace followed by an atomic
OR inserting the new byte/short.
2023-05-05 21:32:02 +03:00
Triang3l
75d805245d [DXBC] discard pixels from kill with ROV instead of returning
Keep the current lane active as it may be needed for derivatives.
2023-04-09 20:13:22 +03:00
Triang3l
45050b2380 [GPU] Vulkan fragment shader interlock RB and related fixes/cleanup
Also fixes addressing of MSAA samples 2 and 3 for 64bpp color render targets in the ROV RB implementation on Direct3D 12.
Additionally, with FSI/ROV, alpha test and alpha to coverage are done only if the render target 0 was dynamically written to (according to the Direct3D 9 rules for writing to color render targets, though not sure if they actually apply to the alpha tests on Direct3D 9, but for safety).
There is also some code cleanup for things spotted during the development of the feature.
2022-10-09 22:06:41 +03:00
Triang3l
37579d3bf0 [GPU] Treat non-adaptive-tessellated patches as 1-control-point 2022-07-24 17:38:26 +03:00
Triang3l
3c12814276 [GPU] EDRAM looped addressing (resolves #2031) 2022-07-22 23:51:50 +03:00
Triang3l
1a95bef8b3 [GPU] Eliminate unused shader I/O, UCP culling, centroid on Vulkan
For more optimal usage of exports and the parameter cache on the host regardless of how effective the optimizations in the host GPU driver are. Also reserve space for Vulkan/Metal/D3D11-specific HostVertexShaderTypes to use one more bit for the host vertex shader type in the shader modification bits, so that won't have to be done in the future as that would require invalidating shader storages (which are invalidated by this commit) again.
2022-07-21 12:32:28 +03:00
Triang3l
e0b890fe5c [DXBC] Remove alphatest/A2C with [earlydepthstencil] 2022-06-26 15:31:08 +03:00
Triang3l
7869b080d3 [D3D12] Truncate depth to float24 in EDRAM range ownership transfers and resolves by default
Doesn't ruin the "greater or equal" depth test in subsequent rendering passes if precision is lost, unlike rounding to the nearest
2022-06-22 12:53:09 +03:00
Triang3l
56f72da137 [GPU] More exact PWL texture/RT gamma conversion 2022-06-07 21:26:34 +03:00
Triang3l
7675b6b140 [DXBC] Cleanup texture/sampler name setting 2022-05-17 22:30:55 +03:00
Triang3l
a65fd4f673 [GPU] Shader::IsHostVertexShaderTypeDomain 2022-05-15 16:13:05 +03:00
Triang3l
0e0f04dc1d [D3D12] Fix point size calculation + point code cleanup
6fcf9d21fe made per-vertex diameter vs. constant radius consistent, and with that commit the shader works with direct pixel to NDC conversion, however, the NDC conversion factor was outdated in that commit (still included the 0.5 factor for diameter to radius conversion, resulting in all points being 50% narrower along each axis than needed). Now, the diameter to radius conversion factor is used there properly, and also the multiplication of the per-vertex diameter by 0.5 has been removed from the shader since the constant already includes it now (the constant diameter is passed via the system constants instead of the radius also).
2022-05-04 13:26:30 +03:00
Triang3l
6fcf9d21fe [D3D12] Point sprite size fixes, point/line bits in PsParamGen 2022-05-03 16:15:16 +03:00
Triang3l
38aca269e1 [GPU] Offset and clamp tessellation patch index (#2008, thanks @deaklajos) 2022-04-14 13:04:34 +03:00
Triang3l
32ab1a2df1 [D3D12] Minor RT code style/comments cleanup 2022-03-22 21:48:26 +03:00
Triang3l
d6188c5d7e [GPU] Reuse base+index*stride in vfetch_mini instead of reloading the index GPR
The wheel shader in 4D530910 does vfetch_full to r0 with the index from r0.x, and then vfetch_mini.
Thanks @Gliniak for the finding :3
Also small formatting cleanup in commented-out code.
2022-01-09 14:58:38 +03:00
Triang3l
38b4741c8f [GPU] Mostly generic, not square-only resolution scaling 2021-12-11 21:55:33 +03:00
Triang3l
fdec0ab332 [Code] Make union usage more consistent 2021-11-03 20:45:09 +03:00
Triang3l
3f156f26c4 [D3D12] Take 0 being bottom-right sample with 2x MSAA in D3D12 into account 2021-06-06 20:58:50 +03:00
Triang3l
dce6938827 [D3D12] ROV sample depth via ddxy(z), DSV depth bias cleanup 2021-06-06 18:27:43 +03:00
Triang3l
538aa91015 [GPU] Primitive processor with Vulkan 1.0 base cases, 24-bit indices and clamping 2021-06-04 23:57:46 +03:00
Triang3l
9f8a432479 [DXBC] Cleanup: kSysConst_*_Vec/Comp > LoadSystemConstant 2021-05-16 17:43:18 +03:00
Triang3l
fb01ccaac6 [GPU] Viewport/clipping cleanup, don't clamp oDepth 2021-05-04 21:39:34 +03:00
Triang3l
913e1e949c [GPU] Ownership-transfer-based RT cache, 3x3 resolution scaling
The ROV path is also disabled by default because of lower performance
2021-04-26 22:12:09 +03:00
Triang3l
9a74df491f [DXBC] dxbc.h with non-translator-specific parts 2021-01-04 16:15:50 +03:00
Triang3l
e6fa0ad139 [GPU] Dynamic r# count via shader modifications + refactoring 2020-12-19 16:14:54 +03:00
Triang3l
34c5fc9c2f [DXBC] ROV: Update a todo comment about early Z 2020-12-10 12:41:29 +03:00
Triang3l
bc0c2040e2 [DXBC] ROV: Force late Z write with kill instructions 2020-12-10 12:36:37 +03:00
Triang3l
9a4643d0f2 [GPU] Non-ROV f24 trunc/round, host shader modifications, cache dir 2020-12-07 22:31:46 +03:00
Triang3l
44a3f200c3 [GPU] Rename PrimitiveTwoFaced to PrimitivePolygonal, add rects to it and ignore fill modes for non-polygons 2020-11-19 23:55:49 +03:00
Triang3l
10d7bcde93 [GPU] Viewport in draw_util with host API flexibility 2020-11-16 23:03:42 +03:00
Triang3l
7e9e37bd09 [DXBC] Remove dxbc_source_map cvar export 2020-10-08 23:08:40 +03:00
Triang3l
a1d33615b0 [DXBC] Inline depth/stencil test 2020-08-27 23:46:41 +03:00
Triang3l
6dc94d9154 [DXBC] ROV: Inline color ROP 2020-08-16 17:10:07 +03:00
Triang3l
bd5f77bc3b [GPU] Common resolve code based on compute shaders, swap MSAA samples 1 and 2, change ROV write rounding, random refactoring 2020-08-09 21:33:10 +03:00
Triang3l
b84239d507 [GPU] xenos.h: max texture size, interpolators 2020-07-11 18:56:56 +03:00
Triang3l
4bb0ca0e09 [GPU] Move all xenos.h to gpu::xenos, disambiguate Dimension/TextureDimension 2020-07-11 15:54:22 +03:00
Triang3l
1547b9df41 [D3D12] Interpolation at centroid 2020-07-08 23:20:36 +03:00
Triang3l
829c6ee2b0 [D3D12] Dithered alpha to coverage 2020-07-07 23:09:53 +03:00
Triang3l
0fbf0eec9d [DXBC] ROV: Inline 24-bit depth conversion 2020-07-05 22:50:24 +03:00
Triang3l
40e335e2a9 [D3D12] Bindless textures/samplers 2020-06-19 23:52:33 +03:00
Triang3l
9f789e01b6 [DXBC] Fix and cleanup depth-only PS register usage 2020-06-07 15:21:31 +03:00
Triang3l
8a64861ec0 [DXBC] New tfetch: pre-swizzle signs, additive LOD + refactoring 2020-06-06 19:12:34 +03:00
Triang3l
3879ff29b3 [DXBC/GPU] vfetch to new codegen, signed vfetch offset, fix AND with system flags 2020-05-23 17:15:11 +03:00
Triang3l
0d14ae01bb [D3D12] Allow non-adaptive tessellation for patch primitive types, and all triangle and quad tessellation modes 2020-05-11 22:40:52 +03:00
Triang3l
814990f686 [DXBC] ALU scalar ops to new codegen 2020-05-10 20:57:33 +03:00
Triang3l
b79ba69548 [DXBC] ALU vector ops to new codegen 2020-05-10 16:33:39 +03:00
Triang3l
3aa0ce3096 [GPU] Shader translator refactoring (mostly ALU), fixes for disassembly round trip and write masks 2020-05-08 23:57:51 +03:00
Triang3l
96a61bc623 [DXBC] All prologues and epilogues to new DXBC code 2020-04-26 13:51:25 +03:00
Triang3l
1799585e92 [DXBC] Control flow to new DXBC code 2020-04-25 19:30:01 +03:00