Commit Graph

58 Commits

Author SHA1 Message Date
Herman S.
65d42843b6 Merge remote-tracking branch 'xenia-master/master' into canary_experimental 2026-03-06 23:05:24 +09:00
Herman S.
067641668f [GPU] Fix min/max blend operations to properly apply factors
Applies factors before the MIN/MAX operation - in FSI/ROV via runtime
blending, in FBO/RTV by pre-multiplying shader output when dstFactor is
ONE only, as we don't have access to dest to provide full support as we
do in the FSI/ROV paths.
2026-02-25 09:39:03 +09:00
Triang3l
cec9ca0ef2 [GPU] 8-bit PWL gamma RT as linear 16-bit UNorm on the host
With render target HLE, directly store linear values as R16G16B16A16_UNORM
without gamma conversion, as this format provides more than enough bits
(need at least 11 per component due to the maximum scale being 2^3 in the
piecewise linear gamma curve) to represent linear values without precision
loss.

This makes blending work correctly in linear space, improving quality of
transparency, lighting passes, and fixing issues such as transparent parts
of impact and footstep decals in 4D5307E6 being bright instead.

The new behavior is enabled by default, as it hugely improves the accuracy
of emulation of this format, that is pretty commonplace in Xbox 360 games,
with likely just a small GPU memory and bandwidth usage increase, compared
to the alternatives that were previously available on the HLE RB path.

It's currently implemented only on Direct3D 12, as most of the current GPU
emulation code is planned to be phased out and redone, and no methods other
than 8-bit with pre-conversion were implemented on Vulkan previously.

To implement on Vulkan later, same conversion as in the Direct3D 12
implementation will need to be done in ownership transfer and resolve
shaders. Currently it's somewhat inconvenient to decouple the conversion
functions in `SpirvShaderTranslator` from an instance of the translator due
to vector constant usage. Later, simpler SPIR-V generation functions may be
added (`spv::Builder` usage in general is overly verbose).

The previously default method (8-bit storage with pre-conversion in shaders
and incorrect blending) can be re-enabled by setting the
"gamma_render_target_as_unorm16" configuration option to `false`. This may
be useful if the game, for instance, switches between 8_8_8_8_GAMMA and
8_8_8_8 formats for the same data frequently, as switching will result in
EDRAM range ownership transfer data copying now. Also, the old path is
preserved for Vulkan devices not supporting R16G16B16A16_UNORM with
blending.

The other workaround that was available previously, replacing the PWL
encoding with host hardware sRGB with linear-space blending in render
target management and in texture fetching, was also inherently inaccurate
in many ways (especially when games have their own PWL encoding math, like
4541080F that displayed incorrect colors on the loading screen), and
required tracking of the encoding needed for ranges in the memory.

The sRGB workaround therefore was deleted in this commit, greatly
simplifying the code in the parts of render target, texture and memory
management and shader generation that were involved in it.
2026-01-18 16:22:22 +03:00
Maks
1a4746f261 [GPU] Reduced fuzzy alpha epsilon 2024-03-02 13:08:42 +01:00
maksloboda
9e86750bae [GPU] Add aproximate alpha test 2024-02-18 22:31:10 +01:00
Triang3l
45050b2380 [GPU] Vulkan fragment shader interlock RB and related fixes/cleanup
Also fixes addressing of MSAA samples 2 and 3 for 64bpp color render targets in the ROV RB implementation on Direct3D 12.
Additionally, with FSI/ROV, alpha test and alpha to coverage are done only if the render target 0 was dynamically written to (according to the Direct3D 9 rules for writing to color render targets, though not sure if they actually apply to the alpha tests on Direct3D 9, but for safety).
There is also some code cleanup for things spotted during the development of the feature.
2022-10-09 22:06:41 +03:00
Triang3l
3c12814276 [GPU] EDRAM looped addressing (resolves #2031) 2022-07-22 23:51:50 +03:00
Triang3l
1a95bef8b3 [GPU] Eliminate unused shader I/O, UCP culling, centroid on Vulkan
For more optimal usage of exports and the parameter cache on the host regardless of how effective the optimizations in the host GPU driver are. Also reserve space for Vulkan/Metal/D3D11-specific HostVertexShaderTypes to use one more bit for the host vertex shader type in the shader modification bits, so that won't have to be done in the future as that would require invalidating shader storages (which are invalidated by this commit) again.
2022-07-21 12:32:28 +03:00
Triang3l
7e691d5ef1 [DXBC] Handle NaN in not equal alpha test as passed 2022-06-30 22:15:01 +03:00
Triang3l
e0b890fe5c [DXBC] Remove alphatest/A2C with [earlydepthstencil] 2022-06-26 15:31:08 +03:00
Triang3l
7869b080d3 [D3D12] Truncate depth to float24 in EDRAM range ownership transfers and resolves by default
Doesn't ruin the "greater or equal" depth test in subsequent rendering passes if precision is lost, unlike rounding to the nearest
2022-06-22 12:53:09 +03:00
Triang3l
e2f632f8fa [D3D12] Use udiv by constant tile size + minor transfer cleanup
Drivers compile that to a multiplication and a shift anyway.
2022-06-20 22:39:30 +03:00
Triang3l
56f72da137 [GPU] More exact PWL texture/RT gamma conversion 2022-06-07 21:26:34 +03:00
Triang3l
d280b3953d [GPU] Texture object/binding management to common superclass 2022-05-14 16:18:10 +03:00
Triang3l
e3425b242e [DXBC] Both v[#] and v[#][#] operands for HS and GS 2022-05-07 16:17:17 +03:00
Triang3l
32ab1a2df1 [D3D12] Minor RT code style/comments cleanup 2022-03-22 21:48:26 +03:00
Triang3l
38b4741c8f [GPU] Mostly generic, not square-only resolution scaling 2021-12-11 21:55:33 +03:00
Triang3l
e720e0a540 [Code] Remove game names from code comments (most of at least) 2021-09-05 21:27:40 +03:00
Triang3l
3f156f26c4 [D3D12] Take 0 being bottom-right sample with 2x MSAA in D3D12 into account 2021-06-06 20:58:50 +03:00
Triang3l
dce6938827 [D3D12] ROV sample depth via ddxy(z), DSV depth bias cleanup 2021-06-06 18:27:43 +03:00
Triang3l
538aa91015 [GPU] Primitive processor with Vulkan 1.0 base cases, 24-bit indices and clamping 2021-06-04 23:57:46 +03:00
Triang3l
9f8a432479 [DXBC] Cleanup: kSysConst_*_Vec/Comp > LoadSystemConstant 2021-05-16 17:43:18 +03:00
Triang3l
fb01ccaac6 [GPU] Viewport/clipping cleanup, don't clamp oDepth 2021-05-04 21:39:34 +03:00
Triang3l
913e1e949c [GPU] Ownership-transfer-based RT cache, 3x3 resolution scaling
The ROV path is also disabled by default because of lower performance
2021-04-26 22:12:09 +03:00
Triang3l
9a74df491f [DXBC] dxbc.h with non-translator-specific parts 2021-01-04 16:15:50 +03:00
Triang3l
e6fa0ad139 [GPU] Dynamic r# count via shader modifications + refactoring 2020-12-19 16:14:54 +03:00
Triang3l
bc0c2040e2 [DXBC] ROV: Force late Z write with kill instructions 2020-12-10 12:36:37 +03:00
Triang3l
9a4643d0f2 [GPU] Non-ROV f24 trunc/round, host shader modifications, cache dir 2020-12-07 22:31:46 +03:00
Triang3l
74804ae710 [DXBC] ROV: Fix depth being overwritten if stencil failed 2020-09-05 19:23:45 +03:00
Triang3l
a1d33615b0 [DXBC] Inline depth/stencil test 2020-08-27 23:46:41 +03:00
Triang3l
6dc94d9154 [DXBC] ROV: Inline color ROP 2020-08-16 17:10:07 +03:00
Triang3l
bd5f77bc3b [GPU] Common resolve code based on compute shaders, swap MSAA samples 1 and 2, change ROV write rounding, random refactoring 2020-08-09 21:33:10 +03:00
Triang3l
4bb0ca0e09 [GPU] Move all xenos.h to gpu::xenos, disambiguate Dimension/TextureDimension 2020-07-11 15:54:22 +03:00
Triang3l
829c6ee2b0 [D3D12] Dithered alpha to coverage 2020-07-07 23:09:53 +03:00
Triang3l
0fbf0eec9d [DXBC] ROV: Inline 24-bit depth conversion 2020-07-05 22:50:24 +03:00
Triang3l
40e335e2a9 [D3D12] Bindless textures/samplers 2020-06-19 23:52:33 +03:00
Triang3l
9f789e01b6 [DXBC] Fix and cleanup depth-only PS register usage 2020-06-07 15:21:31 +03:00
Triang3l
a10bd2a5c1 [DXBC] Unbreak MRT in RTV output path 2020-03-27 23:18:15 +03:00
Triang3l
b59ae30ec3 [D3D12] DXBC: Fix two uninitialized register usages in ROV code, better comments 2020-02-13 08:31:01 +03:00
Triang3l
014d03193e [D3D12] Convert dxbc_shader_translator_om.cc to new DXBC emission code 2020-02-10 23:50:26 +03:00
Triang3l
85fb028faa [D3D12] Cleaner DXBC emission code, port ROV prologue to it 2020-02-07 09:42:43 +03:00
Triang3l
7a88789ebd [D3D12] RB_STENCILREFMASK_BF and stencil constants cleanup 2019-07-14 23:49:30 +03:00
Triang3l
929ecfa15c [D3D12] ROV: Fix stencil test result being ignored for depth 2019-07-13 12:27:15 +03:00
Triang3l
6672997108 [D3D12] ROV early Z and full rewrite, shader scalar optimizations 2019-07-11 09:31:58 +03:00
Triang3l
93a18a517b [D3D12] Place UAV barriers for the EDRAM ROV when layout changes 2019-04-12 15:59:09 +03:00
Triang3l
9dd62c1e15 [D3D12] Alpha to coverage (w/o dithering) with RTV, tiny AtoC fixes 2019-01-21 23:41:47 +03:00
Triang3l
0a9feb5eca [D3D12] ROV: Alpha to coverage (without dithering) 2019-01-21 21:28:26 +03:00
Triang3l
17dfd84f71 [D3D12] Free two alphatest-related system constant dwords 2019-01-15 12:58:36 +03:00
Triang3l
77e9ab342c [D3D12] DXBC: Don't update coverage in the depth-only pixel shader 2019-01-06 20:13:23 +03:00
Triang3l
6c48f209a1 [D3D12] Fix 7e3 and 20e4 denormal conversion 2019-01-06 15:10:55 +03:00