Triang3l
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7a89ad16a6
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[D3D12] Update D3D12RenderTargetCache::Update write mask argument name
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2022-05-02 23:16:18 +03:00 |
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Triang3l
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0fd578cafd
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[GPU] Get unclipped draw height by running VS on the CPU
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2022-04-28 22:25:25 +03:00 |
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Triang3l
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5ec0c92601
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[GPU] Ignore z_enable for !z_write_enable && z_func == ALWAYS
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2022-04-27 21:46:29 +03:00 |
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Triang3l
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c4eae232f1
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[D3D12] Fixes/cleanup for render targets and barriers
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2022-04-02 22:44:10 +03:00 |
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Triang3l
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3a07559df9
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[GPU] XeSL host depth store and VS passthrough shaders
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2022-03-27 16:15:53 +03:00 |
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Triang3l
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32ab1a2df1
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[D3D12] Minor RT code style/comments cleanup
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2022-03-22 21:48:26 +03:00 |
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Triang3l
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38b4741c8f
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[GPU] Mostly generic, not square-only resolution scaling
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2021-12-11 21:55:33 +03:00 |
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Triang3l
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fdec0ab332
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[Code] Make union usage more consistent
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2021-11-03 20:45:09 +03:00 |
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Triang3l
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3a2c7894d2
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[D3D12] Remove unused D3D12RenderTargetCache ref from D3D12RenderTarget
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2021-06-19 14:06:37 +03:00 |
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Triang3l
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8e83042bdf
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[GPU] Fix host_depth_store_2xmsaa CS after 2x MSAA sample swap
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2021-06-14 19:12:12 +03:00 |
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Triang3l
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357aa1cdd3
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[GPU] Fix RT view and pipeline sRGB mismatch
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2021-06-14 17:30:56 +03:00 |
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Triang3l
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12a907bfa5
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[GPU] Shaders to common, xb buildshaders instead of buildhlsl
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2021-06-05 18:53:53 +03:00 |
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Triang3l
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538aa91015
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[GPU] Primitive processor with Vulkan 1.0 base cases, 24-bit indices and clamping
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2021-06-04 23:57:46 +03:00 |
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Triang3l
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51c2c9e5f2
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[D3D12] Fix render target reference leak
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2021-04-27 19:55:29 +03:00 |
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Triang3l
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913e1e949c
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[GPU] Ownership-transfer-based RT cache, 3x3 resolution scaling
The ROV path is also disabled by default because of lower performance
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2021-04-26 22:12:09 +03:00 |
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