Commit Graph

15 Commits

Author SHA1 Message Date
Triang3l
7a89ad16a6 [D3D12] Update D3D12RenderTargetCache::Update write mask argument name 2022-05-02 23:16:18 +03:00
Triang3l
0fd578cafd [GPU] Get unclipped draw height by running VS on the CPU 2022-04-28 22:25:25 +03:00
Triang3l
5ec0c92601 [GPU] Ignore z_enable for !z_write_enable && z_func == ALWAYS 2022-04-27 21:46:29 +03:00
Triang3l
c4eae232f1 [D3D12] Fixes/cleanup for render targets and barriers 2022-04-02 22:44:10 +03:00
Triang3l
3a07559df9 [GPU] XeSL host depth store and VS passthrough shaders 2022-03-27 16:15:53 +03:00
Triang3l
32ab1a2df1 [D3D12] Minor RT code style/comments cleanup 2022-03-22 21:48:26 +03:00
Triang3l
38b4741c8f [GPU] Mostly generic, not square-only resolution scaling 2021-12-11 21:55:33 +03:00
Triang3l
fdec0ab332 [Code] Make union usage more consistent 2021-11-03 20:45:09 +03:00
Triang3l
3a2c7894d2 [D3D12] Remove unused D3D12RenderTargetCache ref from D3D12RenderTarget 2021-06-19 14:06:37 +03:00
Triang3l
8e83042bdf [GPU] Fix host_depth_store_2xmsaa CS after 2x MSAA sample swap 2021-06-14 19:12:12 +03:00
Triang3l
357aa1cdd3 [GPU] Fix RT view and pipeline sRGB mismatch 2021-06-14 17:30:56 +03:00
Triang3l
12a907bfa5 [GPU] Shaders to common, xb buildshaders instead of buildhlsl 2021-06-05 18:53:53 +03:00
Triang3l
538aa91015 [GPU] Primitive processor with Vulkan 1.0 base cases, 24-bit indices and clamping 2021-06-04 23:57:46 +03:00
Triang3l
51c2c9e5f2 [D3D12] Fix render target reference leak 2021-04-27 19:55:29 +03:00
Triang3l
913e1e949c [GPU] Ownership-transfer-based RT cache, 3x3 resolution scaling
The ROV path is also disabled by default because of lower performance
2021-04-26 22:12:09 +03:00