Commit Graph

25 Commits

Author SHA1 Message Date
Herman S.
65d42843b6 Merge remote-tracking branch 'xenia-master/master' into canary_experimental 2026-03-06 23:05:24 +09:00
Triang3l
cec9ca0ef2 [GPU] 8-bit PWL gamma RT as linear 16-bit UNorm on the host
With render target HLE, directly store linear values as R16G16B16A16_UNORM
without gamma conversion, as this format provides more than enough bits
(need at least 11 per component due to the maximum scale being 2^3 in the
piecewise linear gamma curve) to represent linear values without precision
loss.

This makes blending work correctly in linear space, improving quality of
transparency, lighting passes, and fixing issues such as transparent parts
of impact and footstep decals in 4D5307E6 being bright instead.

The new behavior is enabled by default, as it hugely improves the accuracy
of emulation of this format, that is pretty commonplace in Xbox 360 games,
with likely just a small GPU memory and bandwidth usage increase, compared
to the alternatives that were previously available on the HLE RB path.

It's currently implemented only on Direct3D 12, as most of the current GPU
emulation code is planned to be phased out and redone, and no methods other
than 8-bit with pre-conversion were implemented on Vulkan previously.

To implement on Vulkan later, same conversion as in the Direct3D 12
implementation will need to be done in ownership transfer and resolve
shaders. Currently it's somewhat inconvenient to decouple the conversion
functions in `SpirvShaderTranslator` from an instance of the translator due
to vector constant usage. Later, simpler SPIR-V generation functions may be
added (`spv::Builder` usage in general is overly verbose).

The previously default method (8-bit storage with pre-conversion in shaders
and incorrect blending) can be re-enabled by setting the
"gamma_render_target_as_unorm16" configuration option to `false`. This may
be useful if the game, for instance, switches between 8_8_8_8_GAMMA and
8_8_8_8 formats for the same data frequently, as switching will result in
EDRAM range ownership transfer data copying now. Also, the old path is
preserved for Vulkan devices not supporting R16G16B16A16_UNORM with
blending.

The other workaround that was available previously, replacing the PWL
encoding with host hardware sRGB with linear-space blending in render
target management and in texture fetching, was also inherently inaccurate
in many ways (especially when games have their own PWL encoding math, like
4541080F that displayed incorrect colors on the loading screen), and
required tracking of the encoding needed for ranges in the memory.

The sRGB workaround therefore was deleted in this commit, greatly
simplifying the code in the parts of render target, texture and memory
management and shader generation that were involved in it.
2026-01-18 16:22:22 +03:00
Gliniak
b9061e6292 [LINT] Linted files + Added lint job to CI 2024-03-12 19:19:30 +01:00
chss95cs@gmail.com
c1d922eebf Minor decoder optimizations, kernel fixes, cpu backend fixes 2022-11-05 10:50:33 -07:00
Triang3l
45050b2380 [GPU] Vulkan fragment shader interlock RB and related fixes/cleanup
Also fixes addressing of MSAA samples 2 and 3 for 64bpp color render targets in the ROV RB implementation on Direct3D 12.
Additionally, with FSI/ROV, alpha test and alpha to coverage are done only if the render target 0 was dynamically written to (according to the Direct3D 9 rules for writing to color render targets, though not sure if they actually apply to the alpha tests on Direct3D 9, but for safety).
There is also some code cleanup for things spotted during the development of the feature.
2022-10-09 22:06:41 +03:00
Triang3l
3c12814276 [GPU] EDRAM looped addressing (resolves #2031) 2022-07-22 23:51:50 +03:00
Triang3l
14fdf4b270 [GPU] Up to 7x7 resolution scaling 2022-07-17 20:41:50 +03:00
Triang3l
feaad639fb [Vulkan] Destroy all RTs before VulkanRenderTargetCache is destroyed 2022-07-04 11:27:51 +03:00
Triang3l
7869b080d3 [D3D12] Truncate depth to float24 in EDRAM range ownership transfers and resolves by default
Doesn't ruin the "greater or equal" depth test in subsequent rendering passes if precision is lost, unlike rounding to the nearest
2022-06-22 12:53:09 +03:00
Triang3l
d280b3953d [GPU] Texture object/binding management to common superclass 2022-05-14 16:18:10 +03:00
Triang3l
0fd578cafd [GPU] Get unclipped draw height by running VS on the CPU 2022-04-28 22:25:25 +03:00
Triang3l
5ec0c92601 [GPU] Ignore z_enable for !z_write_enable && z_func == ALWAYS 2022-04-27 21:46:29 +03:00
Triang3l
c4eae232f1 [D3D12] Fixes/cleanup for render targets and barriers 2022-04-02 22:44:10 +03:00
Triang3l
3a07559df9 [GPU] XeSL host depth store and VS passthrough shaders 2022-03-27 16:15:53 +03:00
Triang3l
8d07c79897 [GPU] Cleanup RB_COLOR_MASK and RB_DEPTHCONTROL normalization 2022-02-13 20:50:31 +03:00
Triang3l
793cebd6a7 [GPU] Explain 1.5x scaling issues in a comment 2021-12-12 14:31:05 +03:00
Triang3l
38b4741c8f [GPU] Mostly generic, not square-only resolution scaling 2021-12-11 21:55:33 +03:00
Triang3l
fdec0ab332 [Code] Make union usage more consistent 2021-11-03 20:45:09 +03:00
Joel Linn
cfd18b89f8 [GPU] GCC build fix for render target cache 2021-09-27 13:43:57 +03:00
Triang3l
e720e0a540 [Code] Remove game names from code comments (most of at least) 2021-09-05 21:27:40 +03:00
Triang3l
4a95f72fba [GPU] RT size function adjustments for Vulkan convenience 2021-06-19 13:57:14 +03:00
Triang3l
357aa1cdd3 [GPU] Fix RT view and pipeline sRGB mismatch 2021-06-14 17:30:56 +03:00
Triang3l
538aa91015 [GPU] Primitive processor with Vulkan 1.0 base cases, 24-bit indices and clamping 2021-06-04 23:57:46 +03:00
Joel Linn
6dfa36d1b8 [GPU] Misc GCC build fixes 2021-06-02 22:28:43 -05:00
Triang3l
913e1e949c [GPU] Ownership-transfer-based RT cache, 3x3 resolution scaling
The ROV path is also disabled by default because of lower performance
2021-04-26 22:12:09 +03:00