Commit Graph

45 Commits

Author SHA1 Message Date
chss95cs@gmail.com
b26c6ee1b8 Fix some more constant folding
fabsx does NOT set fpscr
turns out that our vector unsigned compare instructions are a bit wierd?
2022-08-21 10:27:54 -07:00
chss95cs@gmail.com
457296850e Add OPCODE_NEGATED_MUL_ADD/OPCODE_NEGATED_MUL_SUB
Proper handling of nans for VMX max/min on x64 (minps/maxps has special behavior depending on the operand order that vmx does not have for vminfp/vmaxfp)
Add extremely unintrusive guest code profiler utilizing KUSER_SHARED systemtime. This profiler is disabled on platforms other than windows, and on windows is disabled by default by a cvar
Repurpose GUEST_SCRATCH64 stack offset to instead be for storing guest function profile times, define GUEST_SCRATCH as 0 instead, since thats already meant to be a scratch area
Fix xenia silently closing on config errors/other fatal errors by setting has_console_attached_'s default to false
Add alternative code path for guest clock that uses kusershared systemtime instead of QueryPerformanceCounter. This is way faster and I have tested it and found it to be working, but i have disabled it because i do not know how well it works on wine or on processors other than mine
Significantly reduce log spam by setting XELOGAPU and XELOGGPU to be LogLevel::Debug
Changed some LOGI to LOGD in places to reduce log spam
Mark VdSwap as kHighFrequency, it was spamming up logs
Make logging calls less intrusive for the caller by forcing the test of log level inline and moving the format/AppendLogLine stuff to an outlined cold function
Add swcache namespace for software cache operations like prefetches, streaming stores and streaming loads.
Add XE_MSVC_REORDER_BARRIER for preventing msvc from propagating a value too close to its store or from its load
Add xe_unlikely_mutex for locks we know have very little contention
add XE_HOST_CACHE_LINE_SIZE and XE_RESTRICT to platform.h
Microoptimization: Changed most uses of size_t to ring_size_t in RingBuffer, this reduces the size of the inlined ringbuffer operations slightly by eliminating rex prefixes, depending on register allocation
Add BeginPrefetchedRead to ringbuffer, which prefetches the second range if there is one according to the provided PrefetchTag
added inline_loadclock cvar, which will directly use the value of the guest clock from clock.cc in jitted guest code. off by default
change uses of GUEST_SCRATCH64 to GUEST_SCRATCH
Add fast vectorized xenos_half_to_float/xenos_float_to_half (currently resides in x64_seq_vector, move to gpu code maybe at some point)
Add fast x64 codegen for PackFloat16_4/UnpackFloat16_4. Same code can be used for Float16_2 in future commit. This should speed up some games that use these functions heavily
Remove cvar for toggling old float16 behavior
Add VRSAVE register, support mfspr/mtspr vrsave
Add cvar for toggling off codegen for trap instructions and set it to true by default.
Add specialized methods to CommandProcessor: WriteRegistersFromMem, WriteRegisterRangeFromRing, and WriteOneRegisterFromRing. These reduce the overall cost of WriteRegister
Use a fixed size vmem vector for upload ranges, realloc/memsetting on resize  in the inner loop of requestranges was showing up on the profiler (the search in requestranges itself needs work)
Rename fixed_vmem_vector to better fit xenia's naming convention
Only log unknown register writes in WriteRegister if DEBUG :/. We're stuck on MSVC with c++17 so we have no way of influencing the branch ordering for that function without profile guided optimization
Remove binding stride assert in shader_translator.cc, triangle told me its leftover ogl stuff
Mark xe::FatalError as noreturn
If a controller is not connected, delay by 1.1 seconds before checking if it has been reconnected. Asking Xinput about a controller slot that is unused is extremely slow, and XinputGetState/SetState were taking up
an enormous amount of time in profiles. this may have caused a bit of input lag
Protect accesses to input_system with a lock
Add proper handling for user_index>= 4 in XamInputGetState/SetState, properly return zeroed state in GetState
Add missing argument to NtQueryVirtualMemory_entry
Fixed RtlCompareMemoryUlong_entry, it actually does not care if the source is misaligned, and for length it aligns down
Fixed RtlUpperChar and RtlLowerChar, added a table that has their correct return values precomputed
2022-08-20 11:40:19 -07:00
chss95cs@gmail.com
968f656d96 Add separate VMX/fpu mxcsr
Add support for constant operands for most fpu instructions
Remove constant folding for most fpu cpde
half float
2022-07-31 08:56:36 -07:00
chss95cs@gmail.com
33a6cfc0a7 Add special cases to DOT_PRODUCT_3/4 that detect whether they're calculating lengthsquared
Add alternate path to DOT_PRODUCT_3/4 for use_fast_dot_product that skips all the status register stuff and just remaps inf to qnan
Add OPCODE_TO_SINGLE to replace the CONVERT_F32_F64 - CONVERT_F64_F32 sequence we used to emit with the idea that a backend could implement a more correct rounding behavior if possible on its arch
Remove some impossible sequences like MUL_HI_I8/I16, MUL_ADD_F32, DIV_V128. These instructions have no equivalent in PPC. Many other instructions are unused/dead code and should be removed to make the x64 backend a better reference for future ones
Add backend_flags to Instr. Basically, flags field that a backend can use for whatever it wants when generating code.
Add backend instr flag to x64 that tells it to not generate code for an instruction. this allows sequences to consume subsequent instructions
Generate actual x64 code for VSL instruction instead of using callnativesafe
Detect repeated COMPARE instructions w/ identical operands and reuse the results in FLAGS if so. this eliminates a ton of garbage compare/set instructions.
If a COMPARE instructions destination is stored to context with no intervening instruction and no additional uses besides the store, do setx [ctx address]
Detect prefetchw and use it in CACHE_CONTROL if prefetch for write is requested instead of doing prefetch to all cache levels
Fixed an accident in an earlier commit by me, VECTOR_DENORMFLUSH was not being emitted at all, so denormal inputs to MUL_ADD_V128 were not becoming zero and outputs from DOT_PRODUCT_X were not either. I believe this introduced a bug into RDR where a wagon wouldnt spawn? (https://discord.com/channels/308194948048486401/308207592482668545/1000443975817252874)
Compute fresx in double precision using RECIP_F64 and then round to single instead of doing (double)(1.0f / (float)value), matching original behavior better
Refactor some of ppc_emit_fpu, much of the InstrEmit function are identical except for whether they round to single or not
Added "tail emitters" to X64Emitter. These are callbacks that get invoked with their label and the X64Emitter after the epilog code. This allows us to move cold code out of the critical path and in the future place constant pools near functions
guest_to_host_thunk/host_to_guest_thunk now gets directly rel32 called, instead of doing a mov
Add X64BackendContext structure, represents data before the start of the PPCContext
Instead of doing branchless sequence, do a compare and jump to tail emitted code for address translation. This makes converting addresses a 3 uop affair in most cases.
Do qnan move for dot product in a tail emitter
Detect whether EFLAGS bits are independent variables for the current cpu (not really detecting it ehe, just checking if zen) and if so generate inc/dec for add/sub 1
Detect whether low 32 bits of membase are 0. If they are then we can use membasereg.cvt32() in place of immediate 0 in many places, particularly in stores
Detect LOAD MODIFY STORE pattern for context variables (currently only done for 64 bit ones) and turn them into modify [context ptr]. This is done for add, sub, and, or, xor, not, neg
Tail emit error handling for TRAP opcodes
Stub out unused trap opcodes like TRAP_TRUE_I32, TRAP_TRUE_I64, TRAP_TRUE_I16 (the call_true/return_true opcodes for these types are also probably unused)
Remove BackpropTruncations. It was poorly written and causes crashes on the game Viva pinata (https://discord.com/channels/308194948048486401/701111856600711208/1000249460451983420)
2022-07-23 12:10:07 -07:00
chss95cs@gmail.com
6a612b4d34 remove useless tag field from hir::Value
pack local_slot and constant in hir::Value
Instead of loading membase at the start of every function, just load it in HostToGuestThunk
vzeroupper in GuestToHostThunk before calling host function, and in HostToGuestThunk after calling function to prevent AVX dirty state slowdowns. In the future, check if CPU implements AVX as 128x2 and skip if so (https://john-h-k.github.io/VexTransitionPenalties.html)
Remove useless save/restore of ctx pointer, nothing modifies it and it prevents cpus from doing cross-function memory renaming (https://www.agner.org/forum/viewtopic.php?t=41). Could not remove the space on stack because of alignment issues, instead turned it into GUEST_SCRATCH64 which is a temporary that sequences may use
Reorder OpcodeInfo so that name is at offset 0, remove name and add GetOpcodeName function (name is only used for debug code, we are seperating frequently accessed data and rarely accessed data)
Add VECTOR_DENORMFLUSH opcode for handling output to DOT_PRODUCT and other opcodes that implicitly force denormal inputs/outputs to zero, will eventually use for implementing NJM
Rewrite sequences for LOAD_VECTOR_SHL/SHR. The mask with 0xf in it was pointless as all InstrEmit_ functions that create the load shift instructions do that in HIR. The tables are only used for nonzero constant inputs now, which are probably pretty rare. Instead of doing a shift and lookup, a base value is used for both in the constant table and adding/subtracting of the input is done
Reuse result of LoadVectorShl/Shr in InstrEmit_stvlx_, InstrEmit_stvrx_. We were previously calculating it twice which was contributing to the final sequences' fatness. Use OPCODE_SELECT instead of the sequence of or, andnot, and that it was using for merging
Add the proper unconditional denormal input flushing behavior to vfmadd, add it also to vfmsub (making the assumption it has the same behavior)
Remove constant propagation for DOT_PRODUCT_3/4
DOT_PRODUCT_3/4 now returns a vector with all four elements set to the result. (what we were doing before, truncating to float32 and then splatting didnt make any sense)
Add much more correct versions of DOT_PRODUCT_3/4, matching the Xb360's  to 1 bit. Still needs work to be a perfect emulation.
Add constant folding for OPCODE_SELECT, OPCODE_INSERT, OPCODE_PERMUTE, OPCODE_SWIZZLE
Remove constant folding for DOT_PRODUCT
Removed the multibyte nop code I committed earlier, it doesnt help us much because nops are only used for debug stuff and its ugly and wouldnt survive in a pr to main
Check for AVX512BMI, use vpermb to shuffle if supported
2022-07-16 10:25:04 -07:00
Wunkolo
0fdb855a11 [JIT, x64] Add and implement OPCODE_AND_NOT
Verified the x64 implementation using `xenia-cpu-ppc-tests`.
2022-01-04 16:16:49 -06:00
Joel Linn
86722be9ca [Base] Make Arena alignment aware
- Add align parameter
- Templated Alloc() implicitly aligns type correctly
- Rewind may leak padding that was added due to alignment
2021-06-02 22:28:43 -05:00
gibbed
5bf0b34445 C++17ification.
C++17ification!

- Filesystem interaction now uses std::filesystem::path.
- Usage of const char*, std::string have been changed to
  std::string_view where appropriate.
- Usage of printf-style functions changed to use fmt.
2020-04-07 16:09:41 -05:00
Triang3l
bc4b68db45 [CPU] Data cache control instructions 2019-08-18 16:22:32 +03:00
gibbed
94284ea9aa [CPU] Fix null termination in HIRBuilder::CommentFormat. 2018-11-23 07:50:42 -06:00
DrChat
e54c24e150 [JIT] New opcodes: OPCODE_LOAD_OFFSET and OPCODE_STORE_OFFSET
These take full advantage of x86 addressing, and eliminate extra add operations.
2018-02-14 16:26:49 -06:00
DrChat
aaf281351d Format all code with new clang-format 2017-12-14 20:44:43 -06:00
Dr. Chat
82efbd7bc5 HIR: Add opcode SET_ROUNDING_MODE (taking FPSCR as an argument) 2017-05-12 14:05:27 -05:00
Dr. Chat
18ff97e6b6 OPCODE_IS_NAN 2016-07-11 20:44:12 -05:00
Dr. Chat
f2ad6b8cb8 OPCODE_RECIP 2016-06-26 13:03:42 -05:00
Dr. Chat
7b6f1388d6 OPCODE_ATOMIC_COMPARE_EXCHANGE 2016-01-13 01:41:58 -06:00
Ben Vanik
dfd92757a9 Adding CONTEXT_BARRIER to force the PPC context to synchronize.
This is just an annotation right now, as it's not actually needed.
2015-11-25 14:48:36 -08:00
Ben Vanik
4af6c41740 Moving profiling.h to base - UI could be separated for cleanliness. 2015-11-07 12:31:07 -08:00
Ben Vanik
82a72e1974 Adding MemoryBarrier opcode. 2015-08-30 17:25:02 -07:00
Ben Vanik
8b0d4fb51c Linux tweaks. 2015-08-18 14:18:00 -07:00
Ben Vanik
a92566dfc5 More style. 2015-08-07 21:29:03 -07:00
Ben Vanik
5e08889d93 More style cleanup. 2015-08-06 20:17:01 -07:00
Ben Vanik
eaa1a8ee3a Refactoring SymbolInfo/FunctionInfo/Function into Symbol/Function. 2015-08-05 21:50:02 -07:00
Ben Vanik
cb701fcb7c Latest linter. 2015-08-01 04:08:59 -07:00
Ben Vanik
91d7acf59e Fixing some particularly bad /W4. 2015-07-18 23:04:21 -07:00
Ben Vanik
40621a90bd Switching to standard mutex for now (but keeping xe::mutex). 2015-07-13 21:49:32 -07:00
Ben Vanik
0630b524fa Removing unused HIR opcodes.
Progress on #291.
2015-06-28 12:01:46 -07:00
Drew DeVault
a064ba053e Add missing includes for cstring 2015-06-16 23:16:18 -06:00
Ben Vanik
edaebbf00f Adding call address assert. 2015-06-14 00:09:58 -07:00
Ben Vanik
3870dabcee Replacing LoadZero and LoadConstant with explicit types. 2015-06-13 23:42:38 -07:00
Ben Vanik
14e1438ec0 Dramatically speeding up HIR comments. 2015-06-10 00:28:02 -07:00
Ben Vanik
889f29c18a Fixing CFG to remove unreachable blocks and properly maintain dominators. 2015-06-07 15:14:14 -07:00
Ben Vanik
429698c2ec Replacing DidCarry with manual calculation and fixing compares. 2015-06-06 15:24:46 -07:00
Ben Vanik
40a6a12800 Attempting to inline a lot of MMIO operations. Works for GPU stuff mainly. 2015-06-02 20:15:43 -07:00
Ben Vanik
d816d80190 StringBuffer cleanup. 2015-05-31 14:35:30 -07:00
Ben Vanik
c97b462d8d Fix assert. 2015-05-30 18:04:31 -07:00
Ben Vanik
c1a0f46ea8 Implementing dcbz. 2015-05-17 16:40:38 -07:00
Ben Vanik
df600a105a Fixing constant compare. 2015-05-14 14:42:54 -07:00
gibbed
ff2c00e220 Just in case. 2015-05-12 06:51:31 -05:00
Ben Vanik
ade5388728 bool-ifying xe::cpu 2015-05-05 18:52:54 -07:00
Ben Vanik
4c8f3501ad Removing xdb and old tracing code before rewrite. 2015-05-03 22:01:31 -07:00
Ben Vanik
e3220f7ae6 Code cleanup: moving poly/ into xenia/base/ 2015-05-02 03:42:51 -07:00
Ben Vanik
99816056be Code cleanup: removing poly.h 2015-05-02 02:29:26 -07:00
Ben Vanik
9281d62106 Moving cpu/runtime/ to cpu/. 2015-03-24 08:25:58 -07:00
Ben Vanik
29912f44c0 Moving alloy/ into xenia/cpu/ to start simplifying things. 2015-03-24 07:46:18 -07:00