Commit Graph

82 Commits

Author SHA1 Message Date
Triang3l
0e81293b02 [GPU] Remove a dangerous comment about break after exece [ci skip]
There can be jumps across an exece, so the code beyond it may still be
executed.
2023-05-05 21:32:02 +03:00
Triang3l
53f98d1fe6 [GPU/D3D12] Memexport from anywhere in control flow + 8/16bpp memexport
There's no limit on the number of memory exports in a shader on the real
Xenos, and exports can be done anywhere, including in loops. Now, instead
of deferring the exports to the end of the shader, and assuming that export
allocs are executed only once, Xenia flushes exports when it reaches an
alloc (allocs terminate memory exports on Xenos, as well as individual ALU
instructions with `serialize`, but not handling this case for simplicity,
it's only truly mandatory to flush memory exports before starting a new
one), the end of the shader, or a pixel with outstanding exports is killed.

To know which eM# registers need to be flushed to the memory, traversing
the successors of each exec potentially writing any eM#, and specifying
that certain eM# registers might have potentially been written before each
reached control flow instruction, until a flush point or the end of the
shader is reached.

Also, some games export to sub-32bpp formats. These are now supported via
atomic AND clearing the bits of the dword to replace followed by an atomic
OR inserting the new byte/short.
2023-05-05 21:32:02 +03:00
Triang3l
1a95bef8b3 [GPU] Eliminate unused shader I/O, UCP culling, centroid on Vulkan
For more optimal usage of exports and the parameter cache on the host regardless of how effective the optimizations in the host GPU driver are. Also reserve space for Vulkan/Metal/D3D11-specific HostVertexShaderTypes to use one more bit for the host vertex shader type in the shader modification bits, so that won't have to be done in the future as that would require invalidating shader storages (which are invalidated by this commit) again.
2022-07-21 12:32:28 +03:00
Triang3l
0fd578cafd [GPU] Get unclipped draw height by running VS on the CPU 2022-04-28 22:25:25 +03:00
Triang3l
5519dbb39f [GPU] Shader control flow documentation improvements 2022-04-27 21:34:08 +03:00
Triang3l
b42680abf7 [GPU] Shader ALU refactoring + documentation
Mainly move instruction info from the ShaderTranslator to xe::gpu::ucode for future use in the CPU shader interpreter
2022-04-27 20:52:20 +03:00
Triang3l
fea430f1f9 [GPU] Fix scalar c[#+aL], shader docs/refactoring 2022-04-13 23:08:19 +03:00
Triang3l
14b69fdb00 [GPU] vfetch_full fetching nothing still must calculate the address 2022-01-09 16:26:05 +03:00
Triang3l
d6188c5d7e [GPU] Reuse base+index*stride in vfetch_mini instead of reloading the index GPR
The wheel shader in 4D530910 does vfetch_full to r0 with the index from r0.x, and then vfetch_mini.
Thanks @Gliniak for the finding :3
Also small formatting cleanup in commented-out code.
2022-01-09 14:58:38 +03:00
Triang3l
e720e0a540 [Code] Remove game names from code comments (most of at least) 2021-09-05 21:27:40 +03:00
Triang3l
9009cba90a [GPU] Refactor shader dumps - bin and txt files for both ucode and host 2020-12-25 21:46:07 +03:00
Triang3l
733efa5ff8 [GPU] Add a missing default label to GatherAluResultInformation 2020-12-22 22:29:00 +03:00
Triang3l
e6fa0ad139 [GPU] Dynamic r# count via shader modifications + refactoring 2020-12-19 16:14:54 +03:00
Triang3l
9a4643d0f2 [GPU] Non-ROV f24 trunc/round, host shader modifications, cache dir 2020-12-07 22:31:46 +03:00
Triang3l
fd18a97f3a [GPU] Shaders: Make label_addresses accessible to translators 2020-10-14 21:19:33 +03:00
Triang3l
79413345af [C++17] static constexpr variables are implicitly inline now 2020-07-11 16:44:57 +03:00
Triang3l
4bb0ca0e09 [GPU] Move all xenos.h to gpu::xenos, disambiguate Dimension/TextureDimension 2020-07-11 15:54:22 +03:00
Triang3l
8a64861ec0 [DXBC] New tfetch: pre-swizzle signs, additive LOD + refactoring 2020-06-06 19:12:34 +03:00
Triang3l
aa73d652ba [DXBC] OpenGL snorm vfetch because why not 2020-05-24 19:25:35 +03:00
Triang3l
3879ff29b3 [DXBC/GPU] vfetch to new codegen, signed vfetch offset, fix AND with system flags 2020-05-23 17:15:11 +03:00
Triang3l
b256005b7a [GPU] Fix GatherInstructionInformation enum values not handled warning 2020-05-11 00:28:26 +03:00
Triang3l
3aa0ce3096 [GPU] Shader translator refactoring (mostly ALU), fixes for disassembly round trip and write masks 2020-05-08 23:57:51 +03:00
gibbed
a48bb71c2f Overhaul logging. 2020-04-07 16:09:41 -05:00
gibbed
5bf0b34445 C++17ification.
C++17ification!

- Filesystem interaction now uses std::filesystem::path.
- Usage of const char*, std::string have been changed to
  std::string_view where appropriate.
- Usage of printf-style functions changed to use fmt.
2020-04-07 16:09:41 -05:00
Triang3l
4b9f63cdf1 [GPU] Shader::HostVertexShaderType enum for domain shader types 2020-04-06 00:03:23 +03:00
Triang3l
1336316139 [D3D12] Vertex kill and multipass vertex exports 2020-02-20 08:56:16 +03:00
Triang3l
4061445087 [GPU] Remove unused kConstantInt/Bool shader operands 2020-02-02 21:05:00 +03:00
Triang3l
a9ed73bdd1 [GPU] Remove most hardcoded register/instruction layouts from common and D3D12 code 2019-10-20 19:40:37 +03:00
Triang3l
f83269cf8c [GPU] Refactor: Register structs in D3D12CommandProcessor and some other places 2019-10-19 23:32:38 +03:00
Triang3l
84a8dc91e4 [D3D12] Filtering between array texture layers 2019-09-03 10:14:25 +03:00
Triang3l
4825e69fda [D3D12] Cleanup primitive types and front/back facing 2019-07-13 22:25:03 +03:00
Triang3l
6672997108 [D3D12] ROV early Z and full rewrite, shader scalar optimizations 2019-07-11 09:31:58 +03:00
Triang3l
66a9c9d812 [GPU] Store ALU result after both vector and scalar instructions 2019-04-20 20:30:01 +03:00
Triang3l
80e5c56340 Merge branch 'master' into d3d12 2019-01-25 20:44:51 +03:00
Triang3l
e706cf0d54 [GPU] Fix addsc/mulsc/subsc r# addressing mode not initialized 2019-01-25 20:43:53 +03:00
Triang3l
ef523823d5 [D3D12] Force early Z with DSV, fix blend disabled flag in rb_colorcontrol ignored 2019-01-11 17:07:33 +03:00
Triang3l
72e9ac5c28 [GPU] Shader translator: More memexport validation 2018-12-21 22:24:09 +03:00
Triang3l
73baaa8e89 [GPU] Gather eA/eM# writes in shader translator 2018-12-21 10:06:41 +03:00
Triang3l
adc0eb87f6 [GPU] Gather used memexport constants in shader translator 2018-12-20 10:14:18 +03:00
Triang3l
9a58841219 [D3D12] ROV: Use MSAA instead of SSAA 2018-11-25 16:37:38 +03:00
Triang3l
da280347c4 Merge branch 'master' into d3d12 2018-11-22 21:01:05 +03:00
Margen67
896ac4a682 Update documentation.
- Convert http to https, provide archive link when possible.
- Made CPU-JIT.png more readable on dark themes;
Added a white background so there isn't black text on a black
background.
2018-11-22 09:20:09 -06:00
Triang3l
d35be635d6 Merge branch 'master' of github.com:xenia-project/xenia into d3d12 2018-11-18 22:21:32 +03:00
Triang3l
7fa453c813 [GPU] Fix 1-component ALU instruction swizzle (hopefully) 2018-11-18 22:20:43 +03:00
Triang3l
2b03a9e095 [GPU] Synchronize GPU frontend with the D3D12 branch 2018-10-22 23:28:52 +03:00
Triang3l
2588aab89d [GPU/D3D12] Float constant remapping fixes 2018-10-01 20:15:00 +03:00
Triang3l
c4599ff211 [D3D12] Compact float constants and don't split them into pages 2018-09-30 20:17:26 +03:00
Triang3l
34fef0911c [GPU] Fix dynamic GPR addressing check 2018-09-17 07:35:56 +03:00
Triang3l
2a98d29eda [D3D12] DXBC: Most of tfetch 2018-09-11 22:57:08 +03:00
Triang3l
1413a7d206 [GPU] Rename uses_register_relative_addressing to uses_register_dynamic_addressing 2018-09-02 16:31:21 +03:00