Commit Graph

26 Commits

Author SHA1 Message Date
Ylederman153
02c6bc6e61 [D3D12] Implement extended range for f32 to f16 conversion in memexport (#899)
Resolves TODO(Triang3l) by implementing a mathematical workaround to allow exponent 31 for extended float16 range up to +/-131008.0f as expected by the native Xbox 360 hardware, bypassing standard D3D12 f32tof16 boundaries which incorrectly clamp/inf values.
2026-03-03 17:16:05 +09:00
Margen67
4cb783bf22 Header cleanup 2025-07-19 14:42:21 -07:00
Triang3l
53f98d1fe6 [GPU/D3D12] Memexport from anywhere in control flow + 8/16bpp memexport
There's no limit on the number of memory exports in a shader on the real
Xenos, and exports can be done anywhere, including in loops. Now, instead
of deferring the exports to the end of the shader, and assuming that export
allocs are executed only once, Xenia flushes exports when it reaches an
alloc (allocs terminate memory exports on Xenos, as well as individual ALU
instructions with `serialize`, but not handling this case for simplicity,
it's only truly mandatory to flush memory exports before starting a new
one), the end of the shader, or a pixel with outstanding exports is killed.

To know which eM# registers need to be flushed to the memory, traversing
the successors of each exec potentially writing any eM#, and specifying
that certain eM# registers might have potentially been written before each
reached control flow instruction, until a flush point or the end of the
shader is reached.

Also, some games export to sub-32bpp formats. These are now supported via
atomic AND clearing the bits of the dword to replace followed by an atomic
OR inserting the new byte/short.
2023-05-05 21:32:02 +03:00
Triang3l
1a95bef8b3 [GPU] Eliminate unused shader I/O, UCP culling, centroid on Vulkan
For more optimal usage of exports and the parameter cache on the host regardless of how effective the optimizations in the host GPU driver are. Also reserve space for Vulkan/Metal/D3D11-specific HostVertexShaderTypes to use one more bit for the host vertex shader type in the shader modification bits, so that won't have to be done in the future as that would require invalidating shader storages (which are invalidated by this commit) again.
2022-07-21 12:32:28 +03:00
Triang3l
e2f632f8fa [D3D12] Use udiv by constant tile size + minor transfer cleanup
Drivers compile that to a multiplication and a shift anyway.
2022-06-20 22:39:30 +03:00
Triang3l
efd7ef212a [D3D12] 128 megatexel limit explanation based on the spec [ci skip] 2022-05-31 23:23:10 +03:00
Triang3l
d280b3953d [GPU] Texture object/binding management to common superclass 2022-05-14 16:18:10 +03:00
Triang3l
e3425b242e [DXBC] Both v[#] and v[#][#] operands for HS and GS 2022-05-07 16:17:17 +03:00
Triang3l
38b4741c8f [GPU] Mostly generic, not square-only resolution scaling 2021-12-11 21:55:33 +03:00
Triang3l
28fec845d5 [GPU] Document memexport/resolve formats with more details 2021-10-22 20:00:41 +03:00
Triang3l
9f8a432479 [DXBC] Cleanup: kSysConst_*_Vec/Comp > LoadSystemConstant 2021-05-16 17:43:18 +03:00
Triang3l
913e1e949c [GPU] Ownership-transfer-based RT cache, 3x3 resolution scaling
The ROV path is also disabled by default because of lower performance
2021-04-26 22:12:09 +03:00
Triang3l
9a74df491f [DXBC] dxbc.h with non-translator-specific parts 2021-01-04 16:15:50 +03:00
Triang3l
e6fa0ad139 [GPU] Dynamic r# count via shader modifications + refactoring 2020-12-19 16:14:54 +03:00
Triang3l
9a4643d0f2 [GPU] Non-ROV f24 trunc/round, host shader modifications, cache dir 2020-12-07 22:31:46 +03:00
Triang3l
bd5f77bc3b [GPU] Common resolve code based on compute shaders, swap MSAA samples 1 and 2, change ROV write rounding, random refactoring 2020-08-09 21:33:10 +03:00
Triang3l
4bb0ca0e09 [GPU] Move all xenos.h to gpu::xenos, disambiguate Dimension/TextureDimension 2020-07-11 15:54:22 +03:00
Triang3l
40e335e2a9 [D3D12] Bindless textures/samplers 2020-06-19 23:52:33 +03:00
Triang3l
5f5e281e8c [DXBC] Rewrite a comment in memexport that may be outdated 2020-03-29 19:14:25 +03:00
Triang3l
05f6b444a0 [DXBC] Move memexport to the new DXBC code and make it more straightforward 2020-03-29 19:09:58 +03:00
Triang3l
7bdf59a8c7 [DXBC] Fix totally broken instruction when memexport is used in PS 2020-03-28 00:23:02 +03:00
Triang3l
6672997108 [D3D12] ROV early Z and full rewrite, shader scalar optimizations 2019-07-11 09:31:58 +03:00
Triang3l
bc89a5822b [D3D12] Memexport: Fix red/blue swap not being in the write mask 2019-01-05 21:14:06 +03:00
Triang3l
43866092a5 [D3D12] Update some comments about numeric formats 2018-12-28 14:12:09 +03:00
Triang3l
5860a8fdc6 [D3D12] DXBC: Add a missing STAT increment to memexport 2018-12-28 08:13:35 +03:00
Triang3l
ec7667ce1b [D3D12] Broken memexport shader code 2018-12-27 20:43:17 +03:00