Commit Graph

2433 Commits

Author SHA1 Message Date
Triang3l
9ebe25fd77 [GPU] Declare unused register fields explicitly 2024-05-02 23:31:13 +03:00
Gliniak
a966143823 [Emulator] use filesystem::file_size instead of ftell where possible 2024-03-22 11:03:34 +01:00
Gliniak
8c44649f01 [GPU] Another attempt to fix memleaks caused by depth_bias_slope_scaled 2024-03-16 19:31:00 +01:00
Gliniak
3d4bdc9023 Revert "[GPU] Resolved memory leak in RTV in pipeline creation"
This reverts commit e8dbb65fc1.
2024-03-16 11:07:45 +01:00
Gliniak
e8dbb65fc1 [GPU] Resolved memory leak in RTV in pipeline creation 2024-03-15 17:38:30 +01:00
Mateusz Dukat
34ed823bfc [GPU] Change FPS limit strategy 2024-03-14 20:58:40 +01:00
Gliniak
b9061e6292 [LINT] Linted files + Added lint job to CI 2024-03-12 19:19:30 +01:00
Maks
1a4746f261 [GPU] Reduced fuzzy alpha epsilon 2024-03-02 13:08:42 +01:00
maksloboda
9e86750bae [GPU] Add aproximate alpha test 2024-02-18 22:31:10 +01:00
yeah-its-gloria
57a23cf192 Fix typing for output stencil ref 2023-12-05 09:37:57 +01:00
Gliniak
a34944e4d2 [GPU] Added hack for AC6 floor/ground. Thanks Blackbird88 & TTFH3500
Added to prevent further builds fragmentation.
This will stay until accurate RCP will be implemented.
2023-10-28 10:28:25 +02:00
disjtqz
d36b1b3830 [GPU] gpu_allow_invalid_fetch_constants true by default 2023-10-12 23:03:14 +02:00
disjtqz
a7b047b2a2 Implement kernel processes 2023-10-12 22:13:40 +02:00
disjtqz
ba7397952d implement missing packet_disassembler code 2023-10-11 19:26:42 +02:00
disjtqz
cfecdcbeab [GPU] Vsync timing requires far less cpu now to be accurate 2023-09-29 20:17:11 +02:00
disjtqz
294b968fdf remove vsync_interval; replace with vsync_fps. 2023-09-29 20:17:11 +02:00
disjtqz
911055c44f add writeback base/size and xps base/size registers, EVENT_WRITE_SHD check 2023-09-21 21:44:23 +02:00
disjtqz
3876a1632a fix matchvalueandref freeze 2023-09-19 17:30:57 +02:00
Gliniak
ce9a82ccf8 Merge branch 'master' of https://github.com/xenia-project/xenia into canary_experimental 2023-09-01 18:20:29 +02:00
Gliniak
2a4d7feaae [GPU] Unified clear_memory_page_state to be used in D3D12 & Vulkan 2023-08-06 21:56:35 +02:00
Triang3l
ed64e3072b [GPU] Remove implicit bool cast in memexport checks 2023-05-05 21:38:45 +03:00
Triang3l
0e81293b02 [GPU] Remove a dangerous comment about break after exece [ci skip]
There can be jumps across an exece, so the code beyond it may still be
executed.
2023-05-05 21:32:02 +03:00
Triang3l
53f98d1fe6 [GPU/D3D12] Memexport from anywhere in control flow + 8/16bpp memexport
There's no limit on the number of memory exports in a shader on the real
Xenos, and exports can be done anywhere, including in loops. Now, instead
of deferring the exports to the end of the shader, and assuming that export
allocs are executed only once, Xenia flushes exports when it reaches an
alloc (allocs terminate memory exports on Xenos, as well as individual ALU
instructions with `serialize`, but not handling this case for simplicity,
it's only truly mandatory to flush memory exports before starting a new
one), the end of the shader, or a pixel with outstanding exports is killed.

To know which eM# registers need to be flushed to the memory, traversing
the successors of each exec potentially writing any eM#, and specifying
that certain eM# registers might have potentially been written before each
reached control flow instruction, until a flush point or the end of the
shader is reached.

Also, some games export to sub-32bpp formats. These are now supported via
atomic AND clearing the bits of the dword to replace followed by an atomic
OR inserting the new byte/short.
2023-05-05 21:32:02 +03:00
Radosław Gliński
37051afcaf Merge branch 'xenia-project:master' into canary_experimental 2023-04-26 13:34:57 +02:00
chss95cs@gmail.com
2fa2f1a78c Add more wrapper functions to ppc_context_t in kernel, want to switch…
… over to referencing state through ppc_context as much as possible, it'll make implementing things like kernel processes much easier in the future

Move forward definitions of kernel types into kernel_fwd.h

Stub implementation of  XamLoaderGetMediaInfoEx
Partially implement XamSetDashContext
implement XamGetDashContext
Stub implementation of XamUserIsUnsafeProgrammingAllowed
Stub implementation of XamUserGetSubscriptionType
Expanded the supported object types for ObReferenceObjectByHandle and wrapped the logic for encoding the type in a constexpr function
ObReferenceObjectByName was taking lpstring_t for first param, but the function actually takes X_ANSI_STRING ptr

NtReleaseMutant actually does not return anything from KeReleaseMutant, it just checks the handle and returns whether it was invalid.

Changed the raise/lower irql functions to just set the irql on the pcr instead of setting it on field of Processor, processor is a shared object and irql is per-thread

Semi-stub implementation of KeGetImagePageTableEntry. I locked at it in the HV and got it so the values are in the same range the HV returns + actually reflect the page & memory range, but i doubt its equal to the values the hv returns on real hw. Used by modern dashboards, don't know for what.
Log error message for ObDereferenceObject w/ null ptr.

Allocate a special fixed page that dashboards reference, currently don't know what the data on that page is supposed to be.
Add current_irql field to X_KPCR
Added Device object member of XObject::Type enum
Added some notes about other gpu registers, found a table of register names and indices in xam
2023-04-23 10:39:52 -04:00
Triang3l
8aaa6f1f7d [SPIR-V] Wrap 4-operand ops and 1-3-operand GLSL std calls 2023-04-19 21:44:24 +03:00
Triang3l
19d56001d2 [SPIR-V] Wrap NoContraction operations 2023-04-19 11:53:45 +03:00
Triang3l
78f1d55a36 [SPIR-V] Use Builder createSelectionMerge directly 2023-04-19 11:11:28 +03:00
Triang3l
64d2a80f79 [SPIR-V] Cleanup ALU emulation conditionals 2023-04-19 10:35:09 +03:00
Triang3l
eede38ff63 [SPIR-V] Remove more vec2-4 reserve calls 2023-04-18 22:05:02 +03:00
chss95cs@gmail.com
27c4cef1b5 Added logger flags, for selectively disabling categories of logging (cpu, apu, kernel). Need to make more log messages make use of these flags.
The "close window" keyboard hotkey (Guide-B) now toggles between loglevel -1 and the loglevel set in your config.
Added LoggerBatch class, which accumulates strings into the threads scratch buffer. This is only intended to be used for very high frequency debug logging. if it exhausts the thread buffer, it just silently stops.
Cleaned nearly 8 years of dust off of the pm4 packet disassembler code, now supports all packets that the command processor supports.
Added extremely verbose logging for gpu register writes. This is not compiled in outside of debug builds, requires LogLevel::Debug and log_guest_driven_gpu_register_written_values = true.
Added full logging of all PM4 packets in the cp. This is not compiled in outside of debug builds, requires LogLevel::Debug and disassemble_pm4.
Piggybacked an implementation of guest callstack backtraces using the stackpoints from enable_host_guest_stack_synchronization. If enable_host_guest_stack_synchronization = false, no backtraces can be obtained.
Added log_ringbuffer_kickoff_initiator_bts. when a thread updates the cp's read pointer, it dumps the backtrace of that thread
Changed the names of the gpu registers CALLBACK_ADDRESS and CALLBACK_CONTEXT to the correct names.
Added a note about CP_PROG_COUNTER
Added CP_RB_WPTR to the gpu register table
Added notes about CP_RB_CNTL and CP_RB_RPTR_ADDR. Both aren't necessary for HLE
Changed name of UNKNOWN_0E00 gpu register to TC_CNTL_STATUS. Games only seem to write 1 to it (L2 invalidate)
2023-04-16 12:42:42 -04:00
chrisps
12c9135843 Merge branch 'xenia-project:master' into canary_experimental 2023-04-16 09:11:39 -04:00
Triang3l
887fda55c2 [SPIR-V] Remove temp reserve for 4 or less elements 2023-04-13 22:43:44 +03:00
Triang3l
75d805245d [DXBC] discard pixels from kill with ROV instead of returning
Keep the current lane active as it may be needed for derivatives.
2023-04-09 20:13:22 +03:00
Gliniak
5e0c67438c Merge branch 'master' of https://github.com/xenia-project/xenia into canary_experimental 2023-04-09 17:28:04 +02:00
Gliniak
7fce8fce9d Revert "[D3D12] Added workaround for broken Geometry Shader in AMD 7900 Series GPU"
This reverts commit 2afd2cc4d6.
2023-04-09 17:27:55 +02:00
Triang3l
88c645d818 [D3D12] Don't use emit_then_cut due to RDNA 3 crash 2023-04-09 18:07:44 +03:00
Triang3l
baa2ff78d8 [Vulkan] Add missing stencil reference unpack in RT transfer + formatting fix 2023-03-30 22:40:40 +03:00
Triang3l
c238d8af55 [Vulkan] Fix FragStencilRef store type 2023-03-30 22:28:56 +03:00
Gliniak
23bd18cfca [GPU] Check if memory page is available while copying data 2023-03-11 16:20:01 +01:00
Gloria
d62fe21d47 RADV bug fix (#139)
* Use correct typing for stencil, dispatch launch on UI thread
* Clean up some LaunchPath code
2023-03-06 08:31:05 +01:00
Adrian
459497f0b6 Implemented Controller Hotkeys (#111)
Implemented Controller Hotkeys

Added controller hotkeys
Added guide button support for XInput and winkey

The hotkey configurations can be found in HID -> Display controller hotkeys
If the Xbox Gamebar overlay is enabled then use the Back button instead of the Guide button.

- Fixed hotkey thread destruction
- Fixed XINPUT_STATE by padding 4 bytes
- Added hotkey vibration for user feedback
- Replaced MessageBoxA with ImGuiDialog::ShowMessageBox

Co-authored-by: Margen67 <Margen67@users.noreply.github.com>
2023-01-13 09:17:43 +01:00
Gliniak
2afd2cc4d6 [D3D12] Added workaround for broken Geometry Shader in AMD 7900 Series GPU 2022-12-31 11:27:01 +01:00
Gliniak
26415cb8b1 Merge branch 'master' of https://github.com/xenia-project/xenia into canary_experimental 2022-12-31 11:19:01 +01:00
Joel Linn
b641e39c4d [ImGui] Use new ImageButton signature 2022-12-28 14:16:32 -06:00
Joel Linn
d6b5cbd634 [ImGui] Fix deprecated SetCursorPos use 2022-12-28 14:16:32 -06:00
Joel Linn
8f88bb237e [ImGui] Fix empty IDs 2022-12-28 14:16:32 -06:00
chss95cs@gmail.com
3952997116 Fix issue introduced yesterday where the final fetch constant would never be marked as written
Reorganized SystemPageFlags for sharedmemory, each field now goes into its own array, the three arrays are page aligned in a single virtual allocation
Refactored sharedmemory a bit, use tzcnt if available when finding ranges (faster on pre-zen4 amd cpus)
2022-12-15 08:35:36 -08:00
chss95cs@gmail.com
f931c34ecb Cleaned up for commit, moved WriteRegistersFromMemCommonSense code into WriteRegistersFromMem
optimized copy_and_swap_32_unaligned further
2022-12-14 11:34:33 -08:00
chss95cs@gmail.com
754293ffc3 Fix mistake with fetch constant dirty mask 2022-12-14 10:13:13 -08:00