4 Commits

Author	SHA1	Message	Date
chss95cs@gmail.com	968f656d96	Add separate VMX/fpu mxcsr ... Add support for constant operands for most fpu instructions Remove constant folding for most fpu cpde half float	2022-07-31 08:56:36 -07:00
Triang3l	fdec0ab332	[Code] Make union usage more consistent	2021-11-03 20:45:09 +03:00
Joel Linn	5284075cf9	[CPU] Misc GCC build fixes	2021-06-02 22:28:43 -05:00
Dr. Chat	6861cce492	[x64] Factor out a lot of the opcode handling code	2018-11-23 18:02:02 -06:00