Commit Graph

37 Commits

Author SHA1 Message Date
Gliniak
320102db34 Revert "[GPU] Reset mip levels for non-mipmapped type"
This reverts commit eeb96f91a5.
2024-08-10 18:15:16 +02:00
Radosław Gliński
eeb96f91a5 [GPU] Reset mip levels for non-mipmapped type
This prevent issue where fetch is partially invalid and contains invalid mip_page and mip_level for BaseMap type
2024-07-15 22:56:53 +02:00
Gliniak
26415cb8b1 Merge branch 'master' of https://github.com/xenia-project/xenia into canary_experimental 2022-12-31 11:19:01 +01:00
Triang3l
a37b57ca8d [GPU] Fix tiled mip tail extent calculation
Previously, for mips, the dimensions of the texture weren't rounded to powers of two before calculating the mip tail extent, resulting in the mip tail for a 260 blocks tall texture, that contains mips ending at Y of up to 36, having the Y extent calculated as 32. With rounding to powers of two, it would have been 64.

However, with the GetTiledAddressUpperBound functions, none of this is necessary at all (and neither is rounding the extents in TextureGuestLayout::Level to 32x32x4 blocks) - using the same code for calculating the XYZ extents of tiled textures as for linear textures now, which, for the mip tail, calculates the actual maximum coordinates of the mips stored in it - and rounding to tiles is done internally by GetTiledAddressUpperBound.
2022-10-23 21:26:47 +03:00
chss95cs@gmail.com
8f7f7dc6ad fixed wine crash from use of NtSetEventPriorityBoost
add xe::clear_lowest_bit, use it in place of shift-andnot in some bit iteration code
make is_allocated_ and is_enabled_ volatile in xma_context
preallocate avpacket buffer in XMAContext::Setup, the reallocations of the buffer in ffmpeg were showing up on profiles
check is_enabled and is_allocated BEFORE locking an xmacontext. XMA worker was spending most of its time locking and unlocking contexts
Removed XeDMAC, dma:: namespace. It was a bad idea and I couldn't make it work in the end. Kept vastcpy and moved it to the memory namespace instead
Made the rest of global_critical_region's members static. They never needed an instance.
Removed ifdef'ed out code from ring_buffer.h
Added EventInfo struct to threading, added Event::Query to aid with implementing NtQueryEvent.
Removed vector from WaitMultiple, instead use a fixed array of 64 handles that we populate. WaitForMultipleObjects cannot handle more than 64 objects.
Remove XE_MSVC_OPTIMIZE_SMALL() use in x64_sequences, x64 backend is now always size optimized because of premake
Make global_critical_region_ static constexpr in shared_memory.h to get rid of wasteage of 8 bytes (empty class=1byte, +alignment for next member=8)
Move trace-related data to the tail of SharedMemory to keep more important data together
In IssueDraw build an array of fetch constant addresses/sizes, then pre-lock the global lock before doing requestrange for each instead of individually locking within requestrange for each of them
Consistent access specifier protected for pm4_command_processor_declare
Devirtualize WriteOneRegisterFromRing.
Move ExecutePacket and ExecutePrimaryBuffer to pm4_command_buffer_x
Remove many redundant header inclusions access xenia-gpu
Minor microoptimization of ExecutePacketType0

Add TextureCache::RequestTextures for batch invocation of LoadTexturesData

Add TextureCache::LoadTexturesData for reducing the number of times we release and reacquire the global lock.
Ideally you should hold the global lock for as little time as possible, but if you are constantly acquiring and releasing it you are actually more likely to have contention
Add already_locked param to ObjectTable::LookupObject to help with reducing lock acquire/release pairs
Add missing checks to XAudioRegisterRenderDriverClient_entry. this is unlikely to fix anything, it was just an easy thing to do
Add NtQueryEvent system call implementation. I don't actually know of any games that need it.
Instead of using std::vector + push_back in KeWaitForMultipleObjects and xeNtWaitForMultipleObjectsEx use a fixed size array of 64 and track the count. More than 64 objects is not permitted by the kernel. The repeated reallocations from push_back were appearing unusually high on the profiler, but were masked until now by waitformultipleobjects natural overhead
Pre-lock the global lock before looking up each handle for xeNtWaitForMultipleObjectsEx and KeWaitForMultipleObjects.
Pre-lock before looking up the signal and waiter in NtSignalAndWaitForSingleObjectEx
add missing checks to NtWaitForMultipleObjectsEx
Support pre-locking in XObject::GetNativeObject
2022-10-08 09:55:17 -07:00
chss95cs@gmail.com
eb8154908c atomic cas use prefetchw if available
remove useless memorybarrier
remove double membarrier in wait pm4 cmd
add int64 cvar
use int64 cvar for x64 feature mask
Rework some functions that were frontend bound according to vtune placing some of their code in different noinline functions, profiling after indicating l1 cache misses decreased and perf of func increased
remove long vpinsrd dep chain code for conversion.h, instead do normal load+bswap or movbe if avail
Much faster entry table via split_map, code size could be improved though
GetResolveInfo was very large and had impact on icache, mark callees as noinline + msvc pragma optimize small
use log2 shifts instead of integer divides in memory
minor optimizations in PhysicalHeap::EnableAccessCallbacks, the majority of time in the function is spent looping, NOT calling Protect! Someone should optimize this function and rework the algo completely
remove wonky scheduling log message, it was spammy and unhelpful
lock count was unnecessary for criticalsection mutex, criticalsection is already a recursive mutex
brief notes i gotta run
2022-09-17 04:04:53 -07:00
chss95cs@gmail.com
20638c2e61 use Sleep(0) instead of SwitchToThread, should waste less power and help the os with scheduling.
PM4 buffer handling made a virtual member of commandprocessor, place the implementation/declaration into reusable macro files. this is probably the biggest boost here.
Optimized SET_CONSTANT/ LOAD_CONSTANT pm4 ops based on the register range they start writing at, this was also a nice boost

Expose X64 extension flags to code outside of x64 backend, so we can detect and use things like avx512, xop, avx2, etc in normal code
Add freelists for HIR structures to try to reduce the number of last level cache misses during optimization (currently disabled... fixme later)

Analyzed PGO feedback and reordered branches, uninlined functions, moved code out into different functions based on info from it in the PM4 functions, this gave like a 2% boost at best.

Added support for the db16cyc opcode, which is used often in xb360 spinlocks. before it was just being translated to nop, now on x64 we translate it to _mm_pause but may change that in the future to reduce cpu time wasted

texture util - all our divisors were powers of 2, instead we look up a shift. this made texture scaling slightly faster, more so on intel processors which seem to be worse at int divs. GetGuestTextureLayout is now a little faster, although it is still one of the heaviest functions in the emulator when scaling is on.

xe_unlikely_mutex was not a good choice for the guest clock lock, (running theory) on intel processors another thread may take a significant time to update the clock? maybe because of the uint64 division? really not sure, but switched it to xe_mutex. This fixed audio stutter that i had introduced to 1 or 2 games, fixed performance on that n64 rare game with the monkeys.
Took another crack at DMA implementation, another failure.
Instead of passing as a parameter, keep the ringbuffer reader as the first member of commandprocessor so it can be accessed through this
Added macro for noalias
Applied noalias to Memory::LookupHeap. This reduced the size of the executable by 7 kb.
Reworked kernel shim template, this shaved like 100kb off the exe and eliminated the indirect calls from the shim to the actual implementation. We still unconditionally generate string representations of kernel calls though :(, unless it is kHighFrequency

Add nvapi extensions support, currently unused. Will use CPUVISIBLE memory at some point
Inserted prefetches in a few places based on feedback from vtune.
Add native implementation of SHA int8 if all elements are the same

Vectorized comparisons for SetViewport, SetScissorRect
Vectorized ranged comparisons for WriteRegister
Add XE_MSVC_ASSUME
Move FormatInfo::name out of the structure, instead look up the name in a different table. Debug related data and critical runtime data are best kept apart
Templated UpdateSystemConstantValues based on ROV/RTV and primitive_polygonal
Add ArchFloatMask functions, these are for storing the results of floating point comparisons without doing costly float->int pipeline transfers (vucomiss/setb)
Use floatmasks in UpdateSystemConstantValues for checking if dirty, only transfer to int at end of function.
Instead of dirty |= (x == y) in UpdateSystemConstantValues, now we do dirty_u32 |= (x^y). if any of them are not equal, dirty_u32 will be nz, else if theyre all equal it will be zero. This is more friendly to register renaming and the lack of dependencies on EFLAGS lets the compiler reorder better
Add PrefetchSamplerParameters to D3D12TextureCache
use PrefetchSamplerParameters in UpdateBindings to eliminate cache misses that vtune detected

Add PrefetchTextureBinding to D3D12TextureCache
Prefetch texture bindings to get rid of more misses vtune detected (more accesses out of order with random strides)
Rewrote DMAC, still terrible though and have disabled it for now.
Replace tiny memcmp of 6 U64 in render_target_cache with inline loop, msvc fails to make it a loop and instead does a thunk to their memcmp function, which is optimized for larger sizes

PrefetchTextureBinding in AreActiveTextureSRVKeysUpToDate
Replace memcmp calls for pipelinedescription with handwritten cmp
Directly write some registers that dont have special handling in PM4 functions
Changed EstimateMaxY to try to eliminate mispredictions that vtune was reporting, msvc ended up turning the changed code into a series of blends

in ExecutePacketType3_EVENT_WRITE_EXT, instead of writing extents to an array on the stack and then doing xe_copy_and_swap_16 of the data to its dest, pre-swap each constant and then store those. msvc manages to unroll that into wider stores
stop logging XE_SWAP every time we receive XE_SWAP, stop logging the start and end of each viz query

Prefetch watch nodes in FireWatches based on feedback from vtune
Removed dead code from texture_info.cc
NOINLINE on GpuSwap, PGO builds did it so we should too.
2022-09-11 14:14:48 -07:00
Triang3l
382710bab7 [GPU] Normalize sampler clamp modes 2022-06-28 21:58:58 +03:00
Triang3l
2606fa5709 [GPU] Apply BaseMap MipFilter via samplers as it may be overridden
Make it have no effect on the texture resource as a resource may be used with samplers with different overrides. Also make sure magnification vs. minification is not undefined with it on Direct3D 12.
2022-06-26 18:41:38 +03:00
Triang3l
086a070fa9 [GPU] Explicitly cast bit field values in std::min/max
According to the integral promotion rules https://eel.is/c++draft/conv.prom#5.sentence-1 bit fields can be promoted to `int` if it's wide enough to store their value, and then otherwise, to `unsigned int`. Hopefully fixes Clang building (the `width_div_8` case).
2022-06-26 16:54:11 +03:00
Triang3l
84fcd5defa [GPU] Fix resolve destination offset and extent calculation 2022-06-02 21:47:30 +03:00
Triang3l
a9a072bf00 [GPU] Explain why a 32x32x4bpp linear texture takes 2 pages, not 1 [ci skip] 2022-06-01 13:00:23 +03:00
Triang3l
8bd244f277 [GPU] Better explanation for exact texture memory extent calculation [ci skip] 2022-06-01 12:55:16 +03:00
Triang3l
25594c918c [GPU] Fix tiled texture memory extent calculation 2022-05-31 23:17:33 +03:00
Triang3l
a4840e1992 [GPU] FIXME comment for 1bpb/2bpb texture tiled extent 2022-05-24 22:33:27 +03:00
Triang3l
d280b3953d [GPU] Texture object/binding management to common superclass 2022-05-14 16:18:10 +03:00
Triang3l
9606ff2a31 [D3D12] Fix 8192 texture size storage 2021-12-12 16:27:49 +03:00
Triang3l
e720e0a540 [Code] Remove game names from code comments (most of at least) 2021-09-05 21:27:40 +03:00
Triang3l
dd5ea87213 [GPU] Linear mip tail exact extent estimation 2021-05-15 18:19:26 +03:00
Triang3l
4eca2326c3 [GPU/D3D12] Support texture pitch, more precise texture extent/stride calculations 2021-05-13 23:02:11 +03:00
Triang3l
bd5f77bc3b [GPU] Common resolve code based on compute shaders, swap MSAA samples 1 and 2, change ROV write rounding, random refactoring 2020-08-09 21:33:10 +03:00
Triang3l
4bb0ca0e09 [GPU] Move all xenos.h to gpu::xenos, disambiguate Dimension/TextureDimension 2020-07-11 15:54:22 +03:00
Triang3l
713f26b5c8 [D3D12] Use typed buffers for texture untiling, calculate guest address once per thread 2020-07-03 20:03:53 +03:00
Triang3l
d26f84b36b [D3D12] Untile whole mip tail to make alignment assumptions later, other mip fixes 2020-06-23 23:49:42 +03:00
Triang3l
8a64861ec0 [DXBC] New tfetch: pre-swizzle signs, additive LOD + refactoring 2020-06-06 19:12:34 +03:00
Triang3l
a3b4c77fdb [GPU] Add texture_util::SwizzleSigns for later 2020-05-11 16:30:09 +03:00
Triang3l
47eee5e1c3 [GPU] Unified function for mip level bounds, BaseMap mip filter, small refactoring 2020-02-18 23:31:48 +03:00
Triang3l
08675ab65e [D3D12] 3D texture resolve 2019-04-25 08:37:55 +03:00
Triang3l
952819ed87 [D3D12] Don't 4KB-align sizes of resolve destinations 2018-12-13 15:22:16 +03:00
Triang3l
9427667a27 [D3D12] Experimental 2x resolution scale 2018-12-06 10:38:13 +03:00
Triang3l
251f078baf [D3D12] Fix mipmapped cubemaps and stacked textures 2018-10-29 22:40:29 +03:00
Triang3l
83c99bc811 [D3D12] Fix resolve region handling 2018-10-28 14:36:41 +03:00
Triang3l
c4f80aac0d [D3D12] EDRAM layout of a rectangle and other resolve stuff 2018-08-22 17:33:43 +03:00
Triang3l
cfd3821b83 [D3D12] DXT1 untiling 2018-08-06 20:10:53 +03:00
Triang3l
265d6eb9df [D3D12] Fix texture size calculation and add texture creation logging 2018-08-05 18:45:57 +03:00
Triang3l
b50d6d844f [D3D12] Texture object creation 2018-08-05 17:43:00 +03:00
Triang3l
8a24ff5078 [D3D12] Texture utility functions, all block sizes and bpp 2018-08-03 23:11:09 +03:00