# Xenia Canary — PowerPC Instruction Reference

Complete catalog of all **455 PowerPC instructions** implemented in the Xenia (canary)
Xbox 360 emulator. These instructions are defined in `tools/ppc-instructions.xml` and
code-generated into the emitter/decoder/disassembler pipeline.

## Architecture Overview

```
PPC Binary → Decoder (ppc_opcode_lookup_gen.cc)
           → Frontend Emit (ppc_emit_*.cc)  →  HIR (intermediate representation)
           → Backend Sequences (x64_seq_*.cc / a64_seq_*.cc)  →  Host Machine Code
```

### Source Files

| File | Role |
|------|------|
| `tools/ppc-instructions.xml` | Master instruction definitions (source of truth) |
| `tools/ppc-table-gen.py` | Code generator |
| `src/xenia/cpu/ppc/ppc_opcode.h` | Generated enum (`PPCOpcode`) |
| `src/xenia/cpu/ppc/ppc_opcode_table_gen.cc` | Generated opcode info table |
| `src/xenia/cpu/ppc/ppc_opcode_lookup_gen.cc` | Generated instruction decoder |
| `src/xenia/cpu/ppc/ppc_opcode_disasm_gen.cc` | Generated disassembler |
| `src/xenia/cpu/ppc/ppc_emit_alu.cc` | Integer/ALU emission (~68 handlers) |
| `src/xenia/cpu/ppc/ppc_emit_control.cc` | Branch/control emission (~28 handlers) |
| `src/xenia/cpu/ppc/ppc_emit_memory.cc` | Load/store emission (~80 handlers) |
| `src/xenia/cpu/ppc/ppc_emit_fpu.cc` | Floating-point emission (~40 handlers) |
| `src/xenia/cpu/ppc/ppc_emit_altivec.cc` | Vector/VMX emission (~306 handlers) |

### Backend Targets

| Backend | Directory |
|---------|-----------|
| x86-64 | `src/xenia/cpu/backend/x64/` |
| ARM64 | `src/xenia/cpu/backend/a64/` |

### Instruction Encoding Formats

**27 formats:** `A`, `B`, `D`, `DCBZ`, `DS`, `I`, `M`, `MD`, `MDS`, `SC`, `VA`, `VC`, `VX`, `VX128`, `VX128_1`, `VX128_2`, `VX128_3`, `VX128_4`, `VX128_5`, `VX128_P`, `VX128_R`, `X`, `XFL`, `XFX`, `XL`, `XO`, `XS`

---

## Instruction Catalog

### Summary

| Category | Count |
|----------|------:|
| Integer / ALU | 70 |
| Branch / System | 9 |
| Condition Register / SPR | 26 |
| Floating-Point | 33 |
| Memory (Load/Store/Cache) | 112 |
| Vector / VMX (AltiVec) | 205 |
| **Total** | **455** |

---

### Integer / ALU (70 instructions)

| # | Mnemonic | Description | Form | Opcode |
|--:|----------|-------------|------|--------|
| 1 | `addx` | Add | XO | `7c000214` |
| 2 | `addcx` | Add Carrying | XO | `7c000014` |
| 3 | `addex` | Add Extended | XO | `7c000114` |
| 4 | `addi` | Add Immediate | D | `38000000` |
| 5 | `addic` | Add Immediate Carrying | D | `30000000` |
| 6 | `addic.` | Add Immediate Carrying and Record | D | `34000000` |
| 7 | `addis` | Add Immediate Shifted | D | `3c000000` |
| 8 | `addmex` | Add to Minus One Extended | XO | `7c0001d4` |
| 9 | `addzex` | Add to Zero Extended | XO | `7c000194` |
| 10 | `andx` | AND | X | `7c000038` |
| 11 | `andcx` | AND with Complement | X | `7c000078` |
| 12 | `andi.` | AND Immediate | D | `70000000` |
| 13 | `andis.` | AND Immediate Shifted | D | `74000000` |
| 14 | `cmp` | Compare | X | `7c000000` |
| 15 | `cmpi` | Compare Immediate | D | `2c000000` |
| 16 | `cmpl` | Compare Logical | X | `7c000040` |
| 17 | `cmpli` | Compare Logical Immediate | D | `28000000` |
| 18 | `cntlzdx` | Count Leading Zeros Doubleword | X | `7c000074` |
| 19 | `cntlzwx` | Count Leading Zeros Word | X | `7c000034` |
| 20 | `divdx` | Divide Doubleword | XO | `7c0003d2` |
| 21 | `divdux` | Divide Doubleword Unsigned | XO | `7c000392` |
| 22 | `divwx` | Divide Word | XO | `7c0003d6` |
| 23 | `divwux` | Divide Word Unsigned | XO | `7c000396` |
| 24 | `eieio` | Enforce In-Order Execution of I/O | X | `7c0006ac` |
| 25 | `eqvx` | Equivalent | X | `7c000238` |
| 26 | `extsbx` | Extend Sign Byte | X | `7c000774` |
| 27 | `extshx` | Extend Sign Half Word | X | `7c000734` |
| 28 | `extswx` | Extend Sign Word | X | `7c0007B4` |
| 29 | `isync` | Instruction Synchronize | XL | `4c00012c` |
| 30 | `mulhdx` | Multiply High Doubleword | XO | `7c000092` |
| 31 | `mulhdux` | Multiply High Doubleword Unsigned | XO | `7c000012` |
| 32 | `mulhwx` | Multiply High Word | XO | `7c000096` |
| 33 | `mulhwux` | Multiply High Word Unsigned | XO | `7c000016` |
| 34 | `mulldx` | Multiply Low Doubleword | XO | `7c0001d2` |
| 35 | `mulli` | Multiply Low Immediate | D | `1c000000` |
| 36 | `mullwx` | Multiply Low Word | XO | `7c0001d6` |
| 37 | `nandx` | NAND | X | `7c0003b8` |
| 38 | `negx` | Negate | XO | `7c0000d0` |
| 39 | `norx` | NOR | X | `7c0000f8` |
| 40 | `orx` | OR | X | `7c000378` |
| 41 | `orcx` | OR with Complement | X | `7c000338` |
| 42 | `ori` | OR Immediate | D | `60000000` |
| 43 | `oris` | OR Immediate Shifted | D | `64000000` |
| 44 | `rldclx` | Rotate Left Doubleword then Clear Left | MDS | `78000010` |
| 45 | `rldcrx` | Rotate Left Doubleword then Clear Right | MDS | `78000012` |
| 46 | `rldicx` | Rotate Left Doubleword Immediate then Clear | MD | `78000008` |
| 47 | `rldiclx` | Rotate Left Doubleword Immediate then Clear Left | MD | `78000000` |
| 48 | `rldicrx` | Rotate Left Doubleword Immediate then Clear Right | MD | `78000004` |
| 49 | `rldimix` | Rotate Left Doubleword Immediate then Mask Insert | MD | `7800000C` |
| 50 | `rlwimix` | Rotate Left Word Immediate then Mask Insert | M | `50000000` |
| 51 | `rlwinmx` | Rotate Left Word Immediate then AND with Mask | M | `54000000` |
| 52 | `rlwnmx` | Rotate Left Word then AND with Mask | M | `5c000000` |
| 53 | `sldx` | Shift Left Doubleword | X | `7c000036` |
| 54 | `slwx` | Shift Left Word | X | `7c000030` |
| 55 | `sradx` | Shift Right Algebraic Doubleword | X | `7c000634` |
| 56 | `sradix` | Shift Right Algebraic Doubleword Immediate | XS | `7c000674` |
| 57 | `srawx` | Shift Right Algebraic Word | X | `7c000630` |
| 58 | `srawix` | Shift Right Algebraic Word Immediate | X | `7c000670` |
| 59 | `srdx` | Shift Right Doubleword | X | `7c000436` |
| 60 | `srwx` | Shift Right Word | X | `7c000430` |
| 61 | `subfx` | Subtract From | XO | `7c000050` |
| 62 | `subfcx` | Subtract From Carrying | XO | `7c000010` |
| 63 | `subfex` | Subtract From Extended | XO | `7c000110` |
| 64 | `subficx` | Subtract From Immediate Carrying | D | `20000000` |
| 65 | `subfmex` | Subtract From Minus One Extended | XO | `7c0001d0` |
| 66 | `subfzex` | Subtract From Zero Extended | XO | `7c000190` |
| 67 | `sync` | Synchronize | X | `7c0004ac` |
| 68 | `xorx` | XOR | X | `7c000278` |
| 69 | `xori` | XOR Immediate | D | `68000000` |
| 70 | `xoris` | XOR Immediate Shifted | D | `6c000000` |

### Branch / System (9 instructions)

| # | Mnemonic | Description | Form | Opcode |
|--:|----------|-------------|------|--------|
| 1 | `bx` | Branch | I | `48000000` |
| 2 | `bcx` | Branch Conditional | B | `40000000` |
| 3 | `bcctrx` | Branch Conditional to Count Register | XL | `4c000420` |
| 4 | `bclrx` | Branch Conditional to Link Register | XL | `4c000020` |
| 5 | `sc` | System Call | SC | `44000002` |
| 6 | `td` | Trap Doubleword | X | `7c000088` |
| 7 | `tdi` | Trap Doubleword Immediate | D | `08000000` |
| 8 | `tw` | Trap Word | X | `7c000008` |
| 9 | `twi` | Trap Word Immediate | D | `0c000000` |

### Condition Register / SPR (26 instructions)

| # | Mnemonic | Description | Form | Opcode |
|--:|----------|-------------|------|--------|
| 1 | `crand` | Condition Register AND | XL | `4c000202` |
| 2 | `crandc` | Condition Register AND with Complement | XL | `4c000102` |
| 3 | `creqv` | Condition Register Equivalent | XL | `4c000242` |
| 4 | `crnand` | Condition Register NAND | XL | `4c0001c2` |
| 5 | `crnor` | Condition Register NOR | XL | `4c000042` |
| 6 | `cror` | Condition Register OR | XL | `4c000382` |
| 7 | `crorc` | Condition Register OR with Complement | XL | `4c000342` |
| 8 | `crxor` | Condition Register XOR | XL | `4c000182` |
| 9 | `mcrf` | Move Condition Register Field | XL | `4c000000` |
| 10 | `mcrfs` | Move to Condition Register from FPSCR | X | `fc000080` |
| 11 | `mcrxr` | Move to Condition Register from XER | X | `7c000400` |
| 12 | `mfcr` | Move from Condition Register | X | `7c000026` |
| 13 | `mffsx` | Move from FPSCR | X | `fc00048e` |
| 14 | `mfmsr` | Move from Machine State Register | X | `7c0000a6` |
| 15 | `mfspr` | Move from Special-Purpose Register | XFX | `7c0002a6` |
| 16 | `mftb` | Move from Time Base | XFX | `7c0002e6` |
| 17 | `mtcrf` | Move to Condition Register Fields | XFX | `7c000120` |
| 18 | `mtfsb0x` | Move to FPSCR Bit 0 | X | `fc00008c` |
| 19 | `mtfsb1x` | Move to FPSCR Bit 1 | X | `fc00004c` |
| 20 | `mtfsfx` | Move to FPSCR Fields | XFL | `fc00058e` |
| 21 | `mtfsfix` | Move to FPSCR Field Immediate | X | `fc00010c` |
| 22 | `mtmsr` | Move to Machine State Register | X | `7c000124` |
| 23 | `mtmsrd` | Move to Machine State Register Doubleword | X | `7c000164` |
| 24 | `mtspr` | Move to Special-Purpose Register | XFX | `7c0003a6` |
| 25 | `mfvscr` | Move from VSCR | VX | `10000604` |
| 26 | `mtvscr` | Move to VSCR | VX | `10000644` |

### Floating-Point (33 instructions)

| # | Mnemonic | Description | Form | Opcode |
|--:|----------|-------------|------|--------|
| 1 | `fabsx` | Floating Absolute Value | X | `fc000210` |
| 2 | `faddx` | Floating Add | A | `fc00002a` |
| 3 | `faddsx` | Floating Add Single | A | `ec00002a` |
| 4 | `fcfidx` | Floating Convert From Integer Doubleword | X | `FC00069C` |
| 5 | `fcmpo` | Floating Compare Ordered | X | `fc000040` |
| 6 | `fcmpu` | Floating Compare Unordered | X | `fc000000` |
| 7 | `fctidx` | Floating Convert to Integer Doubleword | X | `fc00065c` |
| 8 | `fctidzx` | Floating Convert to Integer Doubleword with Round Toward Zero | X | `fc00065e` |
| 9 | `fctiwx` | Floating Convert to Integer Word | X | `fc00001c` |
| 10 | `fctiwzx` | Floating Convert to Integer Word with Round Toward Zero | X | `fc00001e` |
| 11 | `fdivx` | Floating Divide | A | `fc000024` |
| 12 | `fdivsx` | Floating Divide Single | A | `ec000024` |
| 13 | `fmaddx` | Floating Multiply-Add | A | `fc00003a` |
| 14 | `fmaddsx` | Floating Multiply-Add Single | A | `ec00003a` |
| 15 | `fmrx` | Floating Move Register | X | `fc000090` |
| 16 | `fmsubx` | Floating Multiply-Subtract | A | `fc000038` |
| 17 | `fmsubsx` | Floating Multiply-Subtract Single | A | `ec000038` |
| 18 | `fmulx` | Floating Multiply | A | `fc000032` |
| 19 | `fmulsx` | Floating Multiply Single | A | `ec000032` |
| 20 | `fnabsx` | Floating Negative Absolute Value | X | `fc000110` |
| 21 | `fnegx` | Floating Negate | X | `fc000050` |
| 22 | `fnmaddx` | Floating Negative Multiply-Add | A | `fc00003e` |
| 23 | `fnmaddsx` | Floating Negative Multiply-Add Single | A | `ec00003e` |
| 24 | `fnmsubx` | Floating Negative Multiply-Subtract | A | `fc00003c` |
| 25 | `fnmsubsx` | Floating Negative Multiply-Subtract Single | A | `ec00003c` |
| 26 | `fresx` | Floating Reciprocal Estimate Single | A | `ec000030` |
| 27 | `frspx` | Floating Round to Single | X | `fc000018` |
| 28 | `frsqrtex` | Floating Reciprocal Square Root Estimate | A | `fc000034` |
| 29 | `fselx` | Floating Select | A | `fc00002e` |
| 30 | `fsqrtx` | Floating Square Root | A | `fc00002c` |
| 31 | `fsqrtsx` | Floating Square Root Single | A | `ec00002c` |
| 32 | `fsubx` | Floating Subtract | A | `fc000028` |
| 33 | `fsubsx` | Floating Subtract Single | A | `ec000028` |

### Memory (Load/Store/Cache) (112 instructions)

| # | Mnemonic | Description | Form | Opcode |
|--:|----------|-------------|------|--------|
| 1 | `dcbf` | Data Cache Block Flush | X | `7c0000ac` |
| 2 | `dcbi` | Data Cache Block Invalidate | X | `7c0003ac` |
| 3 | `dcbst` | Data Cache Block Store | X | `7c00006c` |
| 4 | `dcbt` | Data Cache Block Touch | X | `7c00022c` |
| 5 | `dcbtst` | Data Cache Block Touch for Store | X | `7c0001ec` |
| 6 | `dcbz` | Data Cache Block Clear to Zero | DCBZ | `7c0007ec` |
| 7 | `dcbz128` | Data Cache Block Clear to Zero 128 | DCBZ | `7c2007ec` |
| 8 | `icbi` | Instruction Cache Block Invalidate | X | `7c0007ac` |
| 9 | `lbz` | Load Byte and Zero | D | `88000000` |
| 10 | `lbzu` | Load Byte and Zero with Update | D | `8c000000` |
| 11 | `lbzux` | Load Byte and Zero with Update Indexed | X | `7c0000ee` |
| 12 | `lbzx` | Load Byte and Zero Indexed | X | `7c0000ae` |
| 13 | `ld` | Load Doubleword | DS | `E8000000` |
| 14 | `ldarx` | Load Doubleword and Reserve Indexed | X | `7C0000A8` |
| 15 | `ldbrx` | Load Doubleword Byte-Reverse Indexed | X | `7C000428` |
| 16 | `ldu` | Load Doubleword with Update | DS | `E8000001` |
| 17 | `ldux` | Load Doubleword with Update Indexed | X | `7c00006a` |
| 18 | `ldx` | Load Doubleword Indexed | X | `7c00002a` |
| 19 | `lfd` | Load Floating-Point Double | D | `c8000000` |
| 20 | `lfdu` | Load Floating-Point Double with Update | D | `cc000000` |
| 21 | `lfdux` | Load Floating-Point Double with Update Indexed | X | `7c0004ee` |
| 22 | `lfdx` | Load Floating-Point Double Indexed | X | `7c0004ae` |
| 23 | `lfs` | Load Floating-Point Single | D | `c0000000` |
| 24 | `lfsu` | Load Floating-Point Single with Update | D | `c4000000` |
| 25 | `lfsux` | Load Floating-Point Single with Update Indexed | X | `7c00046e` |
| 26 | `lfsx` | Load Floating-Point Single Indexed | X | `7c00042e` |
| 27 | `lha` | Load Half Word Algebraic | D | `a8000000` |
| 28 | `lhau` | Load Half Word Algebraic with Update | D | `ac000000` |
| 29 | `lhaux` | Load Half Word Algebraic with Update Indexed | X | `7c0002ee` |
| 30 | `lhax` | Load Half Word Algebraic Indexed | X | `7c0002ae` |
| 31 | `lhbrx` | Load Half Word Byte-Reverse Indexed | X | `7c00062c` |
| 32 | `lhz` | Load Half Word and Zero | D | `a0000000` |
| 33 | `lhzu` | Load Half Word and Zero with Update | D | `a4000000` |
| 34 | `lhzux` | Load Half Word and Zero with Update Indexed | X | `7c00026e` |
| 35 | `lhzx` | Load Half Word and Zero Indexed | X | `7c00022e` |
| 36 | `lmw` | Load Multiple Word | D | `b8000000` |
| 37 | `lswi` | Load String Word Immediate | X | `7c0004aa` |
| 38 | `lswx` | Load String Word Indexed | X | `7c00042a` |
| 39 | `lwa` | Load Word Algebraic | DS | `e8000002` |
| 40 | `lwarx` | Load Word and Reserve Indexed | X | `7c000028` |
| 41 | `lwaux` | Load Word Algebraic with Update Indexed | X | `7c0002ea` |
| 42 | `lwax` | Load Word Algebraic Indexed | X | `7c0002aa` |
| 43 | `lwbrx` | Load Word Byte-Reverse Indexed | X | `7c00042c` |
| 44 | `lwz` | Load Word and Zero | D | `80000000` |
| 45 | `lwzu` | Load Word and Zero with Update | D | `84000000` |
| 46 | `lwzux` | Load Word and Zero with Update Indexed | X | `7c00006e` |
| 47 | `lwzx` | Load Word and Zero Indexed | X | `7c00002e` |
| 48 | `stb` | Store Byte | D | `98000000` |
| 49 | `stbu` | Store Byte with Update | D | `9c000000` |
| 50 | `stbux` | Store Byte with Update Indexed | X | `7c0001ee` |
| 51 | `stbx` | Store Byte Indexed | X | `7c0001ae` |
| 52 | `std` | Store Doubleword | DS | `f8000000` |
| 53 | `stdbrx` | Store Doubleword Byte-Reverse Indexed | X | `7c000528` |
| 54 | `stdcx` | Store Doubleword Conditional Indexed | X | `7c0001ad` |
| 55 | `stdu` | Store Doubleword with Update | DS | `f8000001` |
| 56 | `stdux` | Store Doubleword with Update Indexed | X | `7c00016a` |
| 57 | `stdx` | Store Doubleword Indexed | X | `7c00012a` |
| 58 | `stfd` | Store Floating-Point Double | D | `d8000000` |
| 59 | `stfdu` | Store Floating-Point Double with Update | D | `dc000000` |
| 60 | `stfdux` | Store Floating-Point Double with Update Indexed | X | `7c0005ee` |
| 61 | `stfdx` | Store Floating-Point Double Indexed | X | `7c0005ae` |
| 62 | `stfiwx` | Store Floating-Point as Integer Word Indexed | X | `7c0007ae` |
| 63 | `stfs` | Store Floating-Point Single | D | `d0000000` |
| 64 | `stfsu` | Store Floating-Point Single with Update | D | `d4000000` |
| 65 | `stfsux` | Store Floating-Point Single with Update Indexed | X | `7c00056e` |
| 66 | `stfsx` | Store Floating-Point Single Indexed | X | `7c00052e` |
| 67 | `sth` | Store Half Word | D | `b0000000` |
| 68 | `sthbrx` | Store Half Word Byte-Reverse Indexed | X | `7c00072c` |
| 69 | `sthu` | Store Half Word with Update | D | `b4000000` |
| 70 | `sthux` | Store Half Word with Update Indexed | X | `7c00036e` |
| 71 | `sthx` | Store Half Word Indexed | X | `7c00032e` |
| 72 | `stmw` | Store Multiple Word | D | `bc000000` |
| 73 | `stswi` | Store String Word Immediate | X | `7c0005aa` |
| 74 | `stswx` | Store String Word Indexed | X | `7c00052a` |
| 75 | `stw` | Store Word | D | `90000000` |
| 76 | `stwbrx` | Store Word Byte-Reverse Indexed | X | `7c00052c` |
| 77 | `stwcx` | Store Word Conditional Indexed | X | `7c00012d` |
| 78 | `stwu` | Store Word with Update | D | `94000000` |
| 79 | `stwux` | Store Word with Update Indexed | X | `7c00016e` |
| 80 | `stwx` | Store Word Indexed | X | `7c00012e` |
| 81 | `lvebx` | Load Vector Element Byte Indexed | X | `7c00000e` |
| 82 | `lvehx` | Load Vector Element Half Word Indexed | X | `7c00004e` |
| 83 | `lvewx` | Load Vector Element Word Indexed | X | `7c00008e` |
| 84 | `lvewx128` | Load Vector Element Word Indexed 128 | VX128_1 | `10000083` |
| 85 | `lvx` | Load Vector Indexed | X | `7c0000ce` |
| 86 | `lvx128` | Load Vector Indexed 128 | VX128_1 | `100000C3` |
| 87 | `lvxl` | Load Vector Indexed LRU | X | `7c0002ce` |
| 88 | `lvxl128` | Load Vector Indexed LRU 128 | VX128_1 | `100002C3` |
| 89 | `lvlx` | Load Vector Left Indexed | X | `7C00040E` |
| 90 | `lvlx128` | Load Vector Left Indexed 128 | VX128_1 | `10000403` |
| 91 | `lvlxl` | Load Vector Left Indexed LRU | X | `7C00060E` |
| 92 | `lvlxl128` | Load Vector Left Indexed LRU 128 | VX128_1 | `10000603` |
| 93 | `lvrx` | Load Vector Right Indexed | X | `7C00044E` |
| 94 | `lvrx128` | Load Vector Right Indexed 128 | VX128_1 | `10000443` |
| 95 | `lvrxl` | Load Vector Right Indexed LRU | X | `7C00064E` |
| 96 | `lvrxl128` | Load Vector Right Indexed LRU 128 | VX128_1 | `10000643` |
| 97 | `stvebx` | Store Vector Element Byte Indexed | X | `7c00010e` |
| 98 | `stvehx` | Store Vector Element Half Word Indexed | X | `7c00014e` |
| 99 | `stvewx` | Store Vector Element Word Indexed | X | `7c00018e` |
| 100 | `stvewx128` | Store Vector Element Word Indexed 128 | VX128_1 | `10000183` |
| 101 | `stvx` | Store Vector Indexed | X | `7c0001ce` |
| 102 | `stvx128` | Store Vector Indexed 128 | VX128_1 | `100001c3` |
| 103 | `stvxl` | Store Vector Indexed LRU | X | `7c0003ce` |
| 104 | `stvxl128` | Store Vector Indexed LRU 128 | VX128_1 | `100003c3` |
| 105 | `stvlx` | Store Vector Left Indexed | X | `7c00050e` |
| 106 | `stvlx128` | Store Vector Left Indexed 128 | VX128_1 | `10000503` |
| 107 | `stvlxl` | Store Vector Left Indexed LRU | X | `7c00070e` |
| 108 | `stvlxl128` | Store Vector Left Indexed LRU 128 | VX128_1 | `10000703` |
| 109 | `stvrx` | Store Vector Right Indexed | X | `7c00054e` |
| 110 | `stvrx128` | Store Vector Right Indexed 128 | VX128_1 | `10000543` |
| 111 | `stvrxl` | Store Vector Right Indexed LRU | X | `7c00074e` |
| 112 | `stvrxl128` | Store Vector Right Indexed LRU 128 | VX128_1 | `10000743` |

### Vector / VMX (AltiVec) (205 instructions)

| # | Mnemonic | Description | Form | Opcode |
|--:|----------|-------------|------|--------|
| 1 | `lvsl` | Load Vector for Shift Left Indexed | X | `7c00000c` |
| 2 | `lvsl128` | Load Vector for Shift Left Indexed 128 | VX128_1 | `10000003` |
| 3 | `lvsr` | Load Vector for Shift Right Indexed | X | `7c00004c` |
| 4 | `lvsr128` | Load Vector for Shift Right Indexed 128 | VX128_1 | `10000043` |
| 5 | `vaddcuw` | Vector Add Carryout Unsigned Word | VX | `10000180` |
| 6 | `vaddfp` | Vector Add Floating Point | VX | `1000000A` |
| 7 | `vaddfp128` | Vector128 Add Floating Point | VX128 | `14000010` |
| 8 | `vaddsbs` | Vector Add Signed Byte Saturate | VX | `10000300` |
| 9 | `vaddshs` | Vector Add Signed Half Word Saturate | VX | `10000340` |
| 10 | `vaddsws` | Vector Add Signed Word Saturate | VX | `10000380` |
| 11 | `vaddubm` | Vector Add Unsigned Byte Modulo | VX | `10000000` |
| 12 | `vaddubs` | Vector Add Unsigned Byte Saturate | VX | `10000200` |
| 13 | `vadduhm` | Vector Add Unsigned Half Word Modulo | VX | `10000040` |
| 14 | `vadduhs` | Vector Add Unsigned Half Word Saturate | VX | `10000240` |
| 15 | `vadduwm` | Vector Add Unsigned Word Modulo | VX | `10000080` |
| 16 | `vadduws` | Vector Add Unsigned Word Saturate | VX | `10000280` |
| 17 | `vand` | Vector Logical AND | VX | `10000404` |
| 18 | `vand128` | Vector128 Logical AND | VX128 | `14000210` |
| 19 | `vandc` | Vector Logical AND with Complement | VX | `10000444` |
| 20 | `vandc128` | Vector128 Logical AND with Complement | VX128 | `14000250` |
| 21 | `vavgsb` | Vector Average Signed Byte | VX | `10000502` |
| 22 | `vavgsh` | Vector Average Signed Half Word | VX | `10000542` |
| 23 | `vavgsw` | Vector Average Signed Word | VX | `10000582` |
| 24 | `vavgub` | Vector Average Unsigned Byte | VX | `10000402` |
| 25 | `vavguh` | Vector Average Unsigned Half Word | VX | `10000442` |
| 26 | `vavguw` | Vector Average Unsigned Word | VX | `10000482` |
| 27 | `vcfsx` | Vector Convert from Signed Fixed-Point Word | VX | `1000034A` |
| 28 | `vcfux` | Vector Convert from Unsigned Fixed-Point Word | VX | `1000030A` |
| 29 | `vcmpbfp` | Vector Compare Bounds Floating Point | VC | `100003C6` |
| 30 | `vcmpbfp128` | Vector128 Compare Bounds Floating Point | VX128_R | `18000180` |
| 31 | `vcmpeqfp` | Vector Compare Equal-to Floating Point | VC | `100000C6` |
| 32 | `vcmpeqfp128` | Vector128 Compare Equal-to Floating Point | VX128_R | `18000000` |
| 33 | `vcmpequb` | Vector Compare Equal-to Unsigned Byte | VC | `10000006` |
| 34 | `vcmpequh` | Vector Compare Equal-to Unsigned Half Word | VC | `10000046` |
| 35 | `vcmpequw` | Vector Compare Equal-to Unsigned Word | VC | `10000086` |
| 36 | `vcmpequw128` | Vector128 Compare Equal-to Unsigned Word | VX128_R | `18000200` |
| 37 | `vcmpgefp` | Vector Compare Greater-Than-or-Equal-to Floating Point | VC | `100001C6` |
| 38 | `vcmpgefp128` | Vector128 Compare Greater-Than-or-Equal-to Floating Point | VX128_R | `18000080` |
| 39 | `vcmpgtfp` | Vector Compare Greater-Than Floating Point | VC | `100002C6` |
| 40 | `vcmpgtfp128` | Vector128 Compare Greater-Than Floating-Point | VX128_R | `18000100` |
| 41 | `vcmpgtsb` | Vector Compare Greater-Than Signed Byte | VC | `10000306` |
| 42 | `vcmpgtsh` | Vector Compare Greater-Than Signed Half Word | VC | `10000346` |
| 43 | `vcmpgtsw` | Vector Compare Greater-Than Signed Word | VC | `10000386` |
| 44 | `vcmpgtub` | Vector Compare Greater-Than Unsigned Byte | VC | `10000206` |
| 45 | `vcmpgtuh` | Vector Compare Greater-Than Unsigned Half Word | VC | `10000246` |
| 46 | `vcmpgtuw` | Vector Compare Greater-Than Unsigned Word | VC | `10000286` |
| 47 | `vctsxs` | Vector Convert to Signed Fixed-Point Word Saturate | VX | `100003CA` |
| 48 | `vctuxs` | Vector Convert to Unsigned Fixed-Point Word Saturate | VX | `1000038A` |
| 49 | `vexptefp` | Vector 2 Raised to the Exponent Estimate Floating Point | VX | `1000018A` |
| 50 | `vexptefp128` | Vector128 Log2 Estimate Floating Point | VX128_3 | `180006B0` |
| 51 | `vlogefp` | Vector Log2 Estimate Floating Point | VX | `100001CA` |
| 52 | `vlogefp128` | Vector128 Log2 Estimate Floating Point | VX128_3 | `180006F0` |
| 53 | `vmaddfp` | Vector Multiply-Add Floating Point | VA | `1000002E` |
| 54 | `vmaddfp128` | Vector128 Multiply Add Floating Point | VX128 | `140000D0` |
| 55 | `vmaxfp` | Vector Maximum Floating Point | VX | `1000040A` |
| 56 | `vmaxfp128` | Vector128 Maximum Floating Point | VX128 | `18000280` |
| 57 | `vmaxsb` | Vector Maximum Signed Byte | VX | `10000102` |
| 58 | `vmaxsh` | Vector Maximum Signed Half Word | VX | `10000142` |
| 59 | `vmaxsw` | Vector Maximum Signed Word | VX | `10000182` |
| 60 | `vmaxub` | Vector Maximum Unsigned Byte | VX | `10000002` |
| 61 | `vmaxuh` | Vector Maximum Unsigned Half Word | VX | `10000042` |
| 62 | `vmaxuw` | Vector Maximum Unsigned Word | VX | `10000082` |
| 63 | `vmhaddshs` | Vector Multiply-High and Add Signed Signed Half Word Saturate | VA | `10000020` |
| 64 | `vmhraddshs` | Vector Multiply-High Round and Add Signed Signed Half Word Saturate | VA | `10000021` |
| 65 | `vminfp` | Vector Minimum Floating Point | VX | `1000044A` |
| 66 | `vminfp128` | Vector128 Minimum Floating Point | VX128 | `180002C0` |
| 67 | `vminsb` | Vector Minimum Signed Byte | VX | `10000302` |
| 68 | `vminsh` | Vector Minimum Signed Half Word | VX | `10000342` |
| 69 | `vminsw` | Vector Minimum Signed Word | VX | `10000382` |
| 70 | `vminub` | Vector Minimum Unsigned Byte | VX | `10000202` |
| 71 | `vminuh` | Vector Minimum Unsigned Half Word | VX | `10000242` |
| 72 | `vminuw` | Vector Minimum Unsigned Word | VX | `10000282` |
| 73 | `vmladduhm` | Vector Multiply-Low and Add Unsigned Half Word Modulo | VA | `10000022` |
| 74 | `vmrghb` | Vector Merge High Byte | VX | `1000000C` |
| 75 | `vmrghh` | Vector Merge High Half Word | VX | `1000004C` |
| 76 | `vmrghw` | Vector Merge High Word | VX | `1000008C` |
| 77 | `vmrghw128` | Vector128 Merge High Word | VX128 | `18000300` |
| 78 | `vmrglb` | Vector Merge Low Byte | VX | `1000010C` |
| 79 | `vmrglh` | Vector Merge Low Half Word | VX | `1000014C` |
| 80 | `vmrglw` | Vector Merge Low Word | VX | `1000018C` |
| 81 | `vmrglw128` | Vector128 Merge Low Word | VX128 | `18000340` |
| 82 | `vmsummbm` | Vector Multiply-Sum Mixed-Sign Byte Modulo | VA | `10000025` |
| 83 | `vmsumshm` | Vector Multiply-Sum Signed Half Word Modulo | VA | `10000028` |
| 84 | `vmsumshs` | Vector Multiply-Sum Signed Half Word Saturate | VA | `10000029` |
| 85 | `vmsumubm` | Vector Multiply-Sum Unsigned Byte Modulo | VA | `10000024` |
| 86 | `vmsumuhm` | Vector Multiply-Sum Unsigned Half Word Modulo | VA | `10000026` |
| 87 | `vmsumuhs` | Vector Multiply-Sum Unsigned Half Word Saturate | VA | `10000027` |
| 88 | `vmulesb` | Vector Multiply Even Signed Byte | VX | `10000308` |
| 89 | `vmulesh` | Vector Multiply Even Signed Half Word | VX | `10000348` |
| 90 | `vmuleub` | Vector Multiply Even Unsigned Byte | VX | `10000208` |
| 91 | `vmuleuh` | Vector Multiply Even Unsigned Half Word | VX | `10000248` |
| 92 | `vmulosb` | Vector Multiply Odd Signed Byte | VX | `10000108` |
| 93 | `vmulosh` | Vector Multiply Odd Signed Half Word | VX | `10000148` |
| 94 | `vmuloub` | Vector Multiply Odd Unsigned Byte | VX | `10000008` |
| 95 | `vmulouh` | Vector Multiply Odd Unsigned Half Word | VX | `10000048` |
| 96 | `vnmsubfp` | Vector Negative Multiply-Subtract Floating Point | VA | `1000002F` |
| 97 | `vnmsubfp128` | Vector128 Negative Multiply-Subtract Floating Point | VX128 | `14000150` |
| 98 | `vnor` | Vector Logical NOR | VX | `10000504` |
| 99 | `vnor128` | Vector128 Logical NOR | VX128 | `14000290` |
| 100 | `vor` | Vector Logical OR | VX | `10000484` |
| 101 | `vor128` | Vector128 Logical OR | VX128 | `140002D0` |
| 102 | `vperm` | Vector Permute | VA | `1000002B` |
| 103 | `vperm128` | Vector128 Permute | VX128_2 | `14000000` |
| 104 | `vpkpx` | Vector Pack Pixel | VX | `1000030E` |
| 105 | `vpkshss` | Vector Pack Signed Half Word Signed Saturate | VX | `1000018E` |
| 106 | `vpkshss128` | Vector128 Pack Signed Half Word Signed Saturate | VX128 | `14000200` |
| 107 | `vpkshus` | Vector Pack Signed Half Word Unsigned Saturate | VX | `1000010E` |
| 108 | `vpkshus128` | Vector128 Pack Signed Half Word Unsigned Saturate | VX128 | `14000240` |
| 109 | `vpkswss` | Vector Pack Signed Word Signed Saturate | VX | `100001CE` |
| 110 | `vpkswss128` | Vector128 Pack Signed Word Signed Saturate | VX128 | `14000280` |
| 111 | `vpkswus` | Vector Pack Signed Word Unsigned Saturate | VX | `1000014E` |
| 112 | `vpkswus128` | Vector128 Pack Signed Word Unsigned Saturate | VX128 | `140002C0` |
| 113 | `vpkuhum` | Vector Pack Unsigned Half Word Unsigned Modulo | VX | `1000000E` |
| 114 | `vpkuhum128` | Vector128 Pack Unsigned Half Word Unsigned Modulo | VX128 | `14000300` |
| 115 | `vpkuhus` | Vector Pack Unsigned Half Word Unsigned Saturate | VX | `1000008E` |
| 116 | `vpkuhus128` | Vector128 Pack Unsigned Half Word Unsigned Saturate | VX128 | `14000340` |
| 117 | `vpkuwum` | Vector Pack Unsigned Word Unsigned Modulo | VX | `1000004E` |
| 118 | `vpkuwum128` | Vector128 Pack Unsigned Word Unsigned Modulo | VX128 | `14000380` |
| 119 | `vpkuwus` | Vector Pack Unsigned Word Unsigned Saturate | VX | `100000CE` |
| 120 | `vpkuwus128` | Vector128 Pack Unsigned Word Unsigned Saturate | VX128 | `140003C0` |
| 121 | `vrefp` | Vector Reciprocal Estimate Floating Point | VX | `1000010A` |
| 122 | `vrefp128` | Vector128 Reciprocal Estimate Floating Point | VX128_3 | `18000630` |
| 123 | `vrfim` | Vector Round to Floating-Point Integer toward -Infinity | VX | `100002CA` |
| 124 | `vrfim128` | Vector128 Round to Floating-Point Integer toward -Infinity | VX128_3 | `18000330` |
| 125 | `vrfin` | Vector Round to Floating-Point Integer Nearest | VX | `1000020A` |
| 126 | `vrfin128` | Vector128 Round to Floating-Point Integer Nearest | VX128_3 | `18000370` |
| 127 | `vrfip` | Vector Round to Floating-Point Integer toward +Infinity | VX | `1000028A` |
| 128 | `vrfip128` | Vector128 Round to Floating-Point Integer toward +Infinity | VX128_3 | `180003B0` |
| 129 | `vrfiz` | Vector Round to Floating-Point Integer toward Zero | VX | `1000024A` |
| 130 | `vrfiz128` | Vector128 Round to Floating-Point Integer toward Zero | VX128_3 | `180003F0` |
| 131 | `vrlb` | Vector Rotate Left Integer Byte | VX | `10000004` |
| 132 | `vrlh` | Vector Rotate Left Integer Half Word | VX | `10000044` |
| 133 | `vrlw` | Vector Rotate Left Integer Word | VX | `10000084` |
| 134 | `vrlw128` | Vector128 Rotate Left Word | VX128 | `18000050` |
| 135 | `vrsqrtefp` | Vector Reciprocal Square Root Estimate Floating Point | VX | `1000014A` |
| 136 | `vrsqrtefp128` | Vector128 Reciprocal Square Root Estimate Floating Point | VX128_3 | `18000670` |
| 137 | `vsel` | Vector Conditional Select | VA | `1000002A` |
| 138 | `vsel128` | Vector128 Conditional Select | VX128 | `14000350` |
| 139 | `vsl` | Vector Shift Left | VX | `100001C4` |
| 140 | `vslb` | Vector Shift Left Integer Byte | VX | `10000104` |
| 141 | `vsldoi` | Vector Shift Left Double by Octet Immediate | VA | `1000002C` |
| 142 | `vsldoi128` | Vector128 Shift Left Double by Octet Immediate | VX128_5 | `10000010` |
| 143 | `vslh` | Vector Shift Left Integer Half Word | VX | `10000144` |
| 144 | `vslo` | Vector Shift Left by Octet | VX | `1000040C` |
| 145 | `vslo128` | Vector128 Shift Left Octet | VX128 | `14000390` |
| 146 | `vslw` | Vector Shift Left Integer Word | VX | `10000184` |
| 147 | `vslw128` | Vector128 Shift Left Integer Word | VX128 | `180000D0` |
| 148 | `vspltb` | Vector Splat Byte | VX | `1000020C` |
| 149 | `vsplth` | Vector Splat Half Word | VX | `1000024C` |
| 150 | `vspltisb` | Vector Splat Immediate Signed Byte | VX | `1000030C` |
| 151 | `vspltish` | Vector Splat Immediate Signed Half Word | VX | `1000034C` |
| 152 | `vspltisw` | Vector Splat Immediate Signed Word | VX | `1000038C` |
| 153 | `vspltisw128` | Vector128 Splat Immediate Signed Word | VX128_3 | `18000770` |
| 154 | `vspltw` | Vector Splat Word | VX | `1000028C` |
| 155 | `vspltw128` | Vector128 Splat Word | VX128_3 | `18000730` |
| 156 | `vsr` | Vector Shift Right | VX | `100002C4` |
| 157 | `vsrab` | Vector Shift Right Algebraic Byte | VX | `10000304` |
| 158 | `vsrah` | Vector Shift Right Algebraic Half Word | VX | `10000344` |
| 159 | `vsraw` | Vector Shift Right Algebraic Word | VX | `10000384` |
| 160 | `vsraw128` | Vector128 Shift Right Arithmetic Word | VX128 | `18000150` |
| 161 | `vsrb` | Vector Shift Right Byte | VX | `10000204` |
| 162 | `vsrh` | Vector Shift Right Half Word | VX | `10000244` |
| 163 | `vsro` | Vector Shift Right Octet | VX | `1000044C` |
| 164 | `vsro128` | Vector128 Shift Right Octet | VX128 | `140003D0` |
| 165 | `vsrw` | Vector Shift Right Word | VX | `10000284` |
| 166 | `vsrw128` | Vector128 Shift Right Word | VX128 | `180001D0` |
| 167 | `vsubcuw` | Vector Subtract Carryout Unsigned Word | VX | `10000580` |
| 168 | `vsubfp` | Vector Subtract Floating Point | VX | `1000004A` |
| 169 | `vsubfp128` | Vector128 Subtract Floating Point | VX128 | `14000050` |
| 170 | `vsubsbs` | Vector Subtract Signed Byte Saturate | VX | `10000700` |
| 171 | `vsubshs` | Vector Subtract Signed Half Word Saturate | VX | `10000740` |
| 172 | `vsubsws` | Vector Subtract Signed Word Saturate | VX | `10000780` |
| 173 | `vsububm` | Vector Subtract Unsigned Byte Modulo | VX | `10000400` |
| 174 | `vsububs` | Vector Subtract Unsigned Byte Saturate | VX | `10000600` |
| 175 | `vsubuhm` | Vector Subtract Unsigned Half Word Modulo | VX | `10000440` |
| 176 | `vsubuhs` | Vector Subtract Unsigned Half Word Saturate | VX | `10000640` |
| 177 | `vsubuwm` | Vector Subtract Unsigned Word Modulo | VX | `10000480` |
| 178 | `vsubuws` | Vector Subtract Unsigned Word Saturate | VX | `10000680` |
| 179 | `vsumsws` | Vector Sum Across Signed Word Saturate | VX | `10000788` |
| 180 | `vsum2sws` | Vector Sum Across Partial (1/2) Signed Word Saturate | VX | `10000688` |
| 181 | `vsum4sbs` | Vector Sum Across Partial (1/4) Signed Byte Saturate | VX | `10000708` |
| 182 | `vsum4shs` | Vector Sum Across Partial (1/4) Signed Half Word Saturate | VX | `10000648` |
| 183 | `vsum4ubs` | Vector Sum Across Partial (1/4) Unsigned Byte Saturate | VX | `10000608` |
| 184 | `vupkhpx` | Vector Unpack High Pixel | VX | `1000034E` |
| 185 | `vupkhsb` | Vector Unpack High Signed Byte | VX | `1000020E` |
| 186 | `vupkhsb128` | Vector128 Unpack High Signed Byte | VX128 | `18000380` |
| 187 | `vupkhsh` | Vector Unpack High Signed Half Word | VX | `1000024E` |
| 188 | `vupklpx` | Vector Unpack Low Pixel | VX | `100003CE` |
| 189 | `vupklsb` | Vector Unpack Low Signed Byte | VX | `1000028E` |
| 190 | `vupklsb128` | Vector128 Unpack Low Signed Byte | VX128 | `180003C0` |
| 191 | `vupklsh` | Vector Unpack Low Signed Half Word | VX | `100002CE` |
| 192 | `vxor` | Vector Logical XOR | VX | `100004C4` |
| 193 | `vxor128` | Vector128 Logical XOR | VX128 | `14000310` |
| 194 | `vmulfp128` | Vector128 Multiply Floating-Point | VX128 | `14000090` |
| 195 | `vmaddcfp128` | Vector128 Multiply Add Floating Point | VX128 | `14000110` |
| 196 | `vmsum3fp128` | Vector128 Multiply Sum 3-way Floating Point | VX128 | `14000190` |
| 197 | `vmsum4fp128` | Vector128 Multiply Sum 4-way Floating-Point | VX128 | `140001D0` |
| 198 | `vpermwi128` | Vector128 Permutate Word Immediate | VX128_P | `18000210` |
| 199 | `vcfpsxws128` | Vector128 Convert From Floating-Point to Signed Fixed-Point Word Saturate | VX128_3 | `18000230` |
| 200 | `vcfpuxws128` | Vector128 Convert From Floating-Point to Unsigned Fixed-Point Word Saturate | VX128_3 | `18000270` |
| 201 | `vcsxwfp128` | Vector128 Convert From Signed Fixed-Point Word to Floating-Point | VX128_3 | `180002B0` |
| 202 | `vcuxwfp128` | Vector128 Convert From Unsigned Fixed-Point Word to Floating-Point | VX128_3 | `180002F0` |
| 203 | `vpkd3d128` | Vector128 Pack D3Dtype, Rotate Left Immediate and Mask Insert | VX128_4 | `18000610` |
| 204 | `vrlimi128` | Vector128 Rotate Left Immediate and Mask Insert | VX128_4 | `18000710` |
| 205 | `vupkd3d128` | Vector128 Unpack D3Dtype | VX128_3 | `180007F0` |

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*Generated from `tools/ppc-instructions.xml` — 455 instructions across 6 categories.*