test_vsrh_1:
  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
  vsrh v3, v3, v4
  blr
  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]

test_vsrh_2:
  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
  #_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
  vsrh v3, v3, v4
  blr
  #_ REGISTER_OUT v3 [7FFF7FFF, 7FFF7FFF, 7FFF7FFF, 7FFF7FFF]
  #_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]

test_vsrh_3:
  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
  #_ REGISTER_IN v4 [000F000F, 000F000F, 000F000F, 000F000F]
  vsrh v3, v3, v4
  blr
  #_ REGISTER_OUT v3 [00010001, 00010001, 00010001, 00010001]
  #_ REGISTER_OUT v4 [000F000F, 000F000F, 000F000F, 000F000F]

test_vsrh_4:
  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
  #_ REGISTER_IN v4 [00100010, 00100010, 00100010, 00100010]
  vsrh v3, v3, v4
  blr
  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
  #_ REGISTER_OUT v4 [00100010, 00100010, 00100010, 00100010]

test_vsrh_5:
  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
  #_ REGISTER_IN v4 [00090009, 00090009, 00090009, 00090009]
  vsrh v3, v3, v4
  blr
  #_ REGISTER_OUT v3 [007F007F, 007F007F, 007F007F, 007F007F]
  #_ REGISTER_OUT v4 [00090009, 00090009, 00090009, 00090009]

test_vsrh_6:
  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
  #_ REGISTER_IN v4 [00110011, 00110011, 00110011, 00110011]
  vsrh v3, v3, v4
  blr
  #_ REGISTER_OUT v3 [7FFF7FFF, 7FFF7FFF, 7FFF7FFF, 7FFF7FFF]
  #_ REGISTER_OUT v4 [00110011, 00110011, 00110011, 00110011]

test_vsrh_7:
  #_ REGISTER_IN v3 [12345678, 87654321, 11223344, 55667788]
  #_ REGISTER_IN v4 [000D000D, 000D000D, 000D000D, 000D000D]
  vsrh v5, v3, v4
  blr
  #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788]
  #_ REGISTER_OUT v4 [000D000D, 000D000D, 000D000D, 000D000D]
  #_ REGISTER_OUT v5 [00000002, 00040002, 00000001, 00020003]