test_vminfp_1_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_2_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00000000, FFFF0000, 00000000, FFFF0000] test_vminfp_3_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_4_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_5_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00000000, 00000000, 8899AABB, CCDDEEFF] test_vminfp_6_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00000000, 00000000, FF0000FF, FFFF00FF] test_vminfp_7_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_8_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_9_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_10_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_11_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00000000, 87654321, 00000000, 00000000] test_vminfp_12_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_13_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [00000000, C1200000, 00000000, C1700000] test_vminfp_14_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7FC00203, 00000000, 7FC00A0B, 00000000] test_vminfp_15_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80000000, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vminfp_16_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminfp_17_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 00000000, C1A00000, 00000000] test_vminfp_18_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00000000] test_vminfp_19_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00000000, 00000000] test_vminfp_20_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminfp_21_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000000, 00000000] test_vminfp_22_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, 00000000, FFFCFF7D, 00000000] test_vminfp_23_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, 00000000, FFFFFFFF, 00000000] test_vminfp_24_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, 00000000, FFFEFF7F, 00000000] test_vminfp_25_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_26_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_27_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00000000, FFFF0000, 00000000, FFFF0000] test_vminfp_28_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_29_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_30_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00000000, 00000000, 8899AABB, CCDDEEFF] test_vminfp_31_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00000000, 00000000, FF0000FF, FFFF00FF] test_vminfp_32_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_33_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_34_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_35_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_36_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00000000, 87654321, 00000000, 00000000] test_vminfp_37_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_38_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [00000000, C1200000, 00000000, C1700000] test_vminfp_39_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7FC00203, 00000000, 7FC00A0B, 00000000] test_vminfp_40_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80000000, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vminfp_41_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminfp_42_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 00000000, C1A00000, 00000000] test_vminfp_43_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00000000] test_vminfp_44_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00000000, 00000000] test_vminfp_45_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminfp_46_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000000, 00000000] test_vminfp_47_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, 00000000, FFFCFF7D, 00000000] test_vminfp_48_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, 00000000, FFFFFFFF, 00000000] test_vminfp_49_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, 00000000, FFFEFF7F, 00000000] test_vminfp_50_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_51_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, FFFF0000, 00000000, FFFF0000] test_vminfp_52_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000000, FFFF0000, 00000000, FFFF0000] test_vminfp_53_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000000, FFFF0000, 00000000, FFFF0000] test_vminfp_54_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00000000, FFFF0000, 00000000, FFFF0000] test_vminfp_55_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00000000, FFFF0000, 8899AABB, FFFF0000] test_vminfp_56_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00000000, FFFF0000, FF0000FF, FFFF0000] test_vminfp_57_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00000000, FFFF0000, 00000000, FFFF0000] test_vminfp_58_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00000000, FFFF0000, 00000000, FFFF0000] test_vminfp_59_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00000000, FFFF0000, 00000000, FFFF0000] test_vminfp_60_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00000000, FFFF0000, 00000000, FFFF0000] test_vminfp_61_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00000000, FFFF0000, 00000000, FFFF0000] test_vminfp_62_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [00000000, FFFF0000, 00000000, FFFF0000] test_vminfp_63_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [00000000, FFFF0000, 00000000, FFFF0000] test_vminfp_64_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7FC00203, FFFF0000, 7FC00A0B, FFFF0000] test_vminfp_65_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80000000, FFFF0000, 7FFFFFFF, FFFF0000] test_vminfp_66_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, FFFF0000, BF8CCCCD, FFFF0000] test_vminfp_67_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, FFFF0000, C1A00000, FFFF0000] test_vminfp_68_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, FFFF0000, CDCDCDCD, FFFF0000] test_vminfp_69_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FFFF0000, 00000000, FFFF0000] test_vminfp_70_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FFFF0000, FEFEFEFE, FFFF0000] test_vminfp_71_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFF0000, 00000000, FFFF0000] test_vminfp_72_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, FFFF0000, FFFCFF7D, FFFF0000] test_vminfp_73_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, FFFF0000, FFFFFFFF, FFFF0000] test_vminfp_74_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, FFFF0000, FFFEFF7F, FFFF0000] test_vminfp_75_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFF0000, FFFFFFFF, FFFF0000] test_vminfp_76_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_77_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_78_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00000000, FFFF0000, 00000000, FFFF0000] test_vminfp_79_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_80_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00000000, 04050607, 8899AABB, CCDDEEFF] test_vminfp_81_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00000000, 00000000, FF0000FF, FFFF00FF] test_vminfp_82_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00000000, 04040404, 04040404, 04040404] test_vminfp_83_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00000000, 04050607, 07070707, 07070707] test_vminfp_84_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00000000, 04050607, 08080808, 08080808] test_vminfp_85_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00000000, 04050607, 08090A0B, 0C0D0E0F] test_vminfp_86_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00000000, 87654321, 08090A0B, 0C0D0E0F] test_vminfp_87_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [00000000, 04050607, 08090A0B, 0C0D0E0F] test_vminfp_88_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [00000000, C1200000, 08090A0B, C1700000] test_vminfp_89_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7FC00203, 04050607, 7FC00A0B, 0C0D0E0F] test_vminfp_90_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80000000, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vminfp_91_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminfp_92_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 04050607, C1A00000, 0C0D0E0F] test_vminfp_93_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminfp_94_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00000000, 04050607] test_vminfp_95_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminfp_96_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000000, 00000000] test_vminfp_97_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, 00000000, FFFCFF7D, 00000000] test_vminfp_98_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, 04050607, FFFFFFFF, 00000000] test_vminfp_99_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, 00000000, FFFEFF7F, 00000000] test_vminfp_100_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_101_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_102_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_103_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00000000, FFFF0000, 00000000, FFFF0000] test_vminfp_104_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_105_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00000000, 00000000, 8899AABB, CCDDEEFF] test_vminfp_106_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00000000, 00000000, FF0000FF, FFFF00FF] test_vminfp_107_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_108_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_109_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_110_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_111_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00000000, 87654321, 00000000, 00000000] test_vminfp_112_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_113_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [00000000, C1200000, 00000000, C1700000] test_vminfp_114_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7FC00203, 00000000, 7FC00A0B, 00000000] test_vminfp_115_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80000000, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vminfp_116_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminfp_117_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 00000000, C1A00000, 00000000] test_vminfp_118_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00000000] test_vminfp_119_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00000000, 00000000] test_vminfp_120_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminfp_121_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000000, 00000000] test_vminfp_122_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, 00000000, FFFCFF7D, 00000000] test_vminfp_123_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, 00000000, FFFFFFFF, 00000000] test_vminfp_124_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, 00000000, FFFEFF7F, 00000000] test_vminfp_125_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_126_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 8899AABB, CCDDEEFF] test_vminfp_127_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000000, 00000000, 8899AABB, CCDDEEFF] test_vminfp_128_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00000000, FFFF0000, 8899AABB, FFFF0000] test_vminfp_129_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000000, 04050607, 8899AABB, CCDDEEFF] test_vminfp_130_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00000000, 00000000, 8899AABB, CCDDEEFF] test_vminfp_131_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00000000, 00000000, FF0000FF, FFFF00FF] test_vminfp_132_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00000000, 04040404, 8899AABB, CCDDEEFF] test_vminfp_133_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00000000, 07070707, 8899AABB, CCDDEEFF] test_vminfp_134_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00000000, 08080808, 8899AABB, CCDDEEFF] test_vminfp_135_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00000000, 12121212, 8899AABB, CCDDEEFF] test_vminfp_136_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00000000, 87654321, 8899AABB, CCDDEEFF] test_vminfp_137_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [00000000, 3FC00000, 8899AABB, CCDDEEFF] test_vminfp_138_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [00000000, C1200000, 8899AABB, CCDDEEFF] test_vminfp_139_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7FC00203, 04050607, 7FC00A0B, CCDDEEFF] test_vminfp_140_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80000000, 808F0000, 7FFFFFFF, CCDDEEFF] test_vminfp_141_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, CCDDEEFF] test_vminfp_142_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, CCDDEEFF] test_vminfp_143_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CCDDEEFF] test_vminfp_144_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 8899AABB, CCDDEEFF] test_vminfp_145_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminfp_146_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 8899AABB, CCDDEEFF] test_vminfp_147_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, 00000000, FFFCFF7D, CCDDEEFF] test_vminfp_148_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, 44556677, FFFFFFFF, CCDDEEFF] test_vminfp_149_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, 00000000, FFFEFF7F, CCDDEEFF] test_vminfp_150_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_151_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, FF0000FF, FFFF00FF] test_vminfp_152_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000000, 00000000, FF0000FF, FFFF00FF] test_vminfp_153_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00000000, FFFF0000, FF0000FF, FFFF00FF] test_vminfp_154_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000000, 00000000, FF0000FF, FFFF00FF] test_vminfp_155_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00000000, 00000000, FF0000FF, FFFF00FF] test_vminfp_156_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00000000, 00000000, FF0000FF, FFFF00FF] test_vminfp_157_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00FFFF00, 00000000, FF0000FF, FFFF00FF] test_vminfp_158_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00FFFF00, 00000000, FF0000FF, FFFF00FF] test_vminfp_159_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00FFFF00, 00000000, FF0000FF, FFFF00FF] test_vminfp_160_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00FFFF00, 00000000, FF0000FF, FFFF00FF] test_vminfp_161_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00FFFF00, 87654321, FF0000FF, FFFF00FF] test_vminfp_162_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [00FFFF00, 00000000, FF0000FF, FFFF00FF] test_vminfp_163_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [00FFFF00, C1200000, FF0000FF, FFFF00FF] test_vminfp_164_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7FC00203, 00000000, 7FC00A0B, FFFF00FF] test_vminfp_165_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80000000, 808F0000, 7FFFFFFF, FFFF00FF] test_vminfp_166_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, FF0000FF, FFFF00FF] test_vminfp_167_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 00000000, FF0000FF, FFFF00FF] test_vminfp_168_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, FF0000FF, FFFF00FF] test_vminfp_169_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, FF0000FF, FFFF00FF] test_vminfp_170_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FF0000FF, FFFF00FF] test_vminfp_171_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, FF0000FF, FFFF00FF] test_vminfp_172_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, 00000000, FFFCFF7D, FFFF00FF] test_vminfp_173_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, 00000000, FFFFFFFF, FFFF00FF] test_vminfp_174_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, 00000000, FFFEFF7F, FFFF00FF] test_vminfp_175_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFF00FF] test_vminfp_176_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_177_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_178_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00000000, FFFF0000, 00000000, FFFF0000] test_vminfp_179_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000000, 04040404, 04040404, 04040404] test_vminfp_180_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_181_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00000000, 04040404, 8899AABB, CCDDEEFF] test_vminfp_182_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00FFFF00, 00000000, FF0000FF, FFFF00FF] test_vminfp_183_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vminfp_184_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vminfp_185_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vminfp_186_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [04040404, 87654321, 04040404, 04040404] test_vminfp_187_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vminfp_188_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [04040404, C1200000, 04040404, C1700000] test_vminfp_189_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7FC00203, 04040404, 7FC00A0B, 04040404] test_vminfp_190_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80000000, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vminfp_191_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminfp_192_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 04040404, C1A00000, 04040404] test_vminfp_193_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminfp_194_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00000000, 04040404] test_vminfp_195_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminfp_196_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000000, 00000000] test_vminfp_197_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, 00000000, FFFCFF7D, 00000000] test_vminfp_198_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, 04040404, FFFFFFFF, 00000000] test_vminfp_199_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, 00000000, FFFEFF7F, 00000000] test_vminfp_200_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_201_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_202_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_203_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00000000, FFFF0000, 00000000, FFFF0000] test_vminfp_204_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000000, 04050607, 07070707, 07070707] test_vminfp_205_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_206_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00000000, 07070707, 8899AABB, CCDDEEFF] test_vminfp_207_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00FFFF00, 00000000, FF0000FF, FFFF00FF] test_vminfp_208_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vminfp_209_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vminfp_210_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vminfp_211_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [07070707, 87654321, 07070707, 07070707] test_vminfp_212_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vminfp_213_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [07070707, C1200000, 07070707, C1700000] test_vminfp_214_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7FC00203, 04050607, 7FC00A0B, 07070707] test_vminfp_215_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80000000, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vminfp_216_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminfp_217_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 07070707, C1A00000, 07070707] test_vminfp_218_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminfp_219_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00000000, 04050607] test_vminfp_220_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminfp_221_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000000, 00000000] test_vminfp_222_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, 00000000, FFFCFF7D, 00000000] test_vminfp_223_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, 07070707, FFFFFFFF, 00000000] test_vminfp_224_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, 00000000, FFFEFF7F, 00000000] test_vminfp_225_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_226_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_227_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_228_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00000000, FFFF0000, 00000000, FFFF0000] test_vminfp_229_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000000, 04050607, 08080808, 08080808] test_vminfp_230_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_231_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00000000, 08080808, 8899AABB, CCDDEEFF] test_vminfp_232_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00FFFF00, 00000000, FF0000FF, FFFF00FF] test_vminfp_233_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vminfp_234_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vminfp_235_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vminfp_236_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [08080808, 87654321, 08080808, 08080808] test_vminfp_237_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vminfp_238_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [08080808, C1200000, 08080808, C1700000] test_vminfp_239_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7FC00203, 04050607, 7FC00A0B, 08080808] test_vminfp_240_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80000000, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vminfp_241_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminfp_242_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 08080808, C1A00000, 08080808] test_vminfp_243_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminfp_244_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00000000, 04050607] test_vminfp_245_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminfp_246_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000000, 00000000] test_vminfp_247_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, 00000000, FFFCFF7D, 00000000] test_vminfp_248_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, 08080808, FFFFFFFF, 00000000] test_vminfp_249_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, 00000000, FFFEFF7F, 00000000] test_vminfp_250_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_251_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_252_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_253_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00000000, FFFF0000, 00000000, FFFF0000] test_vminfp_254_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000000, 04050607, 08090A0B, 0C0D0E0F] test_vminfp_255_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_256_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00000000, 12121212, 8899AABB, CCDDEEFF] test_vminfp_257_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00FFFF00, 00000000, FF0000FF, FFFF00FF] test_vminfp_258_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vminfp_259_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vminfp_260_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vminfp_261_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [12121212, 87654321, 11223344, 12121212] test_vminfp_262_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212] test_vminfp_263_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [12121212, C1200000, 12121212, C1700000] test_vminfp_264_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7FC00203, 04050607, 7FC00A0B, 0C0D0E0F] test_vminfp_265_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80000000, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vminfp_266_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminfp_267_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 12121212, C1A00000, 12121212] test_vminfp_268_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminfp_269_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00000000, 04050607] test_vminfp_270_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminfp_271_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000000, 00000000] test_vminfp_272_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, 00000000, FFFCFF7D, 00000000] test_vminfp_273_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, 12121212, FFFFFFFF, 00000000] test_vminfp_274_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, 00000000, FFFEFF7F, 00000000] test_vminfp_275_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_276_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 87654321, 00000000, 00000000] test_vminfp_277_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000000, 87654321, 00000000, 00000000] test_vminfp_278_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00000000, FFFF0000, 00000000, FFFF0000] test_vminfp_279_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000000, 87654321, 08090A0B, 0C0D0E0F] test_vminfp_280_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00000000, 87654321, 00000000, 00000000] test_vminfp_281_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00000000, 87654321, 8899AABB, CCDDEEFF] test_vminfp_282_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00FFFF00, 87654321, FF0000FF, FFFF00FF] test_vminfp_283_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [04040404, 87654321, 04040404, 04040404] test_vminfp_284_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [07070707, 87654321, 07070707, 07070707] test_vminfp_285_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [08080808, 87654321, 08080808, 08080808] test_vminfp_286_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [12121212, 87654321, 11223344, 12121212] test_vminfp_287_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 3FF33333] test_vminfp_288_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [12345678, C1200000, 11223344, C1700000] test_vminfp_289_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7FC00203, 87654321, 7FC00A0B, 0C0D0E0F] test_vminfp_290_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80000000, 87654321, 7FFFFFFF, 8FFFFFFF] test_vminfp_291_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminfp_292_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 87654321, C1A00000, 41F00000] test_vminfp_293_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminfp_294_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00000000, 04050607] test_vminfp_295_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminfp_296_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000000, 00000000] test_vminfp_297_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, 87654321, FFFCFF7D, 00000000] test_vminfp_298_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, 87654321, FFFFFFFF, 00000000] test_vminfp_299_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, 87654321, FFFEFF7F, 00000000] test_vminfp_300_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_301_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_302_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_303_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00000000, FFFF0000, 00000000, FFFF0000] test_vminfp_304_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000000, 04050607, 08090A0B, 0C0D0E0F] test_vminfp_305_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminfp_306_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00000000, 3FC00000, 8899AABB, CCDDEEFF] test_vminfp_307_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00FFFF00, 00000000, FF0000FF, FFFF00FF] test_vminfp_308_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vminfp_309_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vminfp_310_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vminfp_311_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212] test_vminfp_312_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 3FF33333] test_vminfp_313_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [3F800000, C1200000, 3F8CCCCD, C1700000] test_vminfp_314_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7FC00203, 04050607, 7FC00A0B, 0C0D0E0F] test_vminfp_315_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80000000, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vminfp_316_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminfp_317_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 3FC00000, C1A00000, 3FF33333] test_vminfp_318_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminfp_319_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00000000, 04050607] test_vminfp_320_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminfp_321_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000000, 00000000] test_vminfp_322_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, 00000000, FFFCFF7D, 00000000] test_vminfp_323_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, 3FC00000, FFFFFFFF, 00000000] test_vminfp_324_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, 00000000, FFFEFF7F, 00000000] test_vminfp_325_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_326_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, C1200000, 00000000, C1700000] test_vminfp_327_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000000, C1200000, 00000000, C1700000] test_vminfp_328_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00000000, FFFF0000, 00000000, FFFF0000] test_vminfp_329_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000000, C1200000, 08090A0B, C1700000] test_vminfp_330_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00000000, C1200000, 00000000, C1700000] test_vminfp_331_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00000000, C1200000, 8899AABB, CCDDEEFF] test_vminfp_332_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00FFFF00, C1200000, FF0000FF, FFFF00FF] test_vminfp_333_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [04040404, C1200000, 04040404, C1700000] test_vminfp_334_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [07070707, C1200000, 07070707, C1700000] test_vminfp_335_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [08080808, C1200000, 08080808, C1700000] test_vminfp_336_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [12121212, C1200000, 12121212, C1700000] test_vminfp_337_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [12345678, C1200000, 11223344, C1700000] test_vminfp_338_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [3F800000, C1200000, 3F8CCCCD, C1700000] test_vminfp_339_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7FC00203, C1200000, 7FC00A0B, C1700000] test_vminfp_340_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80000000, C1200000, 7FFFFFFF, C1700000] test_vminfp_341_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, C1200000, BF8CCCCD, C1700000] test_vminfp_342_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, C1200000, C1A00000, C1700000] test_vminfp_343_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, C1700000] test_vminfp_344_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00000000, C1700000] test_vminfp_345_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminfp_346_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000000, C1700000] test_vminfp_347_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, C1200000, FFFCFF7D, C1700000] test_vminfp_348_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, C1200000, FFFFFFFF, C1700000] test_vminfp_349_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, C1200000, FFFEFF7F, C1700000] test_vminfp_350_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_351_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [7FC00203, 00000000, 7FC00A0B, 00000000] test_vminfp_352_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [7FC00203, 00000000, 7FC00A0B, 00000000] test_vminfp_353_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [7FC00203, FFFF0000, 7FC00A0B, FFFF0000] test_vminfp_354_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7FC00203, 04050607, 7FC00A0B, 0C0D0E0F] test_vminfp_355_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [7FC00203, 00000000, 7FC00A0B, 00000000] test_vminfp_356_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [7FC00203, 04050607, 7FC00A0B, CCDDEEFF] test_vminfp_357_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [7FC00203, 00000000, 7FC00A0B, FFFF00FF] test_vminfp_358_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [7FC00203, 04040404, 7FC00A0B, 04040404] test_vminfp_359_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [7FC00203, 04050607, 7FC00A0B, 07070707] test_vminfp_360_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [7FC00203, 04050607, 7FC00A0B, 08080808] test_vminfp_361_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [7FC00203, 04050607, 7FC00A0B, 0C0D0E0F] test_vminfp_362_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [7FC00203, 87654321, 7FC00A0B, 0C0D0E0F] test_vminfp_363_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [7FC00203, 04050607, 7FC00A0B, 0C0D0E0F] test_vminfp_364_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [7FC00203, C1200000, 7FC00A0B, C1700000] test_vminfp_365_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [7FC00203, 808F0000, 7FC00A0B, 8FFFFFFF] test_vminfp_366_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [7FC00203, BFC00000, 7FC00A0B, BFF33333] test_vminfp_367_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [7FC00203, 04050607, 7FC00A0B, 0C0D0E0F] test_vminfp_368_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [7FC00203, CDCDCDCD, 7FC00A0B, 04010203] test_vminfp_369_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [7FC00203, FCFDFEFF, 7FC00A0B, 04050607] test_vminfp_370_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [7FC00203, FEFEFEFE, 7FC00A0B, FEFEFEFE] test_vminfp_371_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [7FC00203, FFFEFFFF, 7FC00A0B, 00000000] test_vminfp_372_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [7FC00203, 00000000, 7FC00A0B, 00000000] test_vminfp_373_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [7FC00203, 04050607, 7FC00A0B, 00000000] test_vminfp_374_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [7FC00203, 00000000, 7FC00A0B, 00000000] test_vminfp_375_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [7FC00203, FFFFFFFF, 7FC00A0B, FFFFFFFF] test_vminfp_376_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [80000000, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vminfp_377_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [80000000, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vminfp_378_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [80000000, FFFF0000, 7FFFFFFF, FFFF0000] test_vminfp_379_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [80000000, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vminfp_380_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [80000000, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vminfp_381_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [80000000, 808F0000, 7FFFFFFF, CCDDEEFF] test_vminfp_382_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [80000000, 808F0000, 7FFFFFFF, FFFF00FF] test_vminfp_383_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [80000000, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vminfp_384_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [80000000, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vminfp_385_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [80000000, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vminfp_386_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [80000000, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vminfp_387_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [80000000, 87654321, 7FFFFFFF, 8FFFFFFF] test_vminfp_388_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [80000000, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vminfp_389_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [80000000, C1200000, 7FFFFFFF, C1700000] test_vminfp_390_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7FC00203, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vminfp_391_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, 7FFFFFFF, BFF33333] test_vminfp_392_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vminfp_393_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, 7FFFFFFF, 8FFFFFFF] test_vminfp_394_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 7FFFFFFF, 8FFFFFFF] test_vminfp_395_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, 7FFFFFFF, FEFEFEFE] test_vminfp_396_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 7FFFFFFF, 8FFFFFFF] test_vminfp_397_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vminfp_398_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vminfp_399_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vminfp_400_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, 7FFFFFFF, FFFFFFFF] test_vminfp_401_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminfp_402_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminfp_403_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [BF800000, FFFF0000, BF8CCCCD, FFFF0000] test_vminfp_404_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminfp_405_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminfp_406_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, CCDDEEFF] test_vminfp_407_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [BF800000, BFC00000, FF0000FF, FFFF00FF] test_vminfp_408_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminfp_409_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminfp_410_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminfp_411_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminfp_412_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminfp_413_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminfp_414_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [BF800000, C1200000, BF8CCCCD, C1700000] test_vminfp_415_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7FC00203, BFC00000, 7FC00A0B, BFF33333] test_vminfp_416_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [BF800000, BFC00000, 7FFFFFFF, BFF33333] test_vminfp_417_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, BFC00000, C1A00000, BFF33333] test_vminfp_418_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, BFF33333] test_vminfp_419_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, BF8CCCCD, BFF33333] test_vminfp_420_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminfp_421_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, BF8CCCCD, BFF33333] test_vminfp_422_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, BFC00000, FFFCFF7D, BFF33333] test_vminfp_423_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, BFC00000, FFFFFFFF, BFF33333] test_vminfp_424_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, BFC00000, FFFEFF7F, BFF33333] test_vminfp_425_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_426_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [C1200000, 00000000, C1A00000, 00000000] test_vminfp_427_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [C1200000, 00000000, C1A00000, 00000000] test_vminfp_428_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [C1200000, FFFF0000, C1A00000, FFFF0000] test_vminfp_429_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [C1200000, 04050607, C1A00000, 0C0D0E0F] test_vminfp_430_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [C1200000, 00000000, C1A00000, 00000000] test_vminfp_431_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, CCDDEEFF] test_vminfp_432_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [C1200000, 00000000, FF0000FF, FFFF00FF] test_vminfp_433_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [C1200000, 04040404, C1A00000, 04040404] test_vminfp_434_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [C1200000, 07070707, C1A00000, 07070707] test_vminfp_435_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [C1200000, 08080808, C1A00000, 08080808] test_vminfp_436_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [C1200000, 12121212, C1A00000, 12121212] test_vminfp_437_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [C1200000, 87654321, C1A00000, 41F00000] test_vminfp_438_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [C1200000, 3FC00000, C1A00000, 3FF33333] test_vminfp_439_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [C1200000, C1200000, C1A00000, C1700000] test_vminfp_440_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7FC00203, 04050607, 7FC00A0B, 0C0D0E0F] test_vminfp_441_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [C1200000, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vminfp_442_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [C1200000, BFC00000, C1A00000, BFF33333] test_vminfp_443_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminfp_444_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, C1A00000, 04050607] test_vminfp_445_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminfp_446_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, C1A00000, 00000000] test_vminfp_447_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, 00000000, FFFCFF7D, 00000000] test_vminfp_448_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, 41A00000, FFFFFFFF, 00000000] test_vminfp_449_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, 00000000, FFFEFF7F, 00000000] test_vminfp_450_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_451_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00000000] test_vminfp_452_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00000000] test_vminfp_453_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [CDCDCDCD, FFFF0000, CDCDCDCD, FFFF0000] test_vminfp_454_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminfp_455_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00000000] test_vminfp_456_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CCDDEEFF] test_vminfp_457_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, FF0000FF, FFFF00FF] test_vminfp_458_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminfp_459_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminfp_460_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminfp_461_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminfp_462_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminfp_463_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminfp_464_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, C1700000] test_vminfp_465_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7FC00203, CDCDCDCD, 7FC00A0B, 04010203] test_vminfp_466_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, 7FFFFFFF, 8FFFFFFF] test_vminfp_467_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, BFF33333] test_vminfp_468_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminfp_469_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, CDCDCDCD, 04010203] test_vminfp_470_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminfp_471_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, CDCDCDCD, 00000000] test_vminfp_472_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, CDCDCDCD, FFFCFF7D, 00000000] test_vminfp_473_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, CDCDCDCD, FFFFFFFF, 00000000] test_vminfp_474_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, CDCDCDCD, FFFEFF7F, 00000000] test_vminfp_475_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_476_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00000000, 00000000] test_vminfp_477_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00000000, 00000000] test_vminfp_478_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [F8F9FAFB, FFFF0000, 00000000, FFFF0000] test_vminfp_479_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00000000, 04050607] test_vminfp_480_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00000000, 00000000] test_vminfp_481_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 8899AABB, CCDDEEFF] test_vminfp_482_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, FF0000FF, FFFF00FF] test_vminfp_483_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00000000, 04040404] test_vminfp_484_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00000000, 04050607] test_vminfp_485_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00000000, 04050607] test_vminfp_486_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00000000, 04050607] test_vminfp_487_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00000000, 04050607] test_vminfp_488_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00000000, 04050607] test_vminfp_489_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00000000, C1700000] test_vminfp_490_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7FC00203, FCFDFEFF, 7FC00A0B, 04050607] test_vminfp_491_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 7FFFFFFF, 8FFFFFFF] test_vminfp_492_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, BF8CCCCD, BFF33333] test_vminfp_493_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, C1A00000, 04050607] test_vminfp_494_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, CDCDCDCD, 04010203] test_vminfp_495_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminfp_496_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000000, 00000000] test_vminfp_497_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, FCFDFEFF, FFFCFF7D, 00000000] test_vminfp_498_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, FCFDFEFF, FFFFFFFF, 00000000] test_vminfp_499_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, FCFDFEFF, FFFEFF7F, 00000000] test_vminfp_500_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_501_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminfp_502_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminfp_503_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FEFEFEFE, FFFF0000, FEFEFEFE, FFFF0000] test_vminfp_504_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminfp_505_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminfp_506_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminfp_507_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FF0000FF, FFFF00FF] test_vminfp_508_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminfp_509_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminfp_510_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminfp_511_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminfp_512_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminfp_513_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminfp_514_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminfp_515_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7FC00203, FEFEFEFE, 7FC00A0B, FEFEFEFE] test_vminfp_516_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, 7FFFFFFF, FEFEFEFE] test_vminfp_517_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminfp_518_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminfp_519_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminfp_520_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminfp_521_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, FEFEFEFE, FEFEFEFE] test_vminfp_522_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, FEFEFEFE, FFFCFF7D, FEFEFEFE] test_vminfp_523_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, FEFEFEFE, FFFFFFFF, FEFEFEFE] test_vminfp_524_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, FEFEFEFE, FFFEFF7F, FEFEFEFE] test_vminfp_525_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_526_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000000, 00000000] test_vminfp_527_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000000, 00000000] test_vminfp_528_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000000, FFFF0000] test_vminfp_529_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000000, 00000000] test_vminfp_530_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000000, 00000000] test_vminfp_531_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 8899AABB, CCDDEEFF] test_vminfp_532_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, FF0000FF, FFFF00FF] test_vminfp_533_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000000, 00000000] test_vminfp_534_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000000, 00000000] test_vminfp_535_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000000, 00000000] test_vminfp_536_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000000, 00000000] test_vminfp_537_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000000, 00000000] test_vminfp_538_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000000, 00000000] test_vminfp_539_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000000, C1700000] test_vminfp_540_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 7FC00A0B, 00000000] test_vminfp_541_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 7FFFFFFF, 8FFFFFFF] test_vminfp_542_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, BF8CCCCD, BFF33333] test_vminfp_543_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, C1A00000, 00000000] test_vminfp_544_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, CDCDCDCD, 00000000] test_vminfp_545_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000000, 00000000] test_vminfp_546_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, FEFEFEFE, FEFEFEFE] test_vminfp_547_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, FFFCFF7D, 00000000] test_vminfp_548_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, FFFFFFFF, 00000000] test_vminfp_549_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, FFFEFF7F, 00000000] test_vminfp_550_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_551_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FFFDFF7E, 00000000, FFFCFF7D, 00000000] test_vminfp_552_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FFFDFF7E, 00000000, FFFCFF7D, 00000000] test_vminfp_553_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FFFDFF7E, FFFF0000, FFFCFF7D, FFFF0000] test_vminfp_554_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFDFF7E, 00000000, FFFCFF7D, 00000000] test_vminfp_555_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FFFDFF7E, 00000000, FFFCFF7D, 00000000] test_vminfp_556_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FFFDFF7E, 00000000, FFFCFF7D, CCDDEEFF] test_vminfp_557_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FFFDFF7E, 00000000, FFFCFF7D, FFFF00FF] test_vminfp_558_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FFFDFF7E, 00000000, FFFCFF7D, 00000000] test_vminfp_559_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FFFDFF7E, 00000000, FFFCFF7D, 00000000] test_vminfp_560_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FFFDFF7E, 00000000, FFFCFF7D, 00000000] test_vminfp_561_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FFFDFF7E, 00000000, FFFCFF7D, 00000000] test_vminfp_562_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FFFDFF7E, 87654321, FFFCFF7D, 00000000] test_vminfp_563_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FFFDFF7E, 00000000, FFFCFF7D, 00000000] test_vminfp_564_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FFFDFF7E, C1200000, FFFCFF7D, C1700000] test_vminfp_565_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFDFF7E, 00000000, FFFCFF7D, 00000000] test_vminfp_566_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [FFFDFF7E, 808F0000, FFFCFF7D, 8FFFFFFF] test_vminfp_567_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [FFFDFF7E, BFC00000, FFFCFF7D, BFF33333] test_vminfp_568_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [FFFDFF7E, 00000000, FFFCFF7D, 00000000] test_vminfp_569_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [FFFDFF7E, CDCDCDCD, FFFCFF7D, 00000000] test_vminfp_570_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [FFFDFF7E, FCFDFEFF, FFFCFF7D, 00000000] test_vminfp_571_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FFFDFF7E, FEFEFEFE, FFFCFF7D, FEFEFEFE] test_vminfp_572_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFDFF7E, FFFEFFFF, FFFCFF7D, 00000000] test_vminfp_573_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFDFF7E, 00000000, FFFCFF7D, 00000000] test_vminfp_574_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFDFF7E, 00000000, FFFCFF7D, 00000000] test_vminfp_575_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFDFF7E, FFFFFFFF, FFFCFF7D, FFFFFFFF] test_vminfp_576_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FFFF0101, 00000000, FFFFFFFF, 00000000] test_vminfp_577_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FFFF0101, 00000000, FFFFFFFF, 00000000] test_vminfp_578_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FFFF0101, FFFF0000, FFFFFFFF, FFFF0000] test_vminfp_579_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFF0101, 04050607, FFFFFFFF, 00000000] test_vminfp_580_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FFFF0101, 00000000, FFFFFFFF, 00000000] test_vminfp_581_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FFFF0101, 44556677, FFFFFFFF, CCDDEEFF] test_vminfp_582_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FFFF0101, 00000000, FFFFFFFF, FFFF00FF] test_vminfp_583_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FFFF0101, 04040404, FFFFFFFF, 00000000] test_vminfp_584_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FFFF0101, 07070707, FFFFFFFF, 00000000] test_vminfp_585_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FFFF0101, 08080808, FFFFFFFF, 00000000] test_vminfp_586_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FFFF0101, 12121212, FFFFFFFF, 00000000] test_vminfp_587_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FFFF0101, 87654321, FFFFFFFF, 00000000] test_vminfp_588_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FFFF0101, 3FC00000, FFFFFFFF, 00000000] test_vminfp_589_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FFFF0101, C1200000, FFFFFFFF, C1700000] test_vminfp_590_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFF0101, 04050607, FFFFFFFF, 00000000] test_vminfp_591_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [FFFF0101, 808F0000, FFFFFFFF, 8FFFFFFF] test_vminfp_592_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [FFFF0101, BFC00000, FFFFFFFF, BFF33333] test_vminfp_593_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [FFFF0101, 41A00000, FFFFFFFF, 00000000] test_vminfp_594_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [FFFF0101, CDCDCDCD, FFFFFFFF, 00000000] test_vminfp_595_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [FFFF0101, FCFDFEFF, FFFFFFFF, 00000000] test_vminfp_596_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FFFF0101, FEFEFEFE, FFFFFFFF, FEFEFEFE] test_vminfp_597_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFF0101, FFFEFFFF, FFFFFFFF, 00000000] test_vminfp_598_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFF0101, 00000000, FFFFFFFF, 00000000] test_vminfp_599_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFF0101, 00000000, FFFFFFFF, 00000000] test_vminfp_600_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFF0101, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_601_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FFFFFF80, 00000000, FFFEFF7F, 00000000] test_vminfp_602_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FFFFFF80, 00000000, FFFEFF7F, 00000000] test_vminfp_603_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FFFFFF80, FFFF0000, FFFEFF7F, FFFF0000] test_vminfp_604_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFFFF80, 00000000, FFFEFF7F, 00000000] test_vminfp_605_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FFFFFF80, 00000000, FFFEFF7F, 00000000] test_vminfp_606_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FFFFFF80, 00000000, FFFEFF7F, CCDDEEFF] test_vminfp_607_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FFFFFF80, 00000000, FFFEFF7F, FFFF00FF] test_vminfp_608_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FFFFFF80, 00000000, FFFEFF7F, 00000000] test_vminfp_609_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FFFFFF80, 00000000, FFFEFF7F, 00000000] test_vminfp_610_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FFFFFF80, 00000000, FFFEFF7F, 00000000] test_vminfp_611_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FFFFFF80, 00000000, FFFEFF7F, 00000000] test_vminfp_612_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FFFFFF80, 87654321, FFFEFF7F, 00000000] test_vminfp_613_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FFFFFF80, 00000000, FFFEFF7F, 00000000] test_vminfp_614_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FFFFFF80, C1200000, FFFEFF7F, C1700000] test_vminfp_615_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFFFF80, 00000000, FFFEFF7F, 00000000] test_vminfp_616_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [FFFFFF80, 808F0000, FFFEFF7F, 8FFFFFFF] test_vminfp_617_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [FFFFFF80, BFC00000, FFFEFF7F, BFF33333] test_vminfp_618_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [FFFFFF80, 00000000, FFFEFF7F, 00000000] test_vminfp_619_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [FFFFFF80, CDCDCDCD, FFFEFF7F, 00000000] test_vminfp_620_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [FFFFFF80, FCFDFEFF, FFFEFF7F, 00000000] test_vminfp_621_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FFFFFF80, FEFEFEFE, FFFEFF7F, FEFEFEFE] test_vminfp_622_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFFFF80, FFFEFFFF, FFFEFF7F, 00000000] test_vminfp_623_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFFFF80, 00000000, FFFEFF7F, 00000000] test_vminfp_624_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFFFF80, 00000000, FFFEFF7F, 00000000] test_vminfp_625_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFF80, FFFFFFFF, FFFEFF7F, FFFFFFFF] test_vminfp_626_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_627_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_628_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_629_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_630_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_631_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_632_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_633_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_634_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_635_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_636_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_637_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_638_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_639_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_640_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_641_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_642_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_643_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_644_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_645_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_646_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_647_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_648_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_649_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminfp_650_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminfp v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]