test_vsldoi_1_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vsldoi_2_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vsldoi_3_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vsldoi_4_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 01000000] test_vsldoi_5_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vsldoi_6_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vsldoi_7_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vsldoi_8_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00000000, 00000000, 000000FF, FFFFFF00] test_vsldoi_9_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vsldoi_10_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vsldoi_11_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000001] test_vsldoi_12_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000000, 00000000, 00000102, 03040506] test_vsldoi_13_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vsldoi_14_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vsldoi_15_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 0000000D] test_vsldoi_16_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00000000, 00000000, 00000D00, 0D000D00] test_vsldoi_17_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vsldoi_18_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vsldoi_19_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000011] test_vsldoi_20_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00000000, 00000000, 00001122, 33445566] test_vsldoi_21_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vsldoi_22_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vsldoi_23_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 000000FF] test_vsldoi_24_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00000000, 00000000, 0000FFFF, 000000FF] test_vsldoi_25_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vsldoi_26_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000004] test_vsldoi_27_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000404] test_vsldoi_28_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00000000, 00000000, 00040404, 04040404] test_vsldoi_29_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vsldoi_30_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000007] test_vsldoi_31_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000707] test_vsldoi_32_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00000000, 00000000, 00070707, 07070707] test_vsldoi_33_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vsldoi_34_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000008] test_vsldoi_35_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000808] test_vsldoi_36_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00000000, 00000000, 00080808, 08080808] test_vsldoi_37_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vsldoi_38_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000012] test_vsldoi_39_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00001212] test_vsldoi_40_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00000000, 00000000, 00121212, 12121212] test_vsldoi_41_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vsldoi_42_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000012] test_vsldoi_43_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00001234] test_vsldoi_44_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00000000, 00000000, 00123456, 78876543] test_vsldoi_45_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vsldoi_46_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 0000003F] test_vsldoi_47_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00003F80] test_vsldoi_48_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [00000000, 00000000, 003F8000, 003FC000] test_vsldoi_49_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vsldoi_50_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000041] test_vsldoi_51_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00004120] test_vsldoi_52_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [00000000, 00000000, 00412000, 00C12000] test_vsldoi_53_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vsldoi_54_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 0000007F] test_vsldoi_55_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00007F80] test_vsldoi_56_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000000, 00000000, 007F8002, 03040506] test_vsldoi_57_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vsldoi_58_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000080] test_vsldoi_59_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00008008] test_vsldoi_60_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [00000000, 00000000, 00800810, 10808F00] test_vsldoi_61_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vsldoi_62_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 000000BF] test_vsldoi_63_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 0000BF80] test_vsldoi_64_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [00000000, 00000000, 00BF8000, 00BFC000] test_vsldoi_65_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vsldoi_66_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 000000C1] test_vsldoi_67_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 0000C120] test_vsldoi_68_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [00000000, 00000000, 00C12000, 0041A000] test_vsldoi_69_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vsldoi_70_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 000000CD] test_vsldoi_71_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 0000CDCD] test_vsldoi_72_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [00000000, 00000000, 00CDCDCD, CDCDCDCD] test_vsldoi_73_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vsldoi_74_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 000000F8] test_vsldoi_75_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 0000F8F9] test_vsldoi_76_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [00000000, 00000000, 00F8F9FA, FBFCFDFE] test_vsldoi_77_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vsldoi_78_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 000000FE] test_vsldoi_79_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 0000FEFE] test_vsldoi_80_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [00000000, 00000000, 00FEFEFE, FEFEFEFE] test_vsldoi_81_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vsldoi_82_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 000000FF] test_vsldoi_83_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 0000FFFC] test_vsldoi_84_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [00000000, 00000000, 00FFFCFF, FDFFFEFF] test_vsldoi_85_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vsldoi_86_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 000000FF] test_vsldoi_87_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 0000FFFD] test_vsldoi_88_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [00000000, 00000000, 00FFFDFF, 7E000200] test_vsldoi_89_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vsldoi_90_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 000000FF] test_vsldoi_91_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 0000FFFF] test_vsldoi_92_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00FFFF01, 017070FF] test_vsldoi_93_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vsldoi_94_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 000000FF] test_vsldoi_95_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 0000FFFF] test_vsldoi_96_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [00000000, 00000000, 00FFFFFF, 80000000] test_vsldoi_97_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vsldoi_98_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 000000FF] test_vsldoi_99_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 0000FFFF] test_vsldoi_100_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [00000000, 00000000, 00FFFFFF, FFFFFFFF] test_vsldoi_101_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vsldoi_102_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000100, 00000100, 00000100, 00000100] test_vsldoi_103_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00010000, 00010000, 00010000, 00010000] test_vsldoi_104_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [01000000, 01000000, 01000000, 00000000] test_vsldoi_105_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vsldoi_106_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00000100, 00000100, 00000100, 00000100] test_vsldoi_107_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00010000, 00010000, 00010000, 00010000] test_vsldoi_108_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [01000000, 01000000, 010000FF, FFFFFF00] test_vsldoi_109_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vsldoi_110_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000100, 00000100, 00000100, 00000100] test_vsldoi_111_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010000, 00010000, 00010000, 00010001] test_vsldoi_112_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [01000000, 01000000, 01000102, 03040506] test_vsldoi_113_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vsldoi_114_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00000100, 00000100, 00000100, 00000100] test_vsldoi_115_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00010000, 00010000, 00010000, 0001000D] test_vsldoi_116_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [01000000, 01000000, 01000D00, 0D000D00] test_vsldoi_117_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vsldoi_118_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00000100, 00000100, 00000100, 00000100] test_vsldoi_119_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00010000, 00010000, 00010000, 00010011] test_vsldoi_120_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [01000000, 01000000, 01001122, 33445566] test_vsldoi_121_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vsldoi_122_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00000100, 00000100, 00000100, 00000100] test_vsldoi_123_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00010000, 00010000, 00010000, 000100FF] test_vsldoi_124_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [01000000, 01000000, 0100FFFF, 000000FF] test_vsldoi_125_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vsldoi_126_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00000100, 00000100, 00000100, 00000104] test_vsldoi_127_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00010000, 00010000, 00010000, 00010404] test_vsldoi_128_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [01000000, 01000000, 01040404, 04040404] test_vsldoi_129_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vsldoi_130_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00000100, 00000100, 00000100, 00000107] test_vsldoi_131_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00010000, 00010000, 00010000, 00010707] test_vsldoi_132_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [01000000, 01000000, 01070707, 07070707] test_vsldoi_133_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vsldoi_134_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00000100, 00000100, 00000100, 00000108] test_vsldoi_135_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00010000, 00010000, 00010000, 00010808] test_vsldoi_136_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [01000000, 01000000, 01080808, 08080808] test_vsldoi_137_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vsldoi_138_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00000100, 00000100, 00000100, 00000112] test_vsldoi_139_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00010000, 00010000, 00010000, 00011212] test_vsldoi_140_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [01000000, 01000000, 01121212, 12121212] test_vsldoi_141_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vsldoi_142_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00000100, 00000100, 00000100, 00000112] test_vsldoi_143_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00010000, 00010000, 00010000, 00011234] test_vsldoi_144_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [01000000, 01000000, 01123456, 78876543] test_vsldoi_145_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vsldoi_146_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [00000100, 00000100, 00000100, 0000013F] test_vsldoi_147_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [00010000, 00010000, 00010000, 00013F80] test_vsldoi_148_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [01000000, 01000000, 013F8000, 003FC000] test_vsldoi_149_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vsldoi_150_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [00000100, 00000100, 00000100, 00000141] test_vsldoi_151_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [00010000, 00010000, 00010000, 00014120] test_vsldoi_152_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [01000000, 01000000, 01412000, 00C12000] test_vsldoi_153_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vsldoi_154_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000100, 00000100, 00000100, 0000017F] test_vsldoi_155_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010000, 00010000, 00010000, 00017F80] test_vsldoi_156_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [01000000, 01000000, 017F8002, 03040506] test_vsldoi_157_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vsldoi_158_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [00000100, 00000100, 00000100, 00000180] test_vsldoi_159_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [00010000, 00010000, 00010000, 00018008] test_vsldoi_160_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [01000000, 01000000, 01800810, 10808F00] test_vsldoi_161_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vsldoi_162_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [00000100, 00000100, 00000100, 000001BF] test_vsldoi_163_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [00010000, 00010000, 00010000, 0001BF80] test_vsldoi_164_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [01000000, 01000000, 01BF8000, 00BFC000] test_vsldoi_165_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vsldoi_166_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [00000100, 00000100, 00000100, 000001C1] test_vsldoi_167_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [00010000, 00010000, 00010000, 0001C120] test_vsldoi_168_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [01000000, 01000000, 01C12000, 0041A000] test_vsldoi_169_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vsldoi_170_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [00000100, 00000100, 00000100, 000001CD] test_vsldoi_171_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [00010000, 00010000, 00010000, 0001CDCD] test_vsldoi_172_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [01000000, 01000000, 01CDCDCD, CDCDCDCD] test_vsldoi_173_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vsldoi_174_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [00000100, 00000100, 00000100, 000001F8] test_vsldoi_175_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [00010000, 00010000, 00010000, 0001F8F9] test_vsldoi_176_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [01000000, 01000000, 01F8F9FA, FBFCFDFE] test_vsldoi_177_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vsldoi_178_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [00000100, 00000100, 00000100, 000001FE] test_vsldoi_179_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [00010000, 00010000, 00010000, 0001FEFE] test_vsldoi_180_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [01000000, 01000000, 01FEFEFE, FEFEFEFE] test_vsldoi_181_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vsldoi_182_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [00000100, 00000100, 00000100, 000001FF] test_vsldoi_183_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [00010000, 00010000, 00010000, 0001FFFC] test_vsldoi_184_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [01000000, 01000000, 01FFFCFF, FDFFFEFF] test_vsldoi_185_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vsldoi_186_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [00000100, 00000100, 00000100, 000001FF] test_vsldoi_187_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [00010000, 00010000, 00010000, 0001FFFD] test_vsldoi_188_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [01000000, 01000000, 01FFFDFF, 7E000200] test_vsldoi_189_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vsldoi_190_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [00000100, 00000100, 00000100, 000001FF] test_vsldoi_191_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [00010000, 00010000, 00010000, 0001FFFF] test_vsldoi_192_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [01000000, 01000000, 01FFFF01, 017070FF] test_vsldoi_193_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vsldoi_194_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [00000100, 00000100, 00000100, 000001FF] test_vsldoi_195_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [00010000, 00010000, 00010000, 0001FFFF] test_vsldoi_196_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [01000000, 01000000, 01FFFFFF, 80000000] test_vsldoi_197_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vsldoi_198_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [00000100, 00000100, 00000100, 000001FF] test_vsldoi_199_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [00010000, 00010000, 00010000, 0001FFFF] test_vsldoi_200_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [01000000, 01000000, 01FFFFFF, FFFFFFFF] test_vsldoi_201_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vsldoi_202_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00FFFFFF, FF000000, 000000FF, FF000000] test_vsldoi_203_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FFFFFFFF, 00000000, 0000FFFF, 00000000] test_vsldoi_204_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00FFFF00, 00000000, 00000000] test_vsldoi_205_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vsldoi_206_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00FFFFFF, FF000000, 000000FF, FF000000] test_vsldoi_207_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FFFFFFFF, 00000000, 0000FFFF, 00000000] test_vsldoi_208_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000000, 00FFFF00, 00000000, 01000000] test_vsldoi_209_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vsldoi_210_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00FFFFFF, FF000000, 000000FF, FF000000] test_vsldoi_211_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFFFFFF, 00000000, 0000FFFF, 00000001] test_vsldoi_212_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000000, 00FFFF00, 00000102, 03040506] test_vsldoi_213_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vsldoi_214_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00FFFFFF, FF000000, 000000FF, FF000000] test_vsldoi_215_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FFFFFFFF, 00000000, 0000FFFF, 0000000D] test_vsldoi_216_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00000000, 00FFFF00, 00000D00, 0D000D00] test_vsldoi_217_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vsldoi_218_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00FFFFFF, FF000000, 000000FF, FF000000] test_vsldoi_219_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FFFFFFFF, 00000000, 0000FFFF, 00000011] test_vsldoi_220_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00000000, 00FFFF00, 00001122, 33445566] test_vsldoi_221_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vsldoi_222_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00FFFFFF, FF000000, 000000FF, FF000000] test_vsldoi_223_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FFFFFFFF, 00000000, 0000FFFF, 000000FF] test_vsldoi_224_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00000000, 00FFFF00, 0000FFFF, 000000FF] test_vsldoi_225_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vsldoi_226_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00FFFFFF, FF000000, 000000FF, FF000004] test_vsldoi_227_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FFFFFFFF, 00000000, 0000FFFF, 00000404] test_vsldoi_228_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00000000, 00FFFF00, 00040404, 04040404] test_vsldoi_229_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vsldoi_230_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00FFFFFF, FF000000, 000000FF, FF000007] test_vsldoi_231_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FFFFFFFF, 00000000, 0000FFFF, 00000707] test_vsldoi_232_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00000000, 00FFFF00, 00070707, 07070707] test_vsldoi_233_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vsldoi_234_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00FFFFFF, FF000000, 000000FF, FF000008] test_vsldoi_235_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FFFFFFFF, 00000000, 0000FFFF, 00000808] test_vsldoi_236_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00000000, 00FFFF00, 00080808, 08080808] test_vsldoi_237_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vsldoi_238_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00FFFFFF, FF000000, 000000FF, FF000012] test_vsldoi_239_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FFFFFFFF, 00000000, 0000FFFF, 00001212] test_vsldoi_240_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00000000, 00FFFF00, 00121212, 12121212] test_vsldoi_241_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vsldoi_242_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00FFFFFF, FF000000, 000000FF, FF000012] test_vsldoi_243_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FFFFFFFF, 00000000, 0000FFFF, 00001234] test_vsldoi_244_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00000000, 00FFFF00, 00123456, 78876543] test_vsldoi_245_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vsldoi_246_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [00FFFFFF, FF000000, 000000FF, FF00003F] test_vsldoi_247_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FFFFFFFF, 00000000, 0000FFFF, 00003F80] test_vsldoi_248_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [00000000, 00FFFF00, 003F8000, 003FC000] test_vsldoi_249_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vsldoi_250_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [00FFFFFF, FF000000, 000000FF, FF000041] test_vsldoi_251_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FFFFFFFF, 00000000, 0000FFFF, 00004120] test_vsldoi_252_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [00000000, 00FFFF00, 00412000, 00C12000] test_vsldoi_253_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vsldoi_254_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00FFFFFF, FF000000, 000000FF, FF00007F] test_vsldoi_255_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFFFFFF, 00000000, 0000FFFF, 00007F80] test_vsldoi_256_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000000, 00FFFF00, 007F8002, 03040506] test_vsldoi_257_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vsldoi_258_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [00FFFFFF, FF000000, 000000FF, FF000080] test_vsldoi_259_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, 00000000, 0000FFFF, 00008008] test_vsldoi_260_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [00000000, 00FFFF00, 00800810, 10808F00] test_vsldoi_261_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vsldoi_262_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [00FFFFFF, FF000000, 000000FF, FF0000BF] test_vsldoi_263_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [FFFFFFFF, 00000000, 0000FFFF, 0000BF80] test_vsldoi_264_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [00000000, 00FFFF00, 00BF8000, 00BFC000] test_vsldoi_265_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vsldoi_266_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [00FFFFFF, FF000000, 000000FF, FF0000C1] test_vsldoi_267_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [FFFFFFFF, 00000000, 0000FFFF, 0000C120] test_vsldoi_268_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [00000000, 00FFFF00, 00C12000, 0041A000] test_vsldoi_269_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vsldoi_270_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [00FFFFFF, FF000000, 000000FF, FF0000CD] test_vsldoi_271_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [FFFFFFFF, 00000000, 0000FFFF, 0000CDCD] test_vsldoi_272_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [00000000, 00FFFF00, 00CDCDCD, CDCDCDCD] test_vsldoi_273_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vsldoi_274_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [00FFFFFF, FF000000, 000000FF, FF0000F8] test_vsldoi_275_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [FFFFFFFF, 00000000, 0000FFFF, 0000F8F9] test_vsldoi_276_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [00000000, 00FFFF00, 00F8F9FA, FBFCFDFE] test_vsldoi_277_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vsldoi_278_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [00FFFFFF, FF000000, 000000FF, FF0000FE] test_vsldoi_279_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FFFFFFFF, 00000000, 0000FFFF, 0000FEFE] test_vsldoi_280_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [00000000, 00FFFF00, 00FEFEFE, FEFEFEFE] test_vsldoi_281_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vsldoi_282_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [00FFFFFF, FF000000, 000000FF, FF0000FF] test_vsldoi_283_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFFFFFF, 00000000, 0000FFFF, 0000FFFC] test_vsldoi_284_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [00000000, 00FFFF00, 00FFFCFF, FDFFFEFF] test_vsldoi_285_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vsldoi_286_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [00FFFFFF, FF000000, 000000FF, FF0000FF] test_vsldoi_287_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFFFFFF, 00000000, 0000FFFF, 0000FFFD] test_vsldoi_288_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [00000000, 00FFFF00, 00FFFDFF, 7E000200] test_vsldoi_289_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vsldoi_290_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [00FFFFFF, FF000000, 000000FF, FF0000FF] test_vsldoi_291_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFFFFFF, 00000000, 0000FFFF, 0000FFFF] test_vsldoi_292_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [00000000, 00FFFF00, 00FFFF01, 017070FF] test_vsldoi_293_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vsldoi_294_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [00FFFFFF, FF000000, 000000FF, FF0000FF] test_vsldoi_295_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFFFF, 00000000, 0000FFFF, 0000FFFF] test_vsldoi_296_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [00000000, 00FFFF00, 00FFFFFF, 80000000] test_vsldoi_297_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vsldoi_298_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [00FFFFFF, FF000000, 000000FF, FF0000FF] test_vsldoi_299_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, 00000000, 0000FFFF, 0000FFFF] test_vsldoi_300_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [00000000, 00FFFF00, 00FFFFFF, FFFFFFFF] test_vsldoi_301_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vsldoi_302_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F00] test_vsldoi_303_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [02030405, 06070809, 0A0B0C0D, 0E0F0000] test_vsldoi_304_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [0708090A, 0B0C0D0E, 0F000000, 00000000] test_vsldoi_305_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vsldoi_306_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F00] test_vsldoi_307_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [02030405, 06070809, 0A0B0C0D, 0E0F0000] test_vsldoi_308_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [0708090A, 0B0C0D0E, 0F000000, 01000000] test_vsldoi_309_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vsldoi_310_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F00] test_vsldoi_311_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [02030405, 06070809, 0A0B0C0D, 0E0F0000] test_vsldoi_312_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [0708090A, 0B0C0D0E, 0F0000FF, FFFFFF00] test_vsldoi_313_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vsldoi_314_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F00] test_vsldoi_315_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [02030405, 06070809, 0A0B0C0D, 0E0F000D] test_vsldoi_316_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [0708090A, 0B0C0D0E, 0F000D00, 0D000D00] test_vsldoi_317_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vsldoi_318_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F00] test_vsldoi_319_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [02030405, 06070809, 0A0B0C0D, 0E0F0011] test_vsldoi_320_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [0708090A, 0B0C0D0E, 0F001122, 33445566] test_vsldoi_321_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vsldoi_322_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F00] test_vsldoi_323_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [02030405, 06070809, 0A0B0C0D, 0E0F00FF] test_vsldoi_324_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [0708090A, 0B0C0D0E, 0F00FFFF, 000000FF] test_vsldoi_325_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vsldoi_326_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F04] test_vsldoi_327_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [02030405, 06070809, 0A0B0C0D, 0E0F0404] test_vsldoi_328_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [0708090A, 0B0C0D0E, 0F040404, 04040404] test_vsldoi_329_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vsldoi_330_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F07] test_vsldoi_331_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [02030405, 06070809, 0A0B0C0D, 0E0F0707] test_vsldoi_332_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [0708090A, 0B0C0D0E, 0F070707, 07070707] test_vsldoi_333_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vsldoi_334_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F08] test_vsldoi_335_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [02030405, 06070809, 0A0B0C0D, 0E0F0808] test_vsldoi_336_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [0708090A, 0B0C0D0E, 0F080808, 08080808] test_vsldoi_337_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vsldoi_338_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F12] test_vsldoi_339_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [02030405, 06070809, 0A0B0C0D, 0E0F1212] test_vsldoi_340_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [0708090A, 0B0C0D0E, 0F121212, 12121212] test_vsldoi_341_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vsldoi_342_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F12] test_vsldoi_343_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [02030405, 06070809, 0A0B0C0D, 0E0F1234] test_vsldoi_344_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [0708090A, 0B0C0D0E, 0F123456, 78876543] test_vsldoi_345_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vsldoi_346_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F3F] test_vsldoi_347_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [02030405, 06070809, 0A0B0C0D, 0E0F3F80] test_vsldoi_348_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [0708090A, 0B0C0D0E, 0F3F8000, 003FC000] test_vsldoi_349_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vsldoi_350_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F41] test_vsldoi_351_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [02030405, 06070809, 0A0B0C0D, 0E0F4120] test_vsldoi_352_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [0708090A, 0B0C0D0E, 0F412000, 00C12000] test_vsldoi_353_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vsldoi_354_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F7F] test_vsldoi_355_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [02030405, 06070809, 0A0B0C0D, 0E0F7F80] test_vsldoi_356_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [0708090A, 0B0C0D0E, 0F7F8002, 03040506] test_vsldoi_357_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vsldoi_358_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F80] test_vsldoi_359_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [02030405, 06070809, 0A0B0C0D, 0E0F8008] test_vsldoi_360_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [0708090A, 0B0C0D0E, 0F800810, 10808F00] test_vsldoi_361_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vsldoi_362_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0FBF] test_vsldoi_363_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [02030405, 06070809, 0A0B0C0D, 0E0FBF80] test_vsldoi_364_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [0708090A, 0B0C0D0E, 0FBF8000, 00BFC000] test_vsldoi_365_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vsldoi_366_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0FC1] test_vsldoi_367_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [02030405, 06070809, 0A0B0C0D, 0E0FC120] test_vsldoi_368_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [0708090A, 0B0C0D0E, 0FC12000, 0041A000] test_vsldoi_369_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vsldoi_370_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0FCD] test_vsldoi_371_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [02030405, 06070809, 0A0B0C0D, 0E0FCDCD] test_vsldoi_372_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [0708090A, 0B0C0D0E, 0FCDCDCD, CDCDCDCD] test_vsldoi_373_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vsldoi_374_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0FF8] test_vsldoi_375_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [02030405, 06070809, 0A0B0C0D, 0E0FF8F9] test_vsldoi_376_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [0708090A, 0B0C0D0E, 0FF8F9FA, FBFCFDFE] test_vsldoi_377_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vsldoi_378_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0FFE] test_vsldoi_379_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [02030405, 06070809, 0A0B0C0D, 0E0FFEFE] test_vsldoi_380_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [0708090A, 0B0C0D0E, 0FFEFEFE, FEFEFEFE] test_vsldoi_381_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vsldoi_382_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0FFF] test_vsldoi_383_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [02030405, 06070809, 0A0B0C0D, 0E0FFFFC] test_vsldoi_384_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [0708090A, 0B0C0D0E, 0FFFFCFF, FDFFFEFF] test_vsldoi_385_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vsldoi_386_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0FFF] test_vsldoi_387_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [02030405, 06070809, 0A0B0C0D, 0E0FFFFD] test_vsldoi_388_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [0708090A, 0B0C0D0E, 0FFFFDFF, 7E000200] test_vsldoi_389_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vsldoi_390_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0FFF] test_vsldoi_391_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [02030405, 06070809, 0A0B0C0D, 0E0FFFFF] test_vsldoi_392_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [0708090A, 0B0C0D0E, 0FFFFF01, 017070FF] test_vsldoi_393_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vsldoi_394_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0FFF] test_vsldoi_395_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [02030405, 06070809, 0A0B0C0D, 0E0FFFFF] test_vsldoi_396_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [0708090A, 0B0C0D0E, 0FFFFFFF, 80000000] test_vsldoi_397_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vsldoi_398_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0FFF] test_vsldoi_399_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [02030405, 06070809, 0A0B0C0D, 0E0FFFFF] test_vsldoi_400_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [0708090A, 0B0C0D0E, 0FFFFFFF, FFFFFFFF] test_vsldoi_401_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vsldoi_402_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D000D00, 0D000D00] test_vsldoi_403_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D0000] test_vsldoi_404_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D000000, 00000000] test_vsldoi_405_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vsldoi_406_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D000D00, 0D000D00] test_vsldoi_407_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D0000] test_vsldoi_408_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D000000, 01000000] test_vsldoi_409_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vsldoi_410_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D000D00, 0D000D00] test_vsldoi_411_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D0000] test_vsldoi_412_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D0000FF, FFFFFF00] test_vsldoi_413_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vsldoi_414_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D000D00, 0D000D00] test_vsldoi_415_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D0001] test_vsldoi_416_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D000102, 03040506] test_vsldoi_417_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vsldoi_418_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D000D00, 0D000D00] test_vsldoi_419_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D0011] test_vsldoi_420_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D001122, 33445566] test_vsldoi_421_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vsldoi_422_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D000D00, 0D000D00] test_vsldoi_423_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D00FF] test_vsldoi_424_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D00FFFF, 000000FF] test_vsldoi_425_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vsldoi_426_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D000D00, 0D000D04] test_vsldoi_427_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D0404] test_vsldoi_428_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D040404, 04040404] test_vsldoi_429_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vsldoi_430_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D000D00, 0D000D07] test_vsldoi_431_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D0707] test_vsldoi_432_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D070707, 07070707] test_vsldoi_433_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vsldoi_434_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D000D00, 0D000D08] test_vsldoi_435_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D0808] test_vsldoi_436_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D080808, 08080808] test_vsldoi_437_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vsldoi_438_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D000D00, 0D000D12] test_vsldoi_439_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D1212] test_vsldoi_440_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D121212, 12121212] test_vsldoi_441_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vsldoi_442_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D000D00, 0D000D12] test_vsldoi_443_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D1234] test_vsldoi_444_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D123456, 78876543] test_vsldoi_445_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vsldoi_446_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D000D00, 0D000D3F] test_vsldoi_447_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D3F80] test_vsldoi_448_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D3F8000, 003FC000] test_vsldoi_449_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vsldoi_450_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D000D00, 0D000D41] test_vsldoi_451_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D4120] test_vsldoi_452_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D412000, 00C12000] test_vsldoi_453_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vsldoi_454_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D000D00, 0D000D7F] test_vsldoi_455_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D7F80] test_vsldoi_456_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D7F8002, 03040506] test_vsldoi_457_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vsldoi_458_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D000D00, 0D000D80] test_vsldoi_459_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D8008] test_vsldoi_460_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D800810, 10808F00] test_vsldoi_461_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vsldoi_462_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D000D00, 0D000DBF] test_vsldoi_463_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000DBF80] test_vsldoi_464_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0DBF8000, 00BFC000] test_vsldoi_465_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vsldoi_466_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D000D00, 0D000DC1] test_vsldoi_467_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000DC120] test_vsldoi_468_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0DC12000, 0041A000] test_vsldoi_469_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vsldoi_470_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D000D00, 0D000DCD] test_vsldoi_471_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000DCDCD] test_vsldoi_472_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0DCDCDCD, CDCDCDCD] test_vsldoi_473_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vsldoi_474_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D000D00, 0D000DF8] test_vsldoi_475_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000DF8F9] test_vsldoi_476_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0DF8F9FA, FBFCFDFE] test_vsldoi_477_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vsldoi_478_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D000D00, 0D000DFE] test_vsldoi_479_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000DFEFE] test_vsldoi_480_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0DFEFEFE, FEFEFEFE] test_vsldoi_481_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vsldoi_482_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D000D00, 0D000DFF] test_vsldoi_483_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000DFFFC] test_vsldoi_484_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0DFFFCFF, FDFFFEFF] test_vsldoi_485_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vsldoi_486_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D000D00, 0D000DFF] test_vsldoi_487_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000DFFFD] test_vsldoi_488_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0DFFFDFF, 7E000200] test_vsldoi_489_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vsldoi_490_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D000D00, 0D000DFF] test_vsldoi_491_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000DFFFF] test_vsldoi_492_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0DFFFF01, 017070FF] test_vsldoi_493_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vsldoi_494_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D000D00, 0D000DFF] test_vsldoi_495_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000DFFFF] test_vsldoi_496_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0DFFFFFF, 80000000] test_vsldoi_497_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vsldoi_498_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D000D00, 0D000DFF] test_vsldoi_499_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000DFFFF] test_vsldoi_500_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0DFFFFFF, FFFFFFFF] test_vsldoi_501_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF] test_vsldoi_502_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [11223344, 55667788, 99AABBCC, DDEEFF00] test_vsldoi_503_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [22334455, 66778899, AABBCCDD, EEFF0000] test_vsldoi_504_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [778899AA, BBCCDDEE, FF000000, 00000000] test_vsldoi_505_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF] test_vsldoi_506_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [11223344, 55667788, 99AABBCC, DDEEFF00] test_vsldoi_507_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [22334455, 66778899, AABBCCDD, EEFF0000] test_vsldoi_508_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [778899AA, BBCCDDEE, FF000000, 01000000] test_vsldoi_509_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF] test_vsldoi_510_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [11223344, 55667788, 99AABBCC, DDEEFF00] test_vsldoi_511_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [22334455, 66778899, AABBCCDD, EEFF0000] test_vsldoi_512_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [778899AA, BBCCDDEE, FF0000FF, FFFFFF00] test_vsldoi_513_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF] test_vsldoi_514_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [11223344, 55667788, 99AABBCC, DDEEFF00] test_vsldoi_515_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [22334455, 66778899, AABBCCDD, EEFF0001] test_vsldoi_516_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [778899AA, BBCCDDEE, FF000102, 03040506] test_vsldoi_517_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF] test_vsldoi_518_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [11223344, 55667788, 99AABBCC, DDEEFF00] test_vsldoi_519_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [22334455, 66778899, AABBCCDD, EEFF000D] test_vsldoi_520_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [778899AA, BBCCDDEE, FF000D00, 0D000D00] test_vsldoi_521_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF] test_vsldoi_522_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [11223344, 55667788, 99AABBCC, DDEEFF00] test_vsldoi_523_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [22334455, 66778899, AABBCCDD, EEFF00FF] test_vsldoi_524_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [778899AA, BBCCDDEE, FF00FFFF, 000000FF] test_vsldoi_525_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF] test_vsldoi_526_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [11223344, 55667788, 99AABBCC, DDEEFF04] test_vsldoi_527_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [22334455, 66778899, AABBCCDD, EEFF0404] test_vsldoi_528_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [778899AA, BBCCDDEE, FF040404, 04040404] test_vsldoi_529_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF] test_vsldoi_530_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [11223344, 55667788, 99AABBCC, DDEEFF07] test_vsldoi_531_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [22334455, 66778899, AABBCCDD, EEFF0707] test_vsldoi_532_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [778899AA, BBCCDDEE, FF070707, 07070707] test_vsldoi_533_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF] test_vsldoi_534_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [11223344, 55667788, 99AABBCC, DDEEFF08] test_vsldoi_535_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [22334455, 66778899, AABBCCDD, EEFF0808] test_vsldoi_536_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [778899AA, BBCCDDEE, FF080808, 08080808] test_vsldoi_537_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF] test_vsldoi_538_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [11223344, 55667788, 99AABBCC, DDEEFF12] test_vsldoi_539_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [22334455, 66778899, AABBCCDD, EEFF1212] test_vsldoi_540_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [778899AA, BBCCDDEE, FF121212, 12121212] test_vsldoi_541_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF] test_vsldoi_542_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [11223344, 55667788, 99AABBCC, DDEEFF12] test_vsldoi_543_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [22334455, 66778899, AABBCCDD, EEFF1234] test_vsldoi_544_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [778899AA, BBCCDDEE, FF123456, 78876543] test_vsldoi_545_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF] test_vsldoi_546_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [11223344, 55667788, 99AABBCC, DDEEFF3F] test_vsldoi_547_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [22334455, 66778899, AABBCCDD, EEFF3F80] test_vsldoi_548_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [778899AA, BBCCDDEE, FF3F8000, 003FC000] test_vsldoi_549_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF] test_vsldoi_550_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [11223344, 55667788, 99AABBCC, DDEEFF41] test_vsldoi_551_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [22334455, 66778899, AABBCCDD, EEFF4120] test_vsldoi_552_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [778899AA, BBCCDDEE, FF412000, 00C12000] test_vsldoi_553_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF] test_vsldoi_554_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [11223344, 55667788, 99AABBCC, DDEEFF7F] test_vsldoi_555_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [22334455, 66778899, AABBCCDD, EEFF7F80] test_vsldoi_556_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [778899AA, BBCCDDEE, FF7F8002, 03040506] test_vsldoi_557_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF] test_vsldoi_558_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [11223344, 55667788, 99AABBCC, DDEEFF80] test_vsldoi_559_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [22334455, 66778899, AABBCCDD, EEFF8008] test_vsldoi_560_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [778899AA, BBCCDDEE, FF800810, 10808F00] test_vsldoi_561_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF] test_vsldoi_562_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [11223344, 55667788, 99AABBCC, DDEEFFBF] test_vsldoi_563_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [22334455, 66778899, AABBCCDD, EEFFBF80] test_vsldoi_564_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [778899AA, BBCCDDEE, FFBF8000, 00BFC000] test_vsldoi_565_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF] test_vsldoi_566_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [11223344, 55667788, 99AABBCC, DDEEFFC1] test_vsldoi_567_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [22334455, 66778899, AABBCCDD, EEFFC120] test_vsldoi_568_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [778899AA, BBCCDDEE, FFC12000, 0041A000] test_vsldoi_569_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF] test_vsldoi_570_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [11223344, 55667788, 99AABBCC, DDEEFFCD] test_vsldoi_571_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [22334455, 66778899, AABBCCDD, EEFFCDCD] test_vsldoi_572_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [778899AA, BBCCDDEE, FFCDCDCD, CDCDCDCD] test_vsldoi_573_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF] test_vsldoi_574_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [11223344, 55667788, 99AABBCC, DDEEFFF8] test_vsldoi_575_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [22334455, 66778899, AABBCCDD, EEFFF8F9] test_vsldoi_576_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [778899AA, BBCCDDEE, FFF8F9FA, FBFCFDFE] test_vsldoi_577_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF] test_vsldoi_578_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [11223344, 55667788, 99AABBCC, DDEEFFFE] test_vsldoi_579_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [22334455, 66778899, AABBCCDD, EEFFFEFE] test_vsldoi_580_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [778899AA, BBCCDDEE, FFFEFEFE, FEFEFEFE] test_vsldoi_581_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF] test_vsldoi_582_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [11223344, 55667788, 99AABBCC, DDEEFFFF] test_vsldoi_583_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [22334455, 66778899, AABBCCDD, EEFFFFFC] test_vsldoi_584_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [778899AA, BBCCDDEE, FFFFFCFF, FDFFFEFF] test_vsldoi_585_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF] test_vsldoi_586_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [11223344, 55667788, 99AABBCC, DDEEFFFF] test_vsldoi_587_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [22334455, 66778899, AABBCCDD, EEFFFFFD] test_vsldoi_588_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [778899AA, BBCCDDEE, FFFFFDFF, 7E000200] test_vsldoi_589_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF] test_vsldoi_590_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [11223344, 55667788, 99AABBCC, DDEEFFFF] test_vsldoi_591_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [22334455, 66778899, AABBCCDD, EEFFFFFF] test_vsldoi_592_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [778899AA, BBCCDDEE, FFFFFF01, 017070FF] test_vsldoi_593_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF] test_vsldoi_594_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [11223344, 55667788, 99AABBCC, DDEEFFFF] test_vsldoi_595_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [22334455, 66778899, AABBCCDD, EEFFFFFF] test_vsldoi_596_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [778899AA, BBCCDDEE, FFFFFFFF, 80000000] test_vsldoi_597_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF] test_vsldoi_598_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [11223344, 55667788, 99AABBCC, DDEEFFFF] test_vsldoi_599_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [22334455, 66778899, AABBCCDD, EEFFFFFF] test_vsldoi_600_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [778899AA, BBCCDDEE, FFFFFFFF, FFFFFFFF] test_vsldoi_601_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vsldoi_602_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FFFF0000, 00FF00FF, 0000FFFF, FF00FF00] test_vsldoi_603_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FF000000, FF00FF00, 00FFFFFF, 00FF0000] test_vsldoi_604_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00FF0000, FFFFFF00, FF000000, 00000000] test_vsldoi_605_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vsldoi_606_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FFFF0000, 00FF00FF, 0000FFFF, FF00FF00] test_vsldoi_607_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FF000000, FF00FF00, 00FFFFFF, 00FF0000] test_vsldoi_608_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00FF0000, FFFFFF00, FF000000, 01000000] test_vsldoi_609_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vsldoi_610_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FFFF0000, 00FF00FF, 0000FFFF, FF00FF00] test_vsldoi_611_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FF000000, FF00FF00, 00FFFFFF, 00FF0000] test_vsldoi_612_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00FF0000, FFFFFF00, FF0000FF, FFFFFF00] test_vsldoi_613_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vsldoi_614_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFF0000, 00FF00FF, 0000FFFF, FF00FF00] test_vsldoi_615_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FF000000, FF00FF00, 00FFFFFF, 00FF0001] test_vsldoi_616_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00FF0000, FFFFFF00, FF000102, 03040506] test_vsldoi_617_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vsldoi_618_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FFFF0000, 00FF00FF, 0000FFFF, FF00FF00] test_vsldoi_619_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FF000000, FF00FF00, 00FFFFFF, 00FF000D] test_vsldoi_620_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00FF0000, FFFFFF00, FF000D00, 0D000D00] test_vsldoi_621_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vsldoi_622_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FFFF0000, 00FF00FF, 0000FFFF, FF00FF00] test_vsldoi_623_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FF000000, FF00FF00, 00FFFFFF, 00FF0011] test_vsldoi_624_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00FF0000, FFFFFF00, FF001122, 33445566] test_vsldoi_625_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vsldoi_626_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FFFF0000, 00FF00FF, 0000FFFF, FF00FF04] test_vsldoi_627_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FF000000, FF00FF00, 00FFFFFF, 00FF0404] test_vsldoi_628_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00FF0000, FFFFFF00, FF040404, 04040404] test_vsldoi_629_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vsldoi_630_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FFFF0000, 00FF00FF, 0000FFFF, FF00FF07] test_vsldoi_631_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FF000000, FF00FF00, 00FFFFFF, 00FF0707] test_vsldoi_632_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00FF0000, FFFFFF00, FF070707, 07070707] test_vsldoi_633_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vsldoi_634_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FFFF0000, 00FF00FF, 0000FFFF, FF00FF08] test_vsldoi_635_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FF000000, FF00FF00, 00FFFFFF, 00FF0808] test_vsldoi_636_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00FF0000, FFFFFF00, FF080808, 08080808] test_vsldoi_637_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vsldoi_638_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FFFF0000, 00FF00FF, 0000FFFF, FF00FF12] test_vsldoi_639_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FF000000, FF00FF00, 00FFFFFF, 00FF1212] test_vsldoi_640_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00FF0000, FFFFFF00, FF121212, 12121212] test_vsldoi_641_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vsldoi_642_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FFFF0000, 00FF00FF, 0000FFFF, FF00FF12] test_vsldoi_643_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FF000000, FF00FF00, 00FFFFFF, 00FF1234] test_vsldoi_644_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00FF0000, FFFFFF00, FF123456, 78876543] test_vsldoi_645_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vsldoi_646_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FFFF0000, 00FF00FF, 0000FFFF, FF00FF3F] test_vsldoi_647_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FF000000, FF00FF00, 00FFFFFF, 00FF3F80] test_vsldoi_648_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [00FF0000, FFFFFF00, FF3F8000, 003FC000] test_vsldoi_649_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vsldoi_650_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FFFF0000, 00FF00FF, 0000FFFF, FF00FF41] test_vsldoi_651_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FF000000, FF00FF00, 00FFFFFF, 00FF4120] test_vsldoi_652_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [00FF0000, FFFFFF00, FF412000, 00C12000] test_vsldoi_653_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vsldoi_654_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFF0000, 00FF00FF, 0000FFFF, FF00FF7F] test_vsldoi_655_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FF000000, FF00FF00, 00FFFFFF, 00FF7F80] test_vsldoi_656_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00FF0000, FFFFFF00, FF7F8002, 03040506] test_vsldoi_657_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vsldoi_658_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [FFFF0000, 00FF00FF, 0000FFFF, FF00FF80] test_vsldoi_659_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [FF000000, FF00FF00, 00FFFFFF, 00FF8008] test_vsldoi_660_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [00FF0000, FFFFFF00, FF800810, 10808F00] test_vsldoi_661_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vsldoi_662_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [FFFF0000, 00FF00FF, 0000FFFF, FF00FFBF] test_vsldoi_663_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [FF000000, FF00FF00, 00FFFFFF, 00FFBF80] test_vsldoi_664_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [00FF0000, FFFFFF00, FFBF8000, 00BFC000] test_vsldoi_665_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vsldoi_666_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [FFFF0000, 00FF00FF, 0000FFFF, FF00FFC1] test_vsldoi_667_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [FF000000, FF00FF00, 00FFFFFF, 00FFC120] test_vsldoi_668_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [00FF0000, FFFFFF00, FFC12000, 0041A000] test_vsldoi_669_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vsldoi_670_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [FFFF0000, 00FF00FF, 0000FFFF, FF00FFCD] test_vsldoi_671_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [FF000000, FF00FF00, 00FFFFFF, 00FFCDCD] test_vsldoi_672_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [00FF0000, FFFFFF00, FFCDCDCD, CDCDCDCD] test_vsldoi_673_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vsldoi_674_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [FFFF0000, 00FF00FF, 0000FFFF, FF00FFF8] test_vsldoi_675_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [FF000000, FF00FF00, 00FFFFFF, 00FFF8F9] test_vsldoi_676_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [00FF0000, FFFFFF00, FFF8F9FA, FBFCFDFE] test_vsldoi_677_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vsldoi_678_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FFFF0000, 00FF00FF, 0000FFFF, FF00FFFE] test_vsldoi_679_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FF000000, FF00FF00, 00FFFFFF, 00FFFEFE] test_vsldoi_680_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [00FF0000, FFFFFF00, FFFEFEFE, FEFEFEFE] test_vsldoi_681_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vsldoi_682_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFF0000, 00FF00FF, 0000FFFF, FF00FFFF] test_vsldoi_683_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FF000000, FF00FF00, 00FFFFFF, 00FFFFFC] test_vsldoi_684_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [00FF0000, FFFFFF00, FFFFFCFF, FDFFFEFF] test_vsldoi_685_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vsldoi_686_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFF0000, 00FF00FF, 0000FFFF, FF00FFFF] test_vsldoi_687_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FF000000, FF00FF00, 00FFFFFF, 00FFFFFD] test_vsldoi_688_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [00FF0000, FFFFFF00, FFFFFDFF, 7E000200] test_vsldoi_689_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vsldoi_690_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0000, 00FF00FF, 0000FFFF, FF00FFFF] test_vsldoi_691_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FF000000, FF00FF00, 00FFFFFF, 00FFFFFF] test_vsldoi_692_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [00FF0000, FFFFFF00, FFFFFF01, 017070FF] test_vsldoi_693_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vsldoi_694_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFF0000, 00FF00FF, 0000FFFF, FF00FFFF] test_vsldoi_695_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FF000000, FF00FF00, 00FFFFFF, 00FFFFFF] test_vsldoi_696_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [00FF0000, FFFFFF00, FFFFFFFF, 80000000] test_vsldoi_697_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vsldoi_698_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFF0000, 00FF00FF, 0000FFFF, FF00FFFF] test_vsldoi_699_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FF000000, FF00FF00, 00FFFFFF, 00FFFFFF] test_vsldoi_700_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [00FF0000, FFFFFF00, FFFFFFFF, FFFFFFFF] test_vsldoi_701_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vsldoi_702_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040400] test_vsldoi_703_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040000] test_vsldoi_704_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [04040404, 04040404, 04000000, 00000000] test_vsldoi_705_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vsldoi_706_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040400] test_vsldoi_707_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040000] test_vsldoi_708_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [04040404, 04040404, 04000000, 01000000] test_vsldoi_709_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vsldoi_710_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040400] test_vsldoi_711_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040000] test_vsldoi_712_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [04040404, 04040404, 040000FF, FFFFFF00] test_vsldoi_713_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vsldoi_714_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040400] test_vsldoi_715_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040001] test_vsldoi_716_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [04040404, 04040404, 04000102, 03040506] test_vsldoi_717_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vsldoi_718_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040400] test_vsldoi_719_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 0404000D] test_vsldoi_720_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [04040404, 04040404, 04000D00, 0D000D00] test_vsldoi_721_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vsldoi_722_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040400] test_vsldoi_723_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040011] test_vsldoi_724_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [04040404, 04040404, 04001122, 33445566] test_vsldoi_725_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vsldoi_726_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040400] test_vsldoi_727_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 040400FF] test_vsldoi_728_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [04040404, 04040404, 0400FFFF, 000000FF] test_vsldoi_729_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vsldoi_730_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040407] test_vsldoi_731_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040707] test_vsldoi_732_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [04040404, 04040404, 04070707, 07070707] test_vsldoi_733_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vsldoi_734_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040408] test_vsldoi_735_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040808] test_vsldoi_736_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [04040404, 04040404, 04080808, 08080808] test_vsldoi_737_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vsldoi_738_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040412] test_vsldoi_739_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04041212] test_vsldoi_740_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [04040404, 04040404, 04121212, 12121212] test_vsldoi_741_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vsldoi_742_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040412] test_vsldoi_743_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04041234] test_vsldoi_744_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [04040404, 04040404, 04123456, 78876543] test_vsldoi_745_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vsldoi_746_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 0404043F] test_vsldoi_747_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04043F80] test_vsldoi_748_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [04040404, 04040404, 043F8000, 003FC000] test_vsldoi_749_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vsldoi_750_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040441] test_vsldoi_751_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04044120] test_vsldoi_752_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [04040404, 04040404, 04412000, 00C12000] test_vsldoi_753_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vsldoi_754_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 0404047F] test_vsldoi_755_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04047F80] test_vsldoi_756_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [04040404, 04040404, 047F8002, 03040506] test_vsldoi_757_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vsldoi_758_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040480] test_vsldoi_759_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04048008] test_vsldoi_760_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [04040404, 04040404, 04800810, 10808F00] test_vsldoi_761_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vsldoi_762_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 040404BF] test_vsldoi_763_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 0404BF80] test_vsldoi_764_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [04040404, 04040404, 04BF8000, 00BFC000] test_vsldoi_765_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vsldoi_766_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 040404C1] test_vsldoi_767_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 0404C120] test_vsldoi_768_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [04040404, 04040404, 04C12000, 0041A000] test_vsldoi_769_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vsldoi_770_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 040404CD] test_vsldoi_771_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 0404CDCD] test_vsldoi_772_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [04040404, 04040404, 04CDCDCD, CDCDCDCD] test_vsldoi_773_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vsldoi_774_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 040404F8] test_vsldoi_775_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 0404F8F9] test_vsldoi_776_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [04040404, 04040404, 04F8F9FA, FBFCFDFE] test_vsldoi_777_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vsldoi_778_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 040404FE] test_vsldoi_779_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 0404FEFE] test_vsldoi_780_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [04040404, 04040404, 04FEFEFE, FEFEFEFE] test_vsldoi_781_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vsldoi_782_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 040404FF] test_vsldoi_783_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 0404FFFC] test_vsldoi_784_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [04040404, 04040404, 04FFFCFF, FDFFFEFF] test_vsldoi_785_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vsldoi_786_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 040404FF] test_vsldoi_787_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 0404FFFD] test_vsldoi_788_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [04040404, 04040404, 04FFFDFF, 7E000200] test_vsldoi_789_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vsldoi_790_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 040404FF] test_vsldoi_791_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 0404FFFF] test_vsldoi_792_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [04040404, 04040404, 04FFFF01, 017070FF] test_vsldoi_793_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vsldoi_794_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 040404FF] test_vsldoi_795_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 0404FFFF] test_vsldoi_796_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [04040404, 04040404, 04FFFFFF, 80000000] test_vsldoi_797_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vsldoi_798_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 040404FF] test_vsldoi_799_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 0404FFFF] test_vsldoi_800_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [04040404, 04040404, 04FFFFFF, FFFFFFFF] test_vsldoi_801_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vsldoi_802_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070700] test_vsldoi_803_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070000] test_vsldoi_804_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [07070707, 07070707, 07000000, 00000000] test_vsldoi_805_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vsldoi_806_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070700] test_vsldoi_807_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070000] test_vsldoi_808_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [07070707, 07070707, 07000000, 01000000] test_vsldoi_809_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vsldoi_810_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070700] test_vsldoi_811_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070000] test_vsldoi_812_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [07070707, 07070707, 070000FF, FFFFFF00] test_vsldoi_813_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vsldoi_814_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070700] test_vsldoi_815_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070001] test_vsldoi_816_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [07070707, 07070707, 07000102, 03040506] test_vsldoi_817_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vsldoi_818_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070700] test_vsldoi_819_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 0707000D] test_vsldoi_820_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [07070707, 07070707, 07000D00, 0D000D00] test_vsldoi_821_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vsldoi_822_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070700] test_vsldoi_823_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070011] test_vsldoi_824_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [07070707, 07070707, 07001122, 33445566] test_vsldoi_825_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vsldoi_826_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070700] test_vsldoi_827_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 070700FF] test_vsldoi_828_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [07070707, 07070707, 0700FFFF, 000000FF] test_vsldoi_829_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vsldoi_830_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070704] test_vsldoi_831_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070404] test_vsldoi_832_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [07070707, 07070707, 07040404, 04040404] test_vsldoi_833_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vsldoi_834_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070708] test_vsldoi_835_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070808] test_vsldoi_836_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [07070707, 07070707, 07080808, 08080808] test_vsldoi_837_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vsldoi_838_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070712] test_vsldoi_839_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07071212] test_vsldoi_840_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [07070707, 07070707, 07121212, 12121212] test_vsldoi_841_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vsldoi_842_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070712] test_vsldoi_843_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07071234] test_vsldoi_844_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [07070707, 07070707, 07123456, 78876543] test_vsldoi_845_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vsldoi_846_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 0707073F] test_vsldoi_847_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07073F80] test_vsldoi_848_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [07070707, 07070707, 073F8000, 003FC000] test_vsldoi_849_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vsldoi_850_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070741] test_vsldoi_851_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07074120] test_vsldoi_852_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [07070707, 07070707, 07412000, 00C12000] test_vsldoi_853_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vsldoi_854_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 0707077F] test_vsldoi_855_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07077F80] test_vsldoi_856_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [07070707, 07070707, 077F8002, 03040506] test_vsldoi_857_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vsldoi_858_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070780] test_vsldoi_859_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07078008] test_vsldoi_860_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [07070707, 07070707, 07800810, 10808F00] test_vsldoi_861_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vsldoi_862_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 070707BF] test_vsldoi_863_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 0707BF80] test_vsldoi_864_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [07070707, 07070707, 07BF8000, 00BFC000] test_vsldoi_865_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vsldoi_866_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 070707C1] test_vsldoi_867_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 0707C120] test_vsldoi_868_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [07070707, 07070707, 07C12000, 0041A000] test_vsldoi_869_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vsldoi_870_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 070707CD] test_vsldoi_871_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 0707CDCD] test_vsldoi_872_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [07070707, 07070707, 07CDCDCD, CDCDCDCD] test_vsldoi_873_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vsldoi_874_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 070707F8] test_vsldoi_875_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 0707F8F9] test_vsldoi_876_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [07070707, 07070707, 07F8F9FA, FBFCFDFE] test_vsldoi_877_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vsldoi_878_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 070707FE] test_vsldoi_879_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 0707FEFE] test_vsldoi_880_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [07070707, 07070707, 07FEFEFE, FEFEFEFE] test_vsldoi_881_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vsldoi_882_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 070707FF] test_vsldoi_883_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 0707FFFC] test_vsldoi_884_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [07070707, 07070707, 07FFFCFF, FDFFFEFF] test_vsldoi_885_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vsldoi_886_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 070707FF] test_vsldoi_887_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 0707FFFD] test_vsldoi_888_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [07070707, 07070707, 07FFFDFF, 7E000200] test_vsldoi_889_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vsldoi_890_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 070707FF] test_vsldoi_891_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 0707FFFF] test_vsldoi_892_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [07070707, 07070707, 07FFFF01, 017070FF] test_vsldoi_893_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vsldoi_894_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 070707FF] test_vsldoi_895_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 0707FFFF] test_vsldoi_896_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [07070707, 07070707, 07FFFFFF, 80000000] test_vsldoi_897_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vsldoi_898_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 070707FF] test_vsldoi_899_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 0707FFFF] test_vsldoi_900_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [07070707, 07070707, 07FFFFFF, FFFFFFFF] test_vsldoi_901_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vsldoi_902_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080800] test_vsldoi_903_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080000] test_vsldoi_904_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [08080808, 08080808, 08000000, 00000000] test_vsldoi_905_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vsldoi_906_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080800] test_vsldoi_907_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080000] test_vsldoi_908_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [08080808, 08080808, 08000000, 01000000] test_vsldoi_909_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vsldoi_910_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080800] test_vsldoi_911_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080000] test_vsldoi_912_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [08080808, 08080808, 080000FF, FFFFFF00] test_vsldoi_913_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vsldoi_914_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080800] test_vsldoi_915_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080001] test_vsldoi_916_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [08080808, 08080808, 08000102, 03040506] test_vsldoi_917_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vsldoi_918_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080800] test_vsldoi_919_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 0808000D] test_vsldoi_920_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [08080808, 08080808, 08000D00, 0D000D00] test_vsldoi_921_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vsldoi_922_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080800] test_vsldoi_923_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080011] test_vsldoi_924_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [08080808, 08080808, 08001122, 33445566] test_vsldoi_925_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vsldoi_926_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080800] test_vsldoi_927_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 080800FF] test_vsldoi_928_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [08080808, 08080808, 0800FFFF, 000000FF] test_vsldoi_929_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vsldoi_930_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080804] test_vsldoi_931_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080404] test_vsldoi_932_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [08080808, 08080808, 08040404, 04040404] test_vsldoi_933_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vsldoi_934_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080807] test_vsldoi_935_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080707] test_vsldoi_936_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [08080808, 08080808, 08070707, 07070707] test_vsldoi_937_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vsldoi_938_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080812] test_vsldoi_939_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08081212] test_vsldoi_940_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [08080808, 08080808, 08121212, 12121212] test_vsldoi_941_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vsldoi_942_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080812] test_vsldoi_943_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08081234] test_vsldoi_944_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [08080808, 08080808, 08123456, 78876543] test_vsldoi_945_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vsldoi_946_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 0808083F] test_vsldoi_947_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08083F80] test_vsldoi_948_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [08080808, 08080808, 083F8000, 003FC000] test_vsldoi_949_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vsldoi_950_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080841] test_vsldoi_951_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08084120] test_vsldoi_952_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [08080808, 08080808, 08412000, 00C12000] test_vsldoi_953_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vsldoi_954_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 0808087F] test_vsldoi_955_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08087F80] test_vsldoi_956_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [08080808, 08080808, 087F8002, 03040506] test_vsldoi_957_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vsldoi_958_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080880] test_vsldoi_959_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08088008] test_vsldoi_960_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [08080808, 08080808, 08800810, 10808F00] test_vsldoi_961_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vsldoi_962_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 080808BF] test_vsldoi_963_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 0808BF80] test_vsldoi_964_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [08080808, 08080808, 08BF8000, 00BFC000] test_vsldoi_965_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vsldoi_966_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 080808C1] test_vsldoi_967_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 0808C120] test_vsldoi_968_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [08080808, 08080808, 08C12000, 0041A000] test_vsldoi_969_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vsldoi_970_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 080808CD] test_vsldoi_971_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 0808CDCD] test_vsldoi_972_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [08080808, 08080808, 08CDCDCD, CDCDCDCD] test_vsldoi_973_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vsldoi_974_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 080808F8] test_vsldoi_975_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 0808F8F9] test_vsldoi_976_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [08080808, 08080808, 08F8F9FA, FBFCFDFE] test_vsldoi_977_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vsldoi_978_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 080808FE] test_vsldoi_979_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 0808FEFE] test_vsldoi_980_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [08080808, 08080808, 08FEFEFE, FEFEFEFE] test_vsldoi_981_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vsldoi_982_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 080808FF] test_vsldoi_983_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 0808FFFC] test_vsldoi_984_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [08080808, 08080808, 08FFFCFF, FDFFFEFF] test_vsldoi_985_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vsldoi_986_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 080808FF] test_vsldoi_987_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 0808FFFD] test_vsldoi_988_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [08080808, 08080808, 08FFFDFF, 7E000200] test_vsldoi_989_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vsldoi_990_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 080808FF] test_vsldoi_991_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 0808FFFF] test_vsldoi_992_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [08080808, 08080808, 08FFFF01, 017070FF] test_vsldoi_993_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vsldoi_994_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 080808FF] test_vsldoi_995_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 0808FFFF] test_vsldoi_996_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [08080808, 08080808, 08FFFFFF, 80000000] test_vsldoi_997_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vsldoi_998_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 080808FF] test_vsldoi_999_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 0808FFFF] test_vsldoi_1000_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [08080808, 08080808, 08FFFFFF, FFFFFFFF] test_vsldoi_1001_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212] test_vsldoi_1002_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121200] test_vsldoi_1003_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12120000] test_vsldoi_1004_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [12121212, 12121212, 12000000, 00000000] test_vsldoi_1005_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212] test_vsldoi_1006_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121200] test_vsldoi_1007_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12120000] test_vsldoi_1008_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [12121212, 12121212, 12000000, 01000000] test_vsldoi_1009_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212] test_vsldoi_1010_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121200] test_vsldoi_1011_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12120000] test_vsldoi_1012_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [12121212, 12121212, 120000FF, FFFFFF00] test_vsldoi_1013_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212] test_vsldoi_1014_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121200] test_vsldoi_1015_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12120001] test_vsldoi_1016_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [12121212, 12121212, 12000102, 03040506] test_vsldoi_1017_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212] test_vsldoi_1018_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121200] test_vsldoi_1019_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 1212000D] test_vsldoi_1020_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [12121212, 12121212, 12000D00, 0D000D00] test_vsldoi_1021_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212] test_vsldoi_1022_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121200] test_vsldoi_1023_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12120011] test_vsldoi_1024_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [12121212, 12121212, 12001122, 33445566] test_vsldoi_1025_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212] test_vsldoi_1026_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121200] test_vsldoi_1027_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 121200FF] test_vsldoi_1028_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [12121212, 12121212, 1200FFFF, 000000FF] test_vsldoi_1029_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212] test_vsldoi_1030_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121204] test_vsldoi_1031_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12120404] test_vsldoi_1032_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [12121212, 12121212, 12040404, 04040404] test_vsldoi_1033_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212] test_vsldoi_1034_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121207] test_vsldoi_1035_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12120707] test_vsldoi_1036_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [12121212, 12121212, 12070707, 07070707] test_vsldoi_1037_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212] test_vsldoi_1038_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121208] test_vsldoi_1039_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12120808] test_vsldoi_1040_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [12121212, 12121212, 12080808, 08080808] test_vsldoi_1041_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212] test_vsldoi_1042_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212] test_vsldoi_1043_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121234] test_vsldoi_1044_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [12121212, 12121212, 12123456, 78876543] test_vsldoi_1045_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212] test_vsldoi_1046_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 1212123F] test_vsldoi_1047_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12123F80] test_vsldoi_1048_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [12121212, 12121212, 123F8000, 003FC000] test_vsldoi_1049_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212] test_vsldoi_1050_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121241] test_vsldoi_1051_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12124120] test_vsldoi_1052_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [12121212, 12121212, 12412000, 00C12000] test_vsldoi_1053_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212] test_vsldoi_1054_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 1212127F] test_vsldoi_1055_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12127F80] test_vsldoi_1056_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [12121212, 12121212, 127F8002, 03040506] test_vsldoi_1057_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212] test_vsldoi_1058_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121280] test_vsldoi_1059_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12128008] test_vsldoi_1060_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [12121212, 12121212, 12800810, 10808F00] test_vsldoi_1061_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212] test_vsldoi_1062_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 121212BF] test_vsldoi_1063_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 1212BF80] test_vsldoi_1064_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [12121212, 12121212, 12BF8000, 00BFC000] test_vsldoi_1065_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212] test_vsldoi_1066_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 121212C1] test_vsldoi_1067_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 1212C120] test_vsldoi_1068_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [12121212, 12121212, 12C12000, 0041A000] test_vsldoi_1069_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212] test_vsldoi_1070_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 121212CD] test_vsldoi_1071_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 1212CDCD] test_vsldoi_1072_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [12121212, 12121212, 12CDCDCD, CDCDCDCD] test_vsldoi_1073_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212] test_vsldoi_1074_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 121212F8] test_vsldoi_1075_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 1212F8F9] test_vsldoi_1076_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [12121212, 12121212, 12F8F9FA, FBFCFDFE] test_vsldoi_1077_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212] test_vsldoi_1078_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 121212FE] test_vsldoi_1079_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 1212FEFE] test_vsldoi_1080_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [12121212, 12121212, 12FEFEFE, FEFEFEFE] test_vsldoi_1081_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212] test_vsldoi_1082_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 121212FF] test_vsldoi_1083_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 1212FFFC] test_vsldoi_1084_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [12121212, 12121212, 12FFFCFF, FDFFFEFF] test_vsldoi_1085_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212] test_vsldoi_1086_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 121212FF] test_vsldoi_1087_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 1212FFFD] test_vsldoi_1088_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [12121212, 12121212, 12FFFDFF, 7E000200] test_vsldoi_1089_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212] test_vsldoi_1090_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 121212FF] test_vsldoi_1091_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 1212FFFF] test_vsldoi_1092_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [12121212, 12121212, 12FFFF01, 017070FF] test_vsldoi_1093_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212] test_vsldoi_1094_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 121212FF] test_vsldoi_1095_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 1212FFFF] test_vsldoi_1096_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [12121212, 12121212, 12FFFFFF, 80000000] test_vsldoi_1097_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212] test_vsldoi_1098_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 121212FF] test_vsldoi_1099_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 1212FFFF] test_vsldoi_1100_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [12121212, 12121212, 12FFFFFF, FFFFFFFF] test_vsldoi_1101_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788] test_vsldoi_1102_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [34567887, 65432111, 22334455, 66778800] test_vsldoi_1103_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [56788765, 43211122, 33445566, 77880000] test_vsldoi_1104_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [21112233, 44556677, 88000000, 00000000] test_vsldoi_1105_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788] test_vsldoi_1106_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [34567887, 65432111, 22334455, 66778800] test_vsldoi_1107_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [56788765, 43211122, 33445566, 77880000] test_vsldoi_1108_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [21112233, 44556677, 88000000, 01000000] test_vsldoi_1109_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788] test_vsldoi_1110_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [34567887, 65432111, 22334455, 66778800] test_vsldoi_1111_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [56788765, 43211122, 33445566, 77880000] test_vsldoi_1112_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [21112233, 44556677, 880000FF, FFFFFF00] test_vsldoi_1113_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788] test_vsldoi_1114_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [34567887, 65432111, 22334455, 66778800] test_vsldoi_1115_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [56788765, 43211122, 33445566, 77880001] test_vsldoi_1116_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [21112233, 44556677, 88000102, 03040506] test_vsldoi_1117_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788] test_vsldoi_1118_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [34567887, 65432111, 22334455, 66778800] test_vsldoi_1119_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [56788765, 43211122, 33445566, 7788000D] test_vsldoi_1120_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [21112233, 44556677, 88000D00, 0D000D00] test_vsldoi_1121_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788] test_vsldoi_1122_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [34567887, 65432111, 22334455, 66778800] test_vsldoi_1123_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [56788765, 43211122, 33445566, 77880011] test_vsldoi_1124_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [21112233, 44556677, 88001122, 33445566] test_vsldoi_1125_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788] test_vsldoi_1126_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [34567887, 65432111, 22334455, 66778800] test_vsldoi_1127_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [56788765, 43211122, 33445566, 778800FF] test_vsldoi_1128_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [21112233, 44556677, 8800FFFF, 000000FF] test_vsldoi_1129_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788] test_vsldoi_1130_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [34567887, 65432111, 22334455, 66778804] test_vsldoi_1131_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [56788765, 43211122, 33445566, 77880404] test_vsldoi_1132_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [21112233, 44556677, 88040404, 04040404] test_vsldoi_1133_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788] test_vsldoi_1134_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [34567887, 65432111, 22334455, 66778807] test_vsldoi_1135_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [56788765, 43211122, 33445566, 77880707] test_vsldoi_1136_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [21112233, 44556677, 88070707, 07070707] test_vsldoi_1137_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788] test_vsldoi_1138_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [34567887, 65432111, 22334455, 66778808] test_vsldoi_1139_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [56788765, 43211122, 33445566, 77880808] test_vsldoi_1140_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [21112233, 44556677, 88080808, 08080808] test_vsldoi_1141_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788] test_vsldoi_1142_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [34567887, 65432111, 22334455, 66778812] test_vsldoi_1143_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [56788765, 43211122, 33445566, 77881212] test_vsldoi_1144_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [21112233, 44556677, 88121212, 12121212] test_vsldoi_1145_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788] test_vsldoi_1146_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [34567887, 65432111, 22334455, 6677883F] test_vsldoi_1147_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [56788765, 43211122, 33445566, 77883F80] test_vsldoi_1148_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [21112233, 44556677, 883F8000, 003FC000] test_vsldoi_1149_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788] test_vsldoi_1150_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [34567887, 65432111, 22334455, 66778841] test_vsldoi_1151_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [56788765, 43211122, 33445566, 77884120] test_vsldoi_1152_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [21112233, 44556677, 88412000, 00C12000] test_vsldoi_1153_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788] test_vsldoi_1154_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [34567887, 65432111, 22334455, 6677887F] test_vsldoi_1155_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [56788765, 43211122, 33445566, 77887F80] test_vsldoi_1156_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [21112233, 44556677, 887F8002, 03040506] test_vsldoi_1157_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788] test_vsldoi_1158_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [34567887, 65432111, 22334455, 66778880] test_vsldoi_1159_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [56788765, 43211122, 33445566, 77888008] test_vsldoi_1160_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [21112233, 44556677, 88800810, 10808F00] test_vsldoi_1161_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788] test_vsldoi_1162_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [34567887, 65432111, 22334455, 667788BF] test_vsldoi_1163_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [56788765, 43211122, 33445566, 7788BF80] test_vsldoi_1164_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [21112233, 44556677, 88BF8000, 00BFC000] test_vsldoi_1165_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788] test_vsldoi_1166_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [34567887, 65432111, 22334455, 667788C1] test_vsldoi_1167_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [56788765, 43211122, 33445566, 7788C120] test_vsldoi_1168_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [21112233, 44556677, 88C12000, 0041A000] test_vsldoi_1169_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788] test_vsldoi_1170_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [34567887, 65432111, 22334455, 667788CD] test_vsldoi_1171_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [56788765, 43211122, 33445566, 7788CDCD] test_vsldoi_1172_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [21112233, 44556677, 88CDCDCD, CDCDCDCD] test_vsldoi_1173_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788] test_vsldoi_1174_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [34567887, 65432111, 22334455, 667788F8] test_vsldoi_1175_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [56788765, 43211122, 33445566, 7788F8F9] test_vsldoi_1176_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [21112233, 44556677, 88F8F9FA, FBFCFDFE] test_vsldoi_1177_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788] test_vsldoi_1178_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [34567887, 65432111, 22334455, 667788FE] test_vsldoi_1179_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [56788765, 43211122, 33445566, 7788FEFE] test_vsldoi_1180_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [21112233, 44556677, 88FEFEFE, FEFEFEFE] test_vsldoi_1181_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788] test_vsldoi_1182_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [34567887, 65432111, 22334455, 667788FF] test_vsldoi_1183_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [56788765, 43211122, 33445566, 7788FFFC] test_vsldoi_1184_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [21112233, 44556677, 88FFFCFF, FDFFFEFF] test_vsldoi_1185_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788] test_vsldoi_1186_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [34567887, 65432111, 22334455, 667788FF] test_vsldoi_1187_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [56788765, 43211122, 33445566, 7788FFFD] test_vsldoi_1188_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [21112233, 44556677, 88FFFDFF, 7E000200] test_vsldoi_1189_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788] test_vsldoi_1190_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [34567887, 65432111, 22334455, 667788FF] test_vsldoi_1191_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [56788765, 43211122, 33445566, 7788FFFF] test_vsldoi_1192_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [21112233, 44556677, 88FFFF01, 017070FF] test_vsldoi_1193_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788] test_vsldoi_1194_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [34567887, 65432111, 22334455, 667788FF] test_vsldoi_1195_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [56788765, 43211122, 33445566, 7788FFFF] test_vsldoi_1196_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [21112233, 44556677, 88FFFFFF, 80000000] test_vsldoi_1197_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788] test_vsldoi_1198_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [34567887, 65432111, 22334455, 667788FF] test_vsldoi_1199_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [56788765, 43211122, 33445566, 7788FFFF] test_vsldoi_1200_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [21112233, 44556677, 88FFFFFF, FFFFFFFF] test_vsldoi_1201_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] test_vsldoi_1202_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [8000003F, C000003F, 8CCCCD3F, F3333300] test_vsldoi_1203_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00003FC0, 00003F8C, CCCD3FF3, 33330000] test_vsldoi_1204_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [003F8CCC, CD3FF333, 33000000, 00000000] test_vsldoi_1205_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] test_vsldoi_1206_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [8000003F, C000003F, 8CCCCD3F, F3333300] test_vsldoi_1207_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00003FC0, 00003F8C, CCCD3FF3, 33330000] test_vsldoi_1208_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [003F8CCC, CD3FF333, 33000000, 01000000] test_vsldoi_1209_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] test_vsldoi_1210_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [8000003F, C000003F, 8CCCCD3F, F3333300] test_vsldoi_1211_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00003FC0, 00003F8C, CCCD3FF3, 33330000] test_vsldoi_1212_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [003F8CCC, CD3FF333, 330000FF, FFFFFF00] test_vsldoi_1213_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] test_vsldoi_1214_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [8000003F, C000003F, 8CCCCD3F, F3333300] test_vsldoi_1215_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00003FC0, 00003F8C, CCCD3FF3, 33330001] test_vsldoi_1216_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [003F8CCC, CD3FF333, 33000102, 03040506] test_vsldoi_1217_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] test_vsldoi_1218_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [8000003F, C000003F, 8CCCCD3F, F3333300] test_vsldoi_1219_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00003FC0, 00003F8C, CCCD3FF3, 3333000D] test_vsldoi_1220_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [003F8CCC, CD3FF333, 33000D00, 0D000D00] test_vsldoi_1221_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] test_vsldoi_1222_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [8000003F, C000003F, 8CCCCD3F, F3333300] test_vsldoi_1223_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00003FC0, 00003F8C, CCCD3FF3, 33330011] test_vsldoi_1224_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [003F8CCC, CD3FF333, 33001122, 33445566] test_vsldoi_1225_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] test_vsldoi_1226_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [8000003F, C000003F, 8CCCCD3F, F3333300] test_vsldoi_1227_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00003FC0, 00003F8C, CCCD3FF3, 333300FF] test_vsldoi_1228_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [003F8CCC, CD3FF333, 3300FFFF, 000000FF] test_vsldoi_1229_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] test_vsldoi_1230_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [8000003F, C000003F, 8CCCCD3F, F3333304] test_vsldoi_1231_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00003FC0, 00003F8C, CCCD3FF3, 33330404] test_vsldoi_1232_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [003F8CCC, CD3FF333, 33040404, 04040404] test_vsldoi_1233_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] test_vsldoi_1234_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [8000003F, C000003F, 8CCCCD3F, F3333307] test_vsldoi_1235_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00003FC0, 00003F8C, CCCD3FF3, 33330707] test_vsldoi_1236_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [003F8CCC, CD3FF333, 33070707, 07070707] test_vsldoi_1237_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] test_vsldoi_1238_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [8000003F, C000003F, 8CCCCD3F, F3333308] test_vsldoi_1239_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00003FC0, 00003F8C, CCCD3FF3, 33330808] test_vsldoi_1240_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [003F8CCC, CD3FF333, 33080808, 08080808] test_vsldoi_1241_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] test_vsldoi_1242_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [8000003F, C000003F, 8CCCCD3F, F3333312] test_vsldoi_1243_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00003FC0, 00003F8C, CCCD3FF3, 33331212] test_vsldoi_1244_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [003F8CCC, CD3FF333, 33121212, 12121212] test_vsldoi_1245_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] test_vsldoi_1246_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [8000003F, C000003F, 8CCCCD3F, F3333312] test_vsldoi_1247_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00003FC0, 00003F8C, CCCD3FF3, 33331234] test_vsldoi_1248_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [003F8CCC, CD3FF333, 33123456, 78876543] test_vsldoi_1249_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] test_vsldoi_1250_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [8000003F, C000003F, 8CCCCD3F, F3333341] test_vsldoi_1251_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [00003FC0, 00003F8C, CCCD3FF3, 33334120] test_vsldoi_1252_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [003F8CCC, CD3FF333, 33412000, 00C12000] test_vsldoi_1253_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] test_vsldoi_1254_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [8000003F, C000003F, 8CCCCD3F, F333337F] test_vsldoi_1255_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00003FC0, 00003F8C, CCCD3FF3, 33337F80] test_vsldoi_1256_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [003F8CCC, CD3FF333, 337F8002, 03040506] test_vsldoi_1257_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] test_vsldoi_1258_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [8000003F, C000003F, 8CCCCD3F, F3333380] test_vsldoi_1259_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [00003FC0, 00003F8C, CCCD3FF3, 33338008] test_vsldoi_1260_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [003F8CCC, CD3FF333, 33800810, 10808F00] test_vsldoi_1261_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] test_vsldoi_1262_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [8000003F, C000003F, 8CCCCD3F, F33333BF] test_vsldoi_1263_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [00003FC0, 00003F8C, CCCD3FF3, 3333BF80] test_vsldoi_1264_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [003F8CCC, CD3FF333, 33BF8000, 00BFC000] test_vsldoi_1265_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] test_vsldoi_1266_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [8000003F, C000003F, 8CCCCD3F, F33333C1] test_vsldoi_1267_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [00003FC0, 00003F8C, CCCD3FF3, 3333C120] test_vsldoi_1268_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [003F8CCC, CD3FF333, 33C12000, 0041A000] test_vsldoi_1269_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] test_vsldoi_1270_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [8000003F, C000003F, 8CCCCD3F, F33333CD] test_vsldoi_1271_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [00003FC0, 00003F8C, CCCD3FF3, 3333CDCD] test_vsldoi_1272_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [003F8CCC, CD3FF333, 33CDCDCD, CDCDCDCD] test_vsldoi_1273_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] test_vsldoi_1274_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [8000003F, C000003F, 8CCCCD3F, F33333F8] test_vsldoi_1275_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [00003FC0, 00003F8C, CCCD3FF3, 3333F8F9] test_vsldoi_1276_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [003F8CCC, CD3FF333, 33F8F9FA, FBFCFDFE] test_vsldoi_1277_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] test_vsldoi_1278_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [8000003F, C000003F, 8CCCCD3F, F33333FE] test_vsldoi_1279_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [00003FC0, 00003F8C, CCCD3FF3, 3333FEFE] test_vsldoi_1280_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [003F8CCC, CD3FF333, 33FEFEFE, FEFEFEFE] test_vsldoi_1281_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] test_vsldoi_1282_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [8000003F, C000003F, 8CCCCD3F, F33333FF] test_vsldoi_1283_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [00003FC0, 00003F8C, CCCD3FF3, 3333FFFC] test_vsldoi_1284_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [003F8CCC, CD3FF333, 33FFFCFF, FDFFFEFF] test_vsldoi_1285_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] test_vsldoi_1286_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [8000003F, C000003F, 8CCCCD3F, F33333FF] test_vsldoi_1287_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [00003FC0, 00003F8C, CCCD3FF3, 3333FFFD] test_vsldoi_1288_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [003F8CCC, CD3FF333, 33FFFDFF, 7E000200] test_vsldoi_1289_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] test_vsldoi_1290_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [8000003F, C000003F, 8CCCCD3F, F33333FF] test_vsldoi_1291_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [00003FC0, 00003F8C, CCCD3FF3, 3333FFFF] test_vsldoi_1292_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [003F8CCC, CD3FF333, 33FFFF01, 017070FF] test_vsldoi_1293_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] test_vsldoi_1294_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [8000003F, C000003F, 8CCCCD3F, F33333FF] test_vsldoi_1295_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [00003FC0, 00003F8C, CCCD3FF3, 3333FFFF] test_vsldoi_1296_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [003F8CCC, CD3FF333, 33FFFFFF, 80000000] test_vsldoi_1297_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] test_vsldoi_1298_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [8000003F, C000003F, 8CCCCD3F, F33333FF] test_vsldoi_1299_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [00003FC0, 00003F8C, CCCD3FF3, 3333FFFF] test_vsldoi_1300_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [003F8CCC, CD3FF333, 33FFFFFF, FFFFFFFF] test_vsldoi_1301_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000] test_vsldoi_1302_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [200000C1, 20000041, 700000C1, 70000000] test_vsldoi_1303_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [0000C120, 00004170, 0000C170, 00000000] test_vsldoi_1304_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00417000, 00C17000, 00000000, 00000000] test_vsldoi_1305_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000] test_vsldoi_1306_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [200000C1, 20000041, 700000C1, 70000000] test_vsldoi_1307_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [0000C120, 00004170, 0000C170, 00000000] test_vsldoi_1308_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00417000, 00C17000, 00000000, 01000000] test_vsldoi_1309_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000] test_vsldoi_1310_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [200000C1, 20000041, 700000C1, 70000000] test_vsldoi_1311_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [0000C120, 00004170, 0000C170, 00000000] test_vsldoi_1312_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00417000, 00C17000, 000000FF, FFFFFF00] test_vsldoi_1313_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000] test_vsldoi_1314_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [200000C1, 20000041, 700000C1, 70000000] test_vsldoi_1315_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [0000C120, 00004170, 0000C170, 00000001] test_vsldoi_1316_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00417000, 00C17000, 00000102, 03040506] test_vsldoi_1317_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000] test_vsldoi_1318_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [200000C1, 20000041, 700000C1, 70000000] test_vsldoi_1319_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [0000C120, 00004170, 0000C170, 0000000D] test_vsldoi_1320_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00417000, 00C17000, 00000D00, 0D000D00] test_vsldoi_1321_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000] test_vsldoi_1322_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [200000C1, 20000041, 700000C1, 70000000] test_vsldoi_1323_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [0000C120, 00004170, 0000C170, 00000011] test_vsldoi_1324_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00417000, 00C17000, 00001122, 33445566] test_vsldoi_1325_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000] test_vsldoi_1326_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [200000C1, 20000041, 700000C1, 70000000] test_vsldoi_1327_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [0000C120, 00004170, 0000C170, 000000FF] test_vsldoi_1328_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00417000, 00C17000, 0000FFFF, 000000FF] test_vsldoi_1329_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000] test_vsldoi_1330_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [200000C1, 20000041, 700000C1, 70000004] test_vsldoi_1331_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [0000C120, 00004170, 0000C170, 00000404] test_vsldoi_1332_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00417000, 00C17000, 00040404, 04040404] test_vsldoi_1333_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000] test_vsldoi_1334_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [200000C1, 20000041, 700000C1, 70000007] test_vsldoi_1335_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [0000C120, 00004170, 0000C170, 00000707] test_vsldoi_1336_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00417000, 00C17000, 00070707, 07070707] test_vsldoi_1337_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000] test_vsldoi_1338_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [200000C1, 20000041, 700000C1, 70000008] test_vsldoi_1339_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [0000C120, 00004170, 0000C170, 00000808] test_vsldoi_1340_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00417000, 00C17000, 00080808, 08080808] test_vsldoi_1341_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000] test_vsldoi_1342_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [200000C1, 20000041, 700000C1, 70000012] test_vsldoi_1343_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [0000C120, 00004170, 0000C170, 00001212] test_vsldoi_1344_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00417000, 00C17000, 00121212, 12121212] test_vsldoi_1345_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000] test_vsldoi_1346_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [200000C1, 20000041, 700000C1, 70000012] test_vsldoi_1347_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [0000C120, 00004170, 0000C170, 00001234] test_vsldoi_1348_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00417000, 00C17000, 00123456, 78876543] test_vsldoi_1349_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000] test_vsldoi_1350_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [200000C1, 20000041, 700000C1, 7000003F] test_vsldoi_1351_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [0000C120, 00004170, 0000C170, 00003F80] test_vsldoi_1352_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [00417000, 00C17000, 003F8000, 003FC000] test_vsldoi_1353_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000] test_vsldoi_1354_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [200000C1, 20000041, 700000C1, 7000007F] test_vsldoi_1355_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [0000C120, 00004170, 0000C170, 00007F80] test_vsldoi_1356_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00417000, 00C17000, 007F8002, 03040506] test_vsldoi_1357_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000] test_vsldoi_1358_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [200000C1, 20000041, 700000C1, 70000080] test_vsldoi_1359_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [0000C120, 00004170, 0000C170, 00008008] test_vsldoi_1360_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [00417000, 00C17000, 00800810, 10808F00] test_vsldoi_1361_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000] test_vsldoi_1362_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [200000C1, 20000041, 700000C1, 700000BF] test_vsldoi_1363_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [0000C120, 00004170, 0000C170, 0000BF80] test_vsldoi_1364_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [00417000, 00C17000, 00BF8000, 00BFC000] test_vsldoi_1365_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000] test_vsldoi_1366_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [200000C1, 20000041, 700000C1, 700000C1] test_vsldoi_1367_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [0000C120, 00004170, 0000C170, 0000C120] test_vsldoi_1368_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [00417000, 00C17000, 00C12000, 0041A000] test_vsldoi_1369_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000] test_vsldoi_1370_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [200000C1, 20000041, 700000C1, 700000CD] test_vsldoi_1371_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [0000C120, 00004170, 0000C170, 0000CDCD] test_vsldoi_1372_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [00417000, 00C17000, 00CDCDCD, CDCDCDCD] test_vsldoi_1373_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000] test_vsldoi_1374_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [200000C1, 20000041, 700000C1, 700000F8] test_vsldoi_1375_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [0000C120, 00004170, 0000C170, 0000F8F9] test_vsldoi_1376_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [00417000, 00C17000, 00F8F9FA, FBFCFDFE] test_vsldoi_1377_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000] test_vsldoi_1378_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [200000C1, 20000041, 700000C1, 700000FE] test_vsldoi_1379_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [0000C120, 00004170, 0000C170, 0000FEFE] test_vsldoi_1380_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [00417000, 00C17000, 00FEFEFE, FEFEFEFE] test_vsldoi_1381_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000] test_vsldoi_1382_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [200000C1, 20000041, 700000C1, 700000FF] test_vsldoi_1383_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [0000C120, 00004170, 0000C170, 0000FFFC] test_vsldoi_1384_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [00417000, 00C17000, 00FFFCFF, FDFFFEFF] test_vsldoi_1385_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000] test_vsldoi_1386_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [200000C1, 20000041, 700000C1, 700000FF] test_vsldoi_1387_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [0000C120, 00004170, 0000C170, 0000FFFD] test_vsldoi_1388_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [00417000, 00C17000, 00FFFDFF, 7E000200] test_vsldoi_1389_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000] test_vsldoi_1390_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [200000C1, 20000041, 700000C1, 700000FF] test_vsldoi_1391_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [0000C120, 00004170, 0000C170, 0000FFFF] test_vsldoi_1392_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [00417000, 00C17000, 00FFFF01, 017070FF] test_vsldoi_1393_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000] test_vsldoi_1394_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [200000C1, 20000041, 700000C1, 700000FF] test_vsldoi_1395_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [0000C120, 00004170, 0000C170, 0000FFFF] test_vsldoi_1396_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [00417000, 00C17000, 00FFFFFF, 80000000] test_vsldoi_1397_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000] test_vsldoi_1398_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [200000C1, 20000041, 700000C1, 700000FF] test_vsldoi_1399_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [0000C120, 00004170, 0000C170, 0000FFFF] test_vsldoi_1400_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [00417000, 00C17000, 00FFFFFF, FFFFFFFF] test_vsldoi_1401_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] test_vsldoi_1402_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [80020304, 0506077F, 800A0B0C, 0D0E0F00] test_vsldoi_1403_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [02030405, 06077F80, 0A0B0C0D, 0E0F0000] test_vsldoi_1404_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [077F800A, 0B0C0D0E, 0F000000, 00000000] test_vsldoi_1405_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] test_vsldoi_1406_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [80020304, 0506077F, 800A0B0C, 0D0E0F00] test_vsldoi_1407_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [02030405, 06077F80, 0A0B0C0D, 0E0F0000] test_vsldoi_1408_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [077F800A, 0B0C0D0E, 0F000000, 01000000] test_vsldoi_1409_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] test_vsldoi_1410_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [80020304, 0506077F, 800A0B0C, 0D0E0F00] test_vsldoi_1411_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [02030405, 06077F80, 0A0B0C0D, 0E0F0000] test_vsldoi_1412_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [077F800A, 0B0C0D0E, 0F0000FF, FFFFFF00] test_vsldoi_1413_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] test_vsldoi_1414_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [80020304, 0506077F, 800A0B0C, 0D0E0F00] test_vsldoi_1415_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [02030405, 06077F80, 0A0B0C0D, 0E0F0001] test_vsldoi_1416_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [077F800A, 0B0C0D0E, 0F000102, 03040506] test_vsldoi_1417_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] test_vsldoi_1418_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [80020304, 0506077F, 800A0B0C, 0D0E0F00] test_vsldoi_1419_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [02030405, 06077F80, 0A0B0C0D, 0E0F000D] test_vsldoi_1420_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [077F800A, 0B0C0D0E, 0F000D00, 0D000D00] test_vsldoi_1421_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] test_vsldoi_1422_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [80020304, 0506077F, 800A0B0C, 0D0E0F00] test_vsldoi_1423_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [02030405, 06077F80, 0A0B0C0D, 0E0F0011] test_vsldoi_1424_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [077F800A, 0B0C0D0E, 0F001122, 33445566] test_vsldoi_1425_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] test_vsldoi_1426_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [80020304, 0506077F, 800A0B0C, 0D0E0F00] test_vsldoi_1427_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [02030405, 06077F80, 0A0B0C0D, 0E0F00FF] test_vsldoi_1428_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [077F800A, 0B0C0D0E, 0F00FFFF, 000000FF] test_vsldoi_1429_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] test_vsldoi_1430_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [80020304, 0506077F, 800A0B0C, 0D0E0F04] test_vsldoi_1431_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [02030405, 06077F80, 0A0B0C0D, 0E0F0404] test_vsldoi_1432_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [077F800A, 0B0C0D0E, 0F040404, 04040404] test_vsldoi_1433_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] test_vsldoi_1434_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [80020304, 0506077F, 800A0B0C, 0D0E0F07] test_vsldoi_1435_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [02030405, 06077F80, 0A0B0C0D, 0E0F0707] test_vsldoi_1436_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [077F800A, 0B0C0D0E, 0F070707, 07070707] test_vsldoi_1437_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] test_vsldoi_1438_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [80020304, 0506077F, 800A0B0C, 0D0E0F08] test_vsldoi_1439_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [02030405, 06077F80, 0A0B0C0D, 0E0F0808] test_vsldoi_1440_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [077F800A, 0B0C0D0E, 0F080808, 08080808] test_vsldoi_1441_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] test_vsldoi_1442_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [80020304, 0506077F, 800A0B0C, 0D0E0F12] test_vsldoi_1443_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [02030405, 06077F80, 0A0B0C0D, 0E0F1212] test_vsldoi_1444_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [077F800A, 0B0C0D0E, 0F121212, 12121212] test_vsldoi_1445_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] test_vsldoi_1446_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [80020304, 0506077F, 800A0B0C, 0D0E0F12] test_vsldoi_1447_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [02030405, 06077F80, 0A0B0C0D, 0E0F1234] test_vsldoi_1448_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [077F800A, 0B0C0D0E, 0F123456, 78876543] test_vsldoi_1449_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] test_vsldoi_1450_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [80020304, 0506077F, 800A0B0C, 0D0E0F3F] test_vsldoi_1451_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [02030405, 06077F80, 0A0B0C0D, 0E0F3F80] test_vsldoi_1452_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [077F800A, 0B0C0D0E, 0F3F8000, 003FC000] test_vsldoi_1453_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] test_vsldoi_1454_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [80020304, 0506077F, 800A0B0C, 0D0E0F41] test_vsldoi_1455_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [02030405, 06077F80, 0A0B0C0D, 0E0F4120] test_vsldoi_1456_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [077F800A, 0B0C0D0E, 0F412000, 00C12000] test_vsldoi_1457_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] test_vsldoi_1458_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80020304, 0506077F, 800A0B0C, 0D0E0F80] test_vsldoi_1459_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [02030405, 06077F80, 0A0B0C0D, 0E0F8008] test_vsldoi_1460_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [077F800A, 0B0C0D0E, 0F800810, 10808F00] test_vsldoi_1461_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] test_vsldoi_1462_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [80020304, 0506077F, 800A0B0C, 0D0E0FBF] test_vsldoi_1463_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [02030405, 06077F80, 0A0B0C0D, 0E0FBF80] test_vsldoi_1464_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [077F800A, 0B0C0D0E, 0FBF8000, 00BFC000] test_vsldoi_1465_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] test_vsldoi_1466_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [80020304, 0506077F, 800A0B0C, 0D0E0FC1] test_vsldoi_1467_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [02030405, 06077F80, 0A0B0C0D, 0E0FC120] test_vsldoi_1468_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [077F800A, 0B0C0D0E, 0FC12000, 0041A000] test_vsldoi_1469_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] test_vsldoi_1470_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [80020304, 0506077F, 800A0B0C, 0D0E0FCD] test_vsldoi_1471_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [02030405, 06077F80, 0A0B0C0D, 0E0FCDCD] test_vsldoi_1472_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [077F800A, 0B0C0D0E, 0FCDCDCD, CDCDCDCD] test_vsldoi_1473_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] test_vsldoi_1474_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [80020304, 0506077F, 800A0B0C, 0D0E0FF8] test_vsldoi_1475_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [02030405, 06077F80, 0A0B0C0D, 0E0FF8F9] test_vsldoi_1476_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [077F800A, 0B0C0D0E, 0FF8F9FA, FBFCFDFE] test_vsldoi_1477_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] test_vsldoi_1478_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [80020304, 0506077F, 800A0B0C, 0D0E0FFE] test_vsldoi_1479_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [02030405, 06077F80, 0A0B0C0D, 0E0FFEFE] test_vsldoi_1480_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [077F800A, 0B0C0D0E, 0FFEFEFE, FEFEFEFE] test_vsldoi_1481_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] test_vsldoi_1482_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [80020304, 0506077F, 800A0B0C, 0D0E0FFF] test_vsldoi_1483_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [02030405, 06077F80, 0A0B0C0D, 0E0FFFFC] test_vsldoi_1484_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [077F800A, 0B0C0D0E, 0FFFFCFF, FDFFFEFF] test_vsldoi_1485_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] test_vsldoi_1486_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [80020304, 0506077F, 800A0B0C, 0D0E0FFF] test_vsldoi_1487_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [02030405, 06077F80, 0A0B0C0D, 0E0FFFFD] test_vsldoi_1488_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [077F800A, 0B0C0D0E, 0FFFFDFF, 7E000200] test_vsldoi_1489_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] test_vsldoi_1490_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [80020304, 0506077F, 800A0B0C, 0D0E0FFF] test_vsldoi_1491_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [02030405, 06077F80, 0A0B0C0D, 0E0FFFFF] test_vsldoi_1492_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [077F800A, 0B0C0D0E, 0FFFFF01, 017070FF] test_vsldoi_1493_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] test_vsldoi_1494_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [80020304, 0506077F, 800A0B0C, 0D0E0FFF] test_vsldoi_1495_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [02030405, 06077F80, 0A0B0C0D, 0E0FFFFF] test_vsldoi_1496_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [077F800A, 0B0C0D0E, 0FFFFFFF, 80000000] test_vsldoi_1497_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] test_vsldoi_1498_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [80020304, 0506077F, 800A0B0C, 0D0E0FFF] test_vsldoi_1499_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [02030405, 06077F80, 0A0B0C0D, 0E0FFFFF] test_vsldoi_1500_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [077F800A, 0B0C0D0E, 0FFFFFFF, FFFFFFFF] test_vsldoi_1501_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vsldoi_1502_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [08101080, 8F00007F, FFFFFF8F, FFFFFF00] test_vsldoi_1503_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [1010808F, 00007FFF, FFFF8FFF, FFFF0000] test_vsldoi_1504_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [007FFFFF, FF8FFFFF, FF000000, 00000000] test_vsldoi_1505_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vsldoi_1506_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [08101080, 8F00007F, FFFFFF8F, FFFFFF00] test_vsldoi_1507_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [1010808F, 00007FFF, FFFF8FFF, FFFF0000] test_vsldoi_1508_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [007FFFFF, FF8FFFFF, FF000000, 01000000] test_vsldoi_1509_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vsldoi_1510_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [08101080, 8F00007F, FFFFFF8F, FFFFFF00] test_vsldoi_1511_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [1010808F, 00007FFF, FFFF8FFF, FFFF0000] test_vsldoi_1512_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [007FFFFF, FF8FFFFF, FF0000FF, FFFFFF00] test_vsldoi_1513_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vsldoi_1514_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [08101080, 8F00007F, FFFFFF8F, FFFFFF00] test_vsldoi_1515_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [1010808F, 00007FFF, FFFF8FFF, FFFF0001] test_vsldoi_1516_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [007FFFFF, FF8FFFFF, FF000102, 03040506] test_vsldoi_1517_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vsldoi_1518_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [08101080, 8F00007F, FFFFFF8F, FFFFFF00] test_vsldoi_1519_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [1010808F, 00007FFF, FFFF8FFF, FFFF000D] test_vsldoi_1520_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [007FFFFF, FF8FFFFF, FF000D00, 0D000D00] test_vsldoi_1521_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vsldoi_1522_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [08101080, 8F00007F, FFFFFF8F, FFFFFF00] test_vsldoi_1523_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [1010808F, 00007FFF, FFFF8FFF, FFFF0011] test_vsldoi_1524_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [007FFFFF, FF8FFFFF, FF001122, 33445566] test_vsldoi_1525_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vsldoi_1526_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [08101080, 8F00007F, FFFFFF8F, FFFFFF00] test_vsldoi_1527_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [1010808F, 00007FFF, FFFF8FFF, FFFF00FF] test_vsldoi_1528_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [007FFFFF, FF8FFFFF, FF00FFFF, 000000FF] test_vsldoi_1529_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vsldoi_1530_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [08101080, 8F00007F, FFFFFF8F, FFFFFF04] test_vsldoi_1531_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [1010808F, 00007FFF, FFFF8FFF, FFFF0404] test_vsldoi_1532_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [007FFFFF, FF8FFFFF, FF040404, 04040404] test_vsldoi_1533_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vsldoi_1534_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [08101080, 8F00007F, FFFFFF8F, FFFFFF07] test_vsldoi_1535_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [1010808F, 00007FFF, FFFF8FFF, FFFF0707] test_vsldoi_1536_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [007FFFFF, FF8FFFFF, FF070707, 07070707] test_vsldoi_1537_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vsldoi_1538_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [08101080, 8F00007F, FFFFFF8F, FFFFFF08] test_vsldoi_1539_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [1010808F, 00007FFF, FFFF8FFF, FFFF0808] test_vsldoi_1540_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [007FFFFF, FF8FFFFF, FF080808, 08080808] test_vsldoi_1541_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vsldoi_1542_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [08101080, 8F00007F, FFFFFF8F, FFFFFF12] test_vsldoi_1543_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [1010808F, 00007FFF, FFFF8FFF, FFFF1212] test_vsldoi_1544_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [007FFFFF, FF8FFFFF, FF121212, 12121212] test_vsldoi_1545_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vsldoi_1546_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [08101080, 8F00007F, FFFFFF8F, FFFFFF12] test_vsldoi_1547_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [1010808F, 00007FFF, FFFF8FFF, FFFF1234] test_vsldoi_1548_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [007FFFFF, FF8FFFFF, FF123456, 78876543] test_vsldoi_1549_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vsldoi_1550_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [08101080, 8F00007F, FFFFFF8F, FFFFFF3F] test_vsldoi_1551_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [1010808F, 00007FFF, FFFF8FFF, FFFF3F80] test_vsldoi_1552_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [007FFFFF, FF8FFFFF, FF3F8000, 003FC000] test_vsldoi_1553_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vsldoi_1554_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [08101080, 8F00007F, FFFFFF8F, FFFFFF41] test_vsldoi_1555_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [1010808F, 00007FFF, FFFF8FFF, FFFF4120] test_vsldoi_1556_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [007FFFFF, FF8FFFFF, FF412000, 00C12000] test_vsldoi_1557_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vsldoi_1558_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [08101080, 8F00007F, FFFFFF8F, FFFFFF7F] test_vsldoi_1559_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [1010808F, 00007FFF, FFFF8FFF, FFFF7F80] test_vsldoi_1560_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [007FFFFF, FF8FFFFF, FF7F8002, 03040506] test_vsldoi_1561_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vsldoi_1562_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [08101080, 8F00007F, FFFFFF8F, FFFFFFBF] test_vsldoi_1563_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [1010808F, 00007FFF, FFFF8FFF, FFFFBF80] test_vsldoi_1564_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [007FFFFF, FF8FFFFF, FFBF8000, 00BFC000] test_vsldoi_1565_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vsldoi_1566_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [08101080, 8F00007F, FFFFFF8F, FFFFFFC1] test_vsldoi_1567_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [1010808F, 00007FFF, FFFF8FFF, FFFFC120] test_vsldoi_1568_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [007FFFFF, FF8FFFFF, FFC12000, 0041A000] test_vsldoi_1569_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vsldoi_1570_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [08101080, 8F00007F, FFFFFF8F, FFFFFFCD] test_vsldoi_1571_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [1010808F, 00007FFF, FFFF8FFF, FFFFCDCD] test_vsldoi_1572_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [007FFFFF, FF8FFFFF, FFCDCDCD, CDCDCDCD] test_vsldoi_1573_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vsldoi_1574_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [08101080, 8F00007F, FFFFFF8F, FFFFFFF8] test_vsldoi_1575_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [1010808F, 00007FFF, FFFF8FFF, FFFFF8F9] test_vsldoi_1576_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [007FFFFF, FF8FFFFF, FFF8F9FA, FBFCFDFE] test_vsldoi_1577_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vsldoi_1578_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [08101080, 8F00007F, FFFFFF8F, FFFFFFFE] test_vsldoi_1579_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [1010808F, 00007FFF, FFFF8FFF, FFFFFEFE] test_vsldoi_1580_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [007FFFFF, FF8FFFFF, FFFEFEFE, FEFEFEFE] test_vsldoi_1581_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vsldoi_1582_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [08101080, 8F00007F, FFFFFF8F, FFFFFFFF] test_vsldoi_1583_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [1010808F, 00007FFF, FFFF8FFF, FFFFFFFC] test_vsldoi_1584_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [007FFFFF, FF8FFFFF, FFFFFCFF, FDFFFEFF] test_vsldoi_1585_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vsldoi_1586_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [08101080, 8F00007F, FFFFFF8F, FFFFFFFF] test_vsldoi_1587_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [1010808F, 00007FFF, FFFF8FFF, FFFFFFFD] test_vsldoi_1588_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [007FFFFF, FF8FFFFF, FFFFFDFF, 7E000200] test_vsldoi_1589_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vsldoi_1590_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [08101080, 8F00007F, FFFFFF8F, FFFFFFFF] test_vsldoi_1591_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [1010808F, 00007FFF, FFFF8FFF, FFFFFFFF] test_vsldoi_1592_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [007FFFFF, FF8FFFFF, FFFFFF01, 017070FF] test_vsldoi_1593_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vsldoi_1594_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [08101080, 8F00007F, FFFFFF8F, FFFFFFFF] test_vsldoi_1595_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [1010808F, 00007FFF, FFFF8FFF, FFFFFFFF] test_vsldoi_1596_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [007FFFFF, FF8FFFFF, FFFFFFFF, 80000000] test_vsldoi_1597_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vsldoi_1598_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [08101080, 8F00007F, FFFFFF8F, FFFFFFFF] test_vsldoi_1599_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [1010808F, 00007FFF, FFFF8FFF, FFFFFFFF] test_vsldoi_1600_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [007FFFFF, FF8FFFFF, FFFFFFFF, FFFFFFFF] test_vsldoi_1601_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vsldoi_1602_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [800000BF, C00000BF, 8CCCCDBF, F3333300] test_vsldoi_1603_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [0000BFC0, 0000BF8C, CCCDBFF3, 33330000] test_vsldoi_1604_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00BF8CCC, CDBFF333, 33000000, 00000000] test_vsldoi_1605_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vsldoi_1606_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [800000BF, C00000BF, 8CCCCDBF, F3333300] test_vsldoi_1607_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [0000BFC0, 0000BF8C, CCCDBFF3, 33330000] test_vsldoi_1608_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00BF8CCC, CDBFF333, 33000000, 01000000] test_vsldoi_1609_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vsldoi_1610_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [800000BF, C00000BF, 8CCCCDBF, F3333300] test_vsldoi_1611_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [0000BFC0, 0000BF8C, CCCDBFF3, 33330000] test_vsldoi_1612_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00BF8CCC, CDBFF333, 330000FF, FFFFFF00] test_vsldoi_1613_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vsldoi_1614_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [800000BF, C00000BF, 8CCCCDBF, F3333300] test_vsldoi_1615_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [0000BFC0, 0000BF8C, CCCDBFF3, 33330001] test_vsldoi_1616_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00BF8CCC, CDBFF333, 33000102, 03040506] test_vsldoi_1617_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vsldoi_1618_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [800000BF, C00000BF, 8CCCCDBF, F3333300] test_vsldoi_1619_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [0000BFC0, 0000BF8C, CCCDBFF3, 3333000D] test_vsldoi_1620_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00BF8CCC, CDBFF333, 33000D00, 0D000D00] test_vsldoi_1621_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vsldoi_1622_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [800000BF, C00000BF, 8CCCCDBF, F3333300] test_vsldoi_1623_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [0000BFC0, 0000BF8C, CCCDBFF3, 33330011] test_vsldoi_1624_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00BF8CCC, CDBFF333, 33001122, 33445566] test_vsldoi_1625_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vsldoi_1626_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [800000BF, C00000BF, 8CCCCDBF, F3333300] test_vsldoi_1627_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [0000BFC0, 0000BF8C, CCCDBFF3, 333300FF] test_vsldoi_1628_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00BF8CCC, CDBFF333, 3300FFFF, 000000FF] test_vsldoi_1629_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vsldoi_1630_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [800000BF, C00000BF, 8CCCCDBF, F3333304] test_vsldoi_1631_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [0000BFC0, 0000BF8C, CCCDBFF3, 33330404] test_vsldoi_1632_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00BF8CCC, CDBFF333, 33040404, 04040404] test_vsldoi_1633_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vsldoi_1634_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [800000BF, C00000BF, 8CCCCDBF, F3333307] test_vsldoi_1635_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [0000BFC0, 0000BF8C, CCCDBFF3, 33330707] test_vsldoi_1636_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00BF8CCC, CDBFF333, 33070707, 07070707] test_vsldoi_1637_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vsldoi_1638_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [800000BF, C00000BF, 8CCCCDBF, F3333308] test_vsldoi_1639_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [0000BFC0, 0000BF8C, CCCDBFF3, 33330808] test_vsldoi_1640_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00BF8CCC, CDBFF333, 33080808, 08080808] test_vsldoi_1641_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vsldoi_1642_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [800000BF, C00000BF, 8CCCCDBF, F3333312] test_vsldoi_1643_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [0000BFC0, 0000BF8C, CCCDBFF3, 33331212] test_vsldoi_1644_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00BF8CCC, CDBFF333, 33121212, 12121212] test_vsldoi_1645_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vsldoi_1646_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [800000BF, C00000BF, 8CCCCDBF, F3333312] test_vsldoi_1647_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [0000BFC0, 0000BF8C, CCCDBFF3, 33331234] test_vsldoi_1648_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00BF8CCC, CDBFF333, 33123456, 78876543] test_vsldoi_1649_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vsldoi_1650_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [800000BF, C00000BF, 8CCCCDBF, F333333F] test_vsldoi_1651_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [0000BFC0, 0000BF8C, CCCDBFF3, 33333F80] test_vsldoi_1652_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [00BF8CCC, CDBFF333, 333F8000, 003FC000] test_vsldoi_1653_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vsldoi_1654_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [800000BF, C00000BF, 8CCCCDBF, F3333341] test_vsldoi_1655_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [0000BFC0, 0000BF8C, CCCDBFF3, 33334120] test_vsldoi_1656_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [00BF8CCC, CDBFF333, 33412000, 00C12000] test_vsldoi_1657_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vsldoi_1658_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [800000BF, C00000BF, 8CCCCDBF, F333337F] test_vsldoi_1659_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [0000BFC0, 0000BF8C, CCCDBFF3, 33337F80] test_vsldoi_1660_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00BF8CCC, CDBFF333, 337F8002, 03040506] test_vsldoi_1661_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vsldoi_1662_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [800000BF, C00000BF, 8CCCCDBF, F3333380] test_vsldoi_1663_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [0000BFC0, 0000BF8C, CCCDBFF3, 33338008] test_vsldoi_1664_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [00BF8CCC, CDBFF333, 33800810, 10808F00] test_vsldoi_1665_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vsldoi_1666_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [800000BF, C00000BF, 8CCCCDBF, F33333C1] test_vsldoi_1667_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [0000BFC0, 0000BF8C, CCCDBFF3, 3333C120] test_vsldoi_1668_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [00BF8CCC, CDBFF333, 33C12000, 0041A000] test_vsldoi_1669_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vsldoi_1670_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [800000BF, C00000BF, 8CCCCDBF, F33333CD] test_vsldoi_1671_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [0000BFC0, 0000BF8C, CCCDBFF3, 3333CDCD] test_vsldoi_1672_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [00BF8CCC, CDBFF333, 33CDCDCD, CDCDCDCD] test_vsldoi_1673_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vsldoi_1674_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [800000BF, C00000BF, 8CCCCDBF, F33333F8] test_vsldoi_1675_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [0000BFC0, 0000BF8C, CCCDBFF3, 3333F8F9] test_vsldoi_1676_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [00BF8CCC, CDBFF333, 33F8F9FA, FBFCFDFE] test_vsldoi_1677_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vsldoi_1678_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [800000BF, C00000BF, 8CCCCDBF, F33333FE] test_vsldoi_1679_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [0000BFC0, 0000BF8C, CCCDBFF3, 3333FEFE] test_vsldoi_1680_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [00BF8CCC, CDBFF333, 33FEFEFE, FEFEFEFE] test_vsldoi_1681_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vsldoi_1682_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [800000BF, C00000BF, 8CCCCDBF, F33333FF] test_vsldoi_1683_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [0000BFC0, 0000BF8C, CCCDBFF3, 3333FFFC] test_vsldoi_1684_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [00BF8CCC, CDBFF333, 33FFFCFF, FDFFFEFF] test_vsldoi_1685_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vsldoi_1686_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [800000BF, C00000BF, 8CCCCDBF, F33333FF] test_vsldoi_1687_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [0000BFC0, 0000BF8C, CCCDBFF3, 3333FFFD] test_vsldoi_1688_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [00BF8CCC, CDBFF333, 33FFFDFF, 7E000200] test_vsldoi_1689_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vsldoi_1690_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [800000BF, C00000BF, 8CCCCDBF, F33333FF] test_vsldoi_1691_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [0000BFC0, 0000BF8C, CCCDBFF3, 3333FFFF] test_vsldoi_1692_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [00BF8CCC, CDBFF333, 33FFFF01, 017070FF] test_vsldoi_1693_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vsldoi_1694_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [800000BF, C00000BF, 8CCCCDBF, F33333FF] test_vsldoi_1695_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [0000BFC0, 0000BF8C, CCCDBFF3, 3333FFFF] test_vsldoi_1696_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [00BF8CCC, CDBFF333, 33FFFFFF, 80000000] test_vsldoi_1697_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vsldoi_1698_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [800000BF, C00000BF, 8CCCCDBF, F33333FF] test_vsldoi_1699_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [0000BFC0, 0000BF8C, CCCDBFF3, 3333FFFF] test_vsldoi_1700_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [00BF8CCC, CDBFF333, 33FFFFFF, FFFFFFFF] test_vsldoi_1701_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000] test_vsldoi_1702_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [20000041, A00000C1, A0000041, F0000000] test_vsldoi_1703_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [000041A0, 0000C1A0, 000041F0, 00000000] test_vsldoi_1704_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00C1A000, 0041F000, 00000000, 00000000] test_vsldoi_1705_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000] test_vsldoi_1706_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [20000041, A00000C1, A0000041, F0000000] test_vsldoi_1707_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [000041A0, 0000C1A0, 000041F0, 00000000] test_vsldoi_1708_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00C1A000, 0041F000, 00000000, 01000000] test_vsldoi_1709_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000] test_vsldoi_1710_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [20000041, A00000C1, A0000041, F0000000] test_vsldoi_1711_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [000041A0, 0000C1A0, 000041F0, 00000000] test_vsldoi_1712_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00C1A000, 0041F000, 000000FF, FFFFFF00] test_vsldoi_1713_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000] test_vsldoi_1714_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [20000041, A00000C1, A0000041, F0000000] test_vsldoi_1715_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [000041A0, 0000C1A0, 000041F0, 00000001] test_vsldoi_1716_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00C1A000, 0041F000, 00000102, 03040506] test_vsldoi_1717_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000] test_vsldoi_1718_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [20000041, A00000C1, A0000041, F0000000] test_vsldoi_1719_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [000041A0, 0000C1A0, 000041F0, 0000000D] test_vsldoi_1720_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00C1A000, 0041F000, 00000D00, 0D000D00] test_vsldoi_1721_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000] test_vsldoi_1722_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [20000041, A00000C1, A0000041, F0000000] test_vsldoi_1723_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [000041A0, 0000C1A0, 000041F0, 00000011] test_vsldoi_1724_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00C1A000, 0041F000, 00001122, 33445566] test_vsldoi_1725_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000] test_vsldoi_1726_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [20000041, A00000C1, A0000041, F0000000] test_vsldoi_1727_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [000041A0, 0000C1A0, 000041F0, 000000FF] test_vsldoi_1728_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00C1A000, 0041F000, 0000FFFF, 000000FF] test_vsldoi_1729_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000] test_vsldoi_1730_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [20000041, A00000C1, A0000041, F0000004] test_vsldoi_1731_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [000041A0, 0000C1A0, 000041F0, 00000404] test_vsldoi_1732_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00C1A000, 0041F000, 00040404, 04040404] test_vsldoi_1733_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000] test_vsldoi_1734_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [20000041, A00000C1, A0000041, F0000007] test_vsldoi_1735_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [000041A0, 0000C1A0, 000041F0, 00000707] test_vsldoi_1736_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00C1A000, 0041F000, 00070707, 07070707] test_vsldoi_1737_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000] test_vsldoi_1738_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [20000041, A00000C1, A0000041, F0000008] test_vsldoi_1739_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [000041A0, 0000C1A0, 000041F0, 00000808] test_vsldoi_1740_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00C1A000, 0041F000, 00080808, 08080808] test_vsldoi_1741_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000] test_vsldoi_1742_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [20000041, A00000C1, A0000041, F0000012] test_vsldoi_1743_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [000041A0, 0000C1A0, 000041F0, 00001212] test_vsldoi_1744_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00C1A000, 0041F000, 00121212, 12121212] test_vsldoi_1745_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000] test_vsldoi_1746_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [20000041, A00000C1, A0000041, F0000012] test_vsldoi_1747_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [000041A0, 0000C1A0, 000041F0, 00001234] test_vsldoi_1748_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00C1A000, 0041F000, 00123456, 78876543] test_vsldoi_1749_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000] test_vsldoi_1750_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [20000041, A00000C1, A0000041, F000003F] test_vsldoi_1751_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [000041A0, 0000C1A0, 000041F0, 00003F80] test_vsldoi_1752_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [00C1A000, 0041F000, 003F8000, 003FC000] test_vsldoi_1753_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000] test_vsldoi_1754_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [20000041, A00000C1, A0000041, F0000041] test_vsldoi_1755_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [000041A0, 0000C1A0, 000041F0, 00004120] test_vsldoi_1756_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [00C1A000, 0041F000, 00412000, 00C12000] test_vsldoi_1757_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000] test_vsldoi_1758_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [20000041, A00000C1, A0000041, F000007F] test_vsldoi_1759_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [000041A0, 0000C1A0, 000041F0, 00007F80] test_vsldoi_1760_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00C1A000, 0041F000, 007F8002, 03040506] test_vsldoi_1761_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000] test_vsldoi_1762_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [20000041, A00000C1, A0000041, F0000080] test_vsldoi_1763_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [000041A0, 0000C1A0, 000041F0, 00008008] test_vsldoi_1764_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [00C1A000, 0041F000, 00800810, 10808F00] test_vsldoi_1765_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000] test_vsldoi_1766_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [20000041, A00000C1, A0000041, F00000BF] test_vsldoi_1767_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [000041A0, 0000C1A0, 000041F0, 0000BF80] test_vsldoi_1768_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [00C1A000, 0041F000, 00BF8000, 00BFC000] test_vsldoi_1769_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000] test_vsldoi_1770_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [20000041, A00000C1, A0000041, F00000CD] test_vsldoi_1771_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [000041A0, 0000C1A0, 000041F0, 0000CDCD] test_vsldoi_1772_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [00C1A000, 0041F000, 00CDCDCD, CDCDCDCD] test_vsldoi_1773_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000] test_vsldoi_1774_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [20000041, A00000C1, A0000041, F00000F8] test_vsldoi_1775_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [000041A0, 0000C1A0, 000041F0, 0000F8F9] test_vsldoi_1776_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [00C1A000, 0041F000, 00F8F9FA, FBFCFDFE] test_vsldoi_1777_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000] test_vsldoi_1778_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [20000041, A00000C1, A0000041, F00000FE] test_vsldoi_1779_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [000041A0, 0000C1A0, 000041F0, 0000FEFE] test_vsldoi_1780_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [00C1A000, 0041F000, 00FEFEFE, FEFEFEFE] test_vsldoi_1781_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000] test_vsldoi_1782_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [20000041, A00000C1, A0000041, F00000FF] test_vsldoi_1783_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [000041A0, 0000C1A0, 000041F0, 0000FFFC] test_vsldoi_1784_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [00C1A000, 0041F000, 00FFFCFF, FDFFFEFF] test_vsldoi_1785_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000] test_vsldoi_1786_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [20000041, A00000C1, A0000041, F00000FF] test_vsldoi_1787_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [000041A0, 0000C1A0, 000041F0, 0000FFFD] test_vsldoi_1788_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [00C1A000, 0041F000, 00FFFDFF, 7E000200] test_vsldoi_1789_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000] test_vsldoi_1790_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [20000041, A00000C1, A0000041, F00000FF] test_vsldoi_1791_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [000041A0, 0000C1A0, 000041F0, 0000FFFF] test_vsldoi_1792_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [00C1A000, 0041F000, 00FFFF01, 017070FF] test_vsldoi_1793_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000] test_vsldoi_1794_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [20000041, A00000C1, A0000041, F00000FF] test_vsldoi_1795_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [000041A0, 0000C1A0, 000041F0, 0000FFFF] test_vsldoi_1796_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [00C1A000, 0041F000, 00FFFFFF, 80000000] test_vsldoi_1797_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000] test_vsldoi_1798_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [20000041, A00000C1, A0000041, F00000FF] test_vsldoi_1799_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [000041A0, 0000C1A0, 000041F0, 0000FFFF] test_vsldoi_1800_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [00C1A000, 0041F000, 00FFFFFF, FFFFFFFF] test_vsldoi_1801_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vsldoi_1802_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCD04, 01020300] test_vsldoi_1803_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCD0401, 02030000] test_vsldoi_1804_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [CDCDCDCD, CD040102, 03000000, 00000000] test_vsldoi_1805_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vsldoi_1806_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCD04, 01020300] test_vsldoi_1807_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCD0401, 02030000] test_vsldoi_1808_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [CDCDCDCD, CD040102, 03000000, 01000000] test_vsldoi_1809_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vsldoi_1810_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCD04, 01020300] test_vsldoi_1811_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCD0401, 02030000] test_vsldoi_1812_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [CDCDCDCD, CD040102, 030000FF, FFFFFF00] test_vsldoi_1813_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vsldoi_1814_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCD04, 01020300] test_vsldoi_1815_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCD0401, 02030001] test_vsldoi_1816_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [CDCDCDCD, CD040102, 03000102, 03040506] test_vsldoi_1817_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vsldoi_1818_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCD04, 01020300] test_vsldoi_1819_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCD0401, 0203000D] test_vsldoi_1820_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [CDCDCDCD, CD040102, 03000D00, 0D000D00] test_vsldoi_1821_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vsldoi_1822_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCD04, 01020300] test_vsldoi_1823_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCD0401, 02030011] test_vsldoi_1824_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [CDCDCDCD, CD040102, 03001122, 33445566] test_vsldoi_1825_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vsldoi_1826_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCD04, 01020300] test_vsldoi_1827_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCD0401, 020300FF] test_vsldoi_1828_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [CDCDCDCD, CD040102, 0300FFFF, 000000FF] test_vsldoi_1829_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vsldoi_1830_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCD04, 01020304] test_vsldoi_1831_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCD0401, 02030404] test_vsldoi_1832_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [CDCDCDCD, CD040102, 03040404, 04040404] test_vsldoi_1833_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vsldoi_1834_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCD04, 01020307] test_vsldoi_1835_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCD0401, 02030707] test_vsldoi_1836_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [CDCDCDCD, CD040102, 03070707, 07070707] test_vsldoi_1837_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vsldoi_1838_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCD04, 01020308] test_vsldoi_1839_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCD0401, 02030808] test_vsldoi_1840_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [CDCDCDCD, CD040102, 03080808, 08080808] test_vsldoi_1841_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vsldoi_1842_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCD04, 01020312] test_vsldoi_1843_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCD0401, 02031212] test_vsldoi_1844_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [CDCDCDCD, CD040102, 03121212, 12121212] test_vsldoi_1845_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vsldoi_1846_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCD04, 01020312] test_vsldoi_1847_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCD0401, 02031234] test_vsldoi_1848_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [CDCDCDCD, CD040102, 03123456, 78876543] test_vsldoi_1849_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vsldoi_1850_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCD04, 0102033F] test_vsldoi_1851_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCD0401, 02033F80] test_vsldoi_1852_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [CDCDCDCD, CD040102, 033F8000, 003FC000] test_vsldoi_1853_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vsldoi_1854_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCD04, 01020341] test_vsldoi_1855_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCD0401, 02034120] test_vsldoi_1856_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [CDCDCDCD, CD040102, 03412000, 00C12000] test_vsldoi_1857_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vsldoi_1858_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCD04, 0102037F] test_vsldoi_1859_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCD0401, 02037F80] test_vsldoi_1860_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [CDCDCDCD, CD040102, 037F8002, 03040506] test_vsldoi_1861_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vsldoi_1862_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCD04, 01020380] test_vsldoi_1863_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCD0401, 02038008] test_vsldoi_1864_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [CDCDCDCD, CD040102, 03800810, 10808F00] test_vsldoi_1865_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vsldoi_1866_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCD04, 010203BF] test_vsldoi_1867_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCD0401, 0203BF80] test_vsldoi_1868_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [CDCDCDCD, CD040102, 03BF8000, 00BFC000] test_vsldoi_1869_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vsldoi_1870_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCD04, 010203C1] test_vsldoi_1871_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCD0401, 0203C120] test_vsldoi_1872_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [CDCDCDCD, CD040102, 03C12000, 0041A000] test_vsldoi_1873_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vsldoi_1874_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCD04, 010203F8] test_vsldoi_1875_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCD0401, 0203F8F9] test_vsldoi_1876_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [CDCDCDCD, CD040102, 03F8F9FA, FBFCFDFE] test_vsldoi_1877_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vsldoi_1878_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCD04, 010203FE] test_vsldoi_1879_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCD0401, 0203FEFE] test_vsldoi_1880_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [CDCDCDCD, CD040102, 03FEFEFE, FEFEFEFE] test_vsldoi_1881_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vsldoi_1882_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCD04, 010203FF] test_vsldoi_1883_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCD0401, 0203FFFC] test_vsldoi_1884_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [CDCDCDCD, CD040102, 03FFFCFF, FDFFFEFF] test_vsldoi_1885_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vsldoi_1886_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCD04, 010203FF] test_vsldoi_1887_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCD0401, 0203FFFD] test_vsldoi_1888_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [CDCDCDCD, CD040102, 03FFFDFF, 7E000200] test_vsldoi_1889_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vsldoi_1890_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCD04, 010203FF] test_vsldoi_1891_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCD0401, 0203FFFF] test_vsldoi_1892_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [CDCDCDCD, CD040102, 03FFFF01, 017070FF] test_vsldoi_1893_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vsldoi_1894_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCD04, 010203FF] test_vsldoi_1895_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCD0401, 0203FFFF] test_vsldoi_1896_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [CDCDCDCD, CD040102, 03FFFFFF, 80000000] test_vsldoi_1897_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vsldoi_1898_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCD04, 010203FF] test_vsldoi_1899_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCD0401, 0203FFFF] test_vsldoi_1900_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [CDCDCDCD, CD040102, 03FFFFFF, FFFFFFFF] test_vsldoi_1901_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vsldoi_1902_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [F9FAFBFC, FDFEFF00, 01020304, 05060700] test_vsldoi_1903_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FAFBFCFD, FEFF0001, 02030405, 06070000] test_vsldoi_1904_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FF000102, 03040506, 07000000, 00000000] test_vsldoi_1905_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vsldoi_1906_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [F9FAFBFC, FDFEFF00, 01020304, 05060700] test_vsldoi_1907_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FAFBFCFD, FEFF0001, 02030405, 06070000] test_vsldoi_1908_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FF000102, 03040506, 07000000, 01000000] test_vsldoi_1909_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vsldoi_1910_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [F9FAFBFC, FDFEFF00, 01020304, 05060700] test_vsldoi_1911_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FAFBFCFD, FEFF0001, 02030405, 06070000] test_vsldoi_1912_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FF000102, 03040506, 070000FF, FFFFFF00] test_vsldoi_1913_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vsldoi_1914_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [F9FAFBFC, FDFEFF00, 01020304, 05060700] test_vsldoi_1915_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FAFBFCFD, FEFF0001, 02030405, 06070001] test_vsldoi_1916_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FF000102, 03040506, 07000102, 03040506] test_vsldoi_1917_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vsldoi_1918_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [F9FAFBFC, FDFEFF00, 01020304, 05060700] test_vsldoi_1919_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FAFBFCFD, FEFF0001, 02030405, 0607000D] test_vsldoi_1920_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FF000102, 03040506, 07000D00, 0D000D00] test_vsldoi_1921_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vsldoi_1922_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [F9FAFBFC, FDFEFF00, 01020304, 05060700] test_vsldoi_1923_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FAFBFCFD, FEFF0001, 02030405, 06070011] test_vsldoi_1924_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FF000102, 03040506, 07001122, 33445566] test_vsldoi_1925_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vsldoi_1926_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [F9FAFBFC, FDFEFF00, 01020304, 05060700] test_vsldoi_1927_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FAFBFCFD, FEFF0001, 02030405, 060700FF] test_vsldoi_1928_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FF000102, 03040506, 0700FFFF, 000000FF] test_vsldoi_1929_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vsldoi_1930_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [F9FAFBFC, FDFEFF00, 01020304, 05060704] test_vsldoi_1931_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FAFBFCFD, FEFF0001, 02030405, 06070404] test_vsldoi_1932_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FF000102, 03040506, 07040404, 04040404] test_vsldoi_1933_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vsldoi_1934_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [F9FAFBFC, FDFEFF00, 01020304, 05060707] test_vsldoi_1935_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FAFBFCFD, FEFF0001, 02030405, 06070707] test_vsldoi_1936_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FF000102, 03040506, 07070707, 07070707] test_vsldoi_1937_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vsldoi_1938_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [F9FAFBFC, FDFEFF00, 01020304, 05060708] test_vsldoi_1939_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FAFBFCFD, FEFF0001, 02030405, 06070808] test_vsldoi_1940_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FF000102, 03040506, 07080808, 08080808] test_vsldoi_1941_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vsldoi_1942_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [F9FAFBFC, FDFEFF00, 01020304, 05060712] test_vsldoi_1943_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FAFBFCFD, FEFF0001, 02030405, 06071212] test_vsldoi_1944_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FF000102, 03040506, 07121212, 12121212] test_vsldoi_1945_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vsldoi_1946_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [F9FAFBFC, FDFEFF00, 01020304, 05060712] test_vsldoi_1947_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FAFBFCFD, FEFF0001, 02030405, 06071234] test_vsldoi_1948_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FF000102, 03040506, 07123456, 78876543] test_vsldoi_1949_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vsldoi_1950_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [F9FAFBFC, FDFEFF00, 01020304, 0506073F] test_vsldoi_1951_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FAFBFCFD, FEFF0001, 02030405, 06073F80] test_vsldoi_1952_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FF000102, 03040506, 073F8000, 003FC000] test_vsldoi_1953_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vsldoi_1954_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [F9FAFBFC, FDFEFF00, 01020304, 05060741] test_vsldoi_1955_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FAFBFCFD, FEFF0001, 02030405, 06074120] test_vsldoi_1956_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FF000102, 03040506, 07412000, 00C12000] test_vsldoi_1957_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vsldoi_1958_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [F9FAFBFC, FDFEFF00, 01020304, 0506077F] test_vsldoi_1959_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FAFBFCFD, FEFF0001, 02030405, 06077F80] test_vsldoi_1960_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FF000102, 03040506, 077F8002, 03040506] test_vsldoi_1961_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vsldoi_1962_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [F9FAFBFC, FDFEFF00, 01020304, 05060780] test_vsldoi_1963_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [FAFBFCFD, FEFF0001, 02030405, 06078008] test_vsldoi_1964_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [FF000102, 03040506, 07800810, 10808F00] test_vsldoi_1965_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vsldoi_1966_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [F9FAFBFC, FDFEFF00, 01020304, 050607BF] test_vsldoi_1967_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [FAFBFCFD, FEFF0001, 02030405, 0607BF80] test_vsldoi_1968_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [FF000102, 03040506, 07BF8000, 00BFC000] test_vsldoi_1969_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vsldoi_1970_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [F9FAFBFC, FDFEFF00, 01020304, 050607C1] test_vsldoi_1971_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [FAFBFCFD, FEFF0001, 02030405, 0607C120] test_vsldoi_1972_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [FF000102, 03040506, 07C12000, 0041A000] test_vsldoi_1973_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vsldoi_1974_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [F9FAFBFC, FDFEFF00, 01020304, 050607CD] test_vsldoi_1975_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [FAFBFCFD, FEFF0001, 02030405, 0607CDCD] test_vsldoi_1976_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [FF000102, 03040506, 07CDCDCD, CDCDCDCD] test_vsldoi_1977_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vsldoi_1978_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [F9FAFBFC, FDFEFF00, 01020304, 050607FE] test_vsldoi_1979_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FAFBFCFD, FEFF0001, 02030405, 0607FEFE] test_vsldoi_1980_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FF000102, 03040506, 07FEFEFE, FEFEFEFE] test_vsldoi_1981_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vsldoi_1982_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [F9FAFBFC, FDFEFF00, 01020304, 050607FF] test_vsldoi_1983_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FAFBFCFD, FEFF0001, 02030405, 0607FFFC] test_vsldoi_1984_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FF000102, 03040506, 07FFFCFF, FDFFFEFF] test_vsldoi_1985_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vsldoi_1986_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [F9FAFBFC, FDFEFF00, 01020304, 050607FF] test_vsldoi_1987_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FAFBFCFD, FEFF0001, 02030405, 0607FFFD] test_vsldoi_1988_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FF000102, 03040506, 07FFFDFF, 7E000200] test_vsldoi_1989_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vsldoi_1990_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [F9FAFBFC, FDFEFF00, 01020304, 050607FF] test_vsldoi_1991_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FAFBFCFD, FEFF0001, 02030405, 0607FFFF] test_vsldoi_1992_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FF000102, 03040506, 07FFFF01, 017070FF] test_vsldoi_1993_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vsldoi_1994_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [F9FAFBFC, FDFEFF00, 01020304, 050607FF] test_vsldoi_1995_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FAFBFCFD, FEFF0001, 02030405, 0607FFFF] test_vsldoi_1996_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FF000102, 03040506, 07FFFFFF, 80000000] test_vsldoi_1997_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vsldoi_1998_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [F9FAFBFC, FDFEFF00, 01020304, 050607FF] test_vsldoi_1999_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FAFBFCFD, FEFF0001, 02030405, 0607FFFF] test_vsldoi_2000_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FF000102, 03040506, 07FFFFFF, FFFFFFFF] test_vsldoi_2001_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vsldoi_2002_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFE00] test_vsldoi_2003_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFE0000] test_vsldoi_2004_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FE000000, 00000000] test_vsldoi_2005_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vsldoi_2006_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFE00] test_vsldoi_2007_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFE0000] test_vsldoi_2008_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FE000000, 01000000] test_vsldoi_2009_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vsldoi_2010_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFE00] test_vsldoi_2011_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFE0000] test_vsldoi_2012_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FE0000FF, FFFFFF00] test_vsldoi_2013_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vsldoi_2014_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFE00] test_vsldoi_2015_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFE0001] test_vsldoi_2016_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FE000102, 03040506] test_vsldoi_2017_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vsldoi_2018_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFE00] test_vsldoi_2019_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFE000D] test_vsldoi_2020_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FE000D00, 0D000D00] test_vsldoi_2021_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vsldoi_2022_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFE00] test_vsldoi_2023_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFE0011] test_vsldoi_2024_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FE001122, 33445566] test_vsldoi_2025_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vsldoi_2026_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFE00] test_vsldoi_2027_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFE00FF] test_vsldoi_2028_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FE00FFFF, 000000FF] test_vsldoi_2029_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vsldoi_2030_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFE04] test_vsldoi_2031_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFE0404] test_vsldoi_2032_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FE040404, 04040404] test_vsldoi_2033_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vsldoi_2034_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFE07] test_vsldoi_2035_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFE0707] test_vsldoi_2036_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FE070707, 07070707] test_vsldoi_2037_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vsldoi_2038_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFE08] test_vsldoi_2039_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFE0808] test_vsldoi_2040_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FE080808, 08080808] test_vsldoi_2041_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vsldoi_2042_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFE12] test_vsldoi_2043_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFE1212] test_vsldoi_2044_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FE121212, 12121212] test_vsldoi_2045_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vsldoi_2046_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFE12] test_vsldoi_2047_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFE1234] test_vsldoi_2048_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FE123456, 78876543] test_vsldoi_2049_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vsldoi_2050_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFE3F] test_vsldoi_2051_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFE3F80] test_vsldoi_2052_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FE3F8000, 003FC000] test_vsldoi_2053_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vsldoi_2054_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFE41] test_vsldoi_2055_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFE4120] test_vsldoi_2056_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FE412000, 00C12000] test_vsldoi_2057_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vsldoi_2058_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFE7F] test_vsldoi_2059_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFE7F80] test_vsldoi_2060_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FE7F8002, 03040506] test_vsldoi_2061_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vsldoi_2062_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFE80] test_vsldoi_2063_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFE8008] test_vsldoi_2064_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FE800810, 10808F00] test_vsldoi_2065_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vsldoi_2066_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEBF] test_vsldoi_2067_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEBF80] test_vsldoi_2068_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEBF8000, 00BFC000] test_vsldoi_2069_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vsldoi_2070_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEC1] test_vsldoi_2071_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEC120] test_vsldoi_2072_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEC12000, 0041A000] test_vsldoi_2073_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vsldoi_2074_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFECD] test_vsldoi_2075_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFECDCD] test_vsldoi_2076_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FECDCDCD, CDCDCDCD] test_vsldoi_2077_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vsldoi_2078_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEF8] test_vsldoi_2079_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEF8F9] test_vsldoi_2080_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEF8F9FA, FBFCFDFE] test_vsldoi_2081_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vsldoi_2082_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFF] test_vsldoi_2083_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFFFC] test_vsldoi_2084_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFFFCFF, FDFFFEFF] test_vsldoi_2085_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vsldoi_2086_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFF] test_vsldoi_2087_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFFFD] test_vsldoi_2088_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFFFDFF, 7E000200] test_vsldoi_2089_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vsldoi_2090_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFF] test_vsldoi_2091_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFFFF] test_vsldoi_2092_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFFFF01, 017070FF] test_vsldoi_2093_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vsldoi_2094_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFF] test_vsldoi_2095_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFFFF] test_vsldoi_2096_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFFFFFF, 80000000] test_vsldoi_2097_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vsldoi_2098_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFF] test_vsldoi_2099_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFFFF] test_vsldoi_2100_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFFFFFF, FFFFFFFF] test_vsldoi_2101_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vsldoi_2102_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FCFFFDFF, FEFFFF00, 00000100, 02000300] test_vsldoi_2103_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FFFDFFFE, FFFF0000, 00010002, 00030000] test_vsldoi_2104_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FF000000, 01000200, 03000000, 00000000] test_vsldoi_2105_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vsldoi_2106_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FCFFFDFF, FEFFFF00, 00000100, 02000300] test_vsldoi_2107_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FFFDFFFE, FFFF0000, 00010002, 00030000] test_vsldoi_2108_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FF000000, 01000200, 03000000, 01000000] test_vsldoi_2109_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vsldoi_2110_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FCFFFDFF, FEFFFF00, 00000100, 02000300] test_vsldoi_2111_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FFFDFFFE, FFFF0000, 00010002, 00030000] test_vsldoi_2112_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FF000000, 01000200, 030000FF, FFFFFF00] test_vsldoi_2113_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vsldoi_2114_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FCFFFDFF, FEFFFF00, 00000100, 02000300] test_vsldoi_2115_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFDFFFE, FFFF0000, 00010002, 00030001] test_vsldoi_2116_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FF000000, 01000200, 03000102, 03040506] test_vsldoi_2117_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vsldoi_2118_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FCFFFDFF, FEFFFF00, 00000100, 02000300] test_vsldoi_2119_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FFFDFFFE, FFFF0000, 00010002, 0003000D] test_vsldoi_2120_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FF000000, 01000200, 03000D00, 0D000D00] test_vsldoi_2121_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vsldoi_2122_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FCFFFDFF, FEFFFF00, 00000100, 02000300] test_vsldoi_2123_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FFFDFFFE, FFFF0000, 00010002, 00030011] test_vsldoi_2124_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FF000000, 01000200, 03001122, 33445566] test_vsldoi_2125_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vsldoi_2126_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FCFFFDFF, FEFFFF00, 00000100, 02000300] test_vsldoi_2127_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FFFDFFFE, FFFF0000, 00010002, 000300FF] test_vsldoi_2128_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FF000000, 01000200, 0300FFFF, 000000FF] test_vsldoi_2129_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vsldoi_2130_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FCFFFDFF, FEFFFF00, 00000100, 02000304] test_vsldoi_2131_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FFFDFFFE, FFFF0000, 00010002, 00030404] test_vsldoi_2132_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FF000000, 01000200, 03040404, 04040404] test_vsldoi_2133_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vsldoi_2134_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FCFFFDFF, FEFFFF00, 00000100, 02000307] test_vsldoi_2135_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FFFDFFFE, FFFF0000, 00010002, 00030707] test_vsldoi_2136_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FF000000, 01000200, 03070707, 07070707] test_vsldoi_2137_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vsldoi_2138_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FCFFFDFF, FEFFFF00, 00000100, 02000308] test_vsldoi_2139_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FFFDFFFE, FFFF0000, 00010002, 00030808] test_vsldoi_2140_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FF000000, 01000200, 03080808, 08080808] test_vsldoi_2141_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vsldoi_2142_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FCFFFDFF, FEFFFF00, 00000100, 02000312] test_vsldoi_2143_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FFFDFFFE, FFFF0000, 00010002, 00031212] test_vsldoi_2144_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FF000000, 01000200, 03121212, 12121212] test_vsldoi_2145_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vsldoi_2146_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FCFFFDFF, FEFFFF00, 00000100, 02000312] test_vsldoi_2147_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FFFDFFFE, FFFF0000, 00010002, 00031234] test_vsldoi_2148_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FF000000, 01000200, 03123456, 78876543] test_vsldoi_2149_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vsldoi_2150_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FCFFFDFF, FEFFFF00, 00000100, 0200033F] test_vsldoi_2151_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FFFDFFFE, FFFF0000, 00010002, 00033F80] test_vsldoi_2152_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FF000000, 01000200, 033F8000, 003FC000] test_vsldoi_2153_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vsldoi_2154_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FCFFFDFF, FEFFFF00, 00000100, 02000341] test_vsldoi_2155_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FFFDFFFE, FFFF0000, 00010002, 00034120] test_vsldoi_2156_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FF000000, 01000200, 03412000, 00C12000] test_vsldoi_2157_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vsldoi_2158_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FCFFFDFF, FEFFFF00, 00000100, 0200037F] test_vsldoi_2159_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFDFFFE, FFFF0000, 00010002, 00037F80] test_vsldoi_2160_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FF000000, 01000200, 037F8002, 03040506] test_vsldoi_2161_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vsldoi_2162_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [FCFFFDFF, FEFFFF00, 00000100, 02000380] test_vsldoi_2163_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [FFFDFFFE, FFFF0000, 00010002, 00038008] test_vsldoi_2164_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [FF000000, 01000200, 03800810, 10808F00] test_vsldoi_2165_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vsldoi_2166_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [FCFFFDFF, FEFFFF00, 00000100, 020003BF] test_vsldoi_2167_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [FFFDFFFE, FFFF0000, 00010002, 0003BF80] test_vsldoi_2168_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [FF000000, 01000200, 03BF8000, 00BFC000] test_vsldoi_2169_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vsldoi_2170_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [FCFFFDFF, FEFFFF00, 00000100, 020003C1] test_vsldoi_2171_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [FFFDFFFE, FFFF0000, 00010002, 0003C120] test_vsldoi_2172_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [FF000000, 01000200, 03C12000, 0041A000] test_vsldoi_2173_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vsldoi_2174_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [FCFFFDFF, FEFFFF00, 00000100, 020003CD] test_vsldoi_2175_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [FFFDFFFE, FFFF0000, 00010002, 0003CDCD] test_vsldoi_2176_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [FF000000, 01000200, 03CDCDCD, CDCDCDCD] test_vsldoi_2177_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vsldoi_2178_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [FCFFFDFF, FEFFFF00, 00000100, 020003F8] test_vsldoi_2179_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [FFFDFFFE, FFFF0000, 00010002, 0003F8F9] test_vsldoi_2180_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [FF000000, 01000200, 03F8F9FA, FBFCFDFE] test_vsldoi_2181_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vsldoi_2182_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FCFFFDFF, FEFFFF00, 00000100, 020003FE] test_vsldoi_2183_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FFFDFFFE, FFFF0000, 00010002, 0003FEFE] test_vsldoi_2184_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FF000000, 01000200, 03FEFEFE, FEFEFEFE] test_vsldoi_2185_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vsldoi_2186_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FCFFFDFF, FEFFFF00, 00000100, 020003FF] test_vsldoi_2187_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFFFE, FFFF0000, 00010002, 0003FFFD] test_vsldoi_2188_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FF000000, 01000200, 03FFFDFF, 7E000200] test_vsldoi_2189_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vsldoi_2190_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FCFFFDFF, FEFFFF00, 00000100, 020003FF] test_vsldoi_2191_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFDFFFE, FFFF0000, 00010002, 0003FFFF] test_vsldoi_2192_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FF000000, 01000200, 03FFFF01, 017070FF] test_vsldoi_2193_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vsldoi_2194_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FCFFFDFF, FEFFFF00, 00000100, 020003FF] test_vsldoi_2195_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFDFFFE, FFFF0000, 00010002, 0003FFFF] test_vsldoi_2196_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FF000000, 01000200, 03FFFFFF, 80000000] test_vsldoi_2197_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vsldoi_2198_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FCFFFDFF, FEFFFF00, 00000100, 020003FF] test_vsldoi_2199_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFDFFFE, FFFF0000, 00010002, 0003FFFF] test_vsldoi_2200_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FF000000, 01000200, 03FFFFFF, FFFFFFFF] test_vsldoi_2201_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vsldoi_2202_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FDFF7E00, 020081FF, FCFF7D00, 03008200] test_vsldoi_2203_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FF7E0002, 0081FFFC, FF7D0003, 00820000] test_vsldoi_2204_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [81FFFCFF, 7D000300, 82000000, 00000000] test_vsldoi_2205_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vsldoi_2206_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FDFF7E00, 020081FF, FCFF7D00, 03008200] test_vsldoi_2207_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FF7E0002, 0081FFFC, FF7D0003, 00820000] test_vsldoi_2208_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [81FFFCFF, 7D000300, 82000000, 01000000] test_vsldoi_2209_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vsldoi_2210_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FDFF7E00, 020081FF, FCFF7D00, 03008200] test_vsldoi_2211_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FF7E0002, 0081FFFC, FF7D0003, 00820000] test_vsldoi_2212_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [81FFFCFF, 7D000300, 820000FF, FFFFFF00] test_vsldoi_2213_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vsldoi_2214_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FDFF7E00, 020081FF, FCFF7D00, 03008200] test_vsldoi_2215_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FF7E0002, 0081FFFC, FF7D0003, 00820001] test_vsldoi_2216_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [81FFFCFF, 7D000300, 82000102, 03040506] test_vsldoi_2217_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vsldoi_2218_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FDFF7E00, 020081FF, FCFF7D00, 03008200] test_vsldoi_2219_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FF7E0002, 0081FFFC, FF7D0003, 0082000D] test_vsldoi_2220_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [81FFFCFF, 7D000300, 82000D00, 0D000D00] test_vsldoi_2221_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vsldoi_2222_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FDFF7E00, 020081FF, FCFF7D00, 03008200] test_vsldoi_2223_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FF7E0002, 0081FFFC, FF7D0003, 00820011] test_vsldoi_2224_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [81FFFCFF, 7D000300, 82001122, 33445566] test_vsldoi_2225_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vsldoi_2226_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FDFF7E00, 020081FF, FCFF7D00, 03008200] test_vsldoi_2227_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FF7E0002, 0081FFFC, FF7D0003, 008200FF] test_vsldoi_2228_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [81FFFCFF, 7D000300, 8200FFFF, 000000FF] test_vsldoi_2229_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vsldoi_2230_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FDFF7E00, 020081FF, FCFF7D00, 03008204] test_vsldoi_2231_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FF7E0002, 0081FFFC, FF7D0003, 00820404] test_vsldoi_2232_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [81FFFCFF, 7D000300, 82040404, 04040404] test_vsldoi_2233_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vsldoi_2234_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FDFF7E00, 020081FF, FCFF7D00, 03008207] test_vsldoi_2235_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FF7E0002, 0081FFFC, FF7D0003, 00820707] test_vsldoi_2236_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [81FFFCFF, 7D000300, 82070707, 07070707] test_vsldoi_2237_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vsldoi_2238_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FDFF7E00, 020081FF, FCFF7D00, 03008208] test_vsldoi_2239_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FF7E0002, 0081FFFC, FF7D0003, 00820808] test_vsldoi_2240_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [81FFFCFF, 7D000300, 82080808, 08080808] test_vsldoi_2241_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vsldoi_2242_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FDFF7E00, 020081FF, FCFF7D00, 03008212] test_vsldoi_2243_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FF7E0002, 0081FFFC, FF7D0003, 00821212] test_vsldoi_2244_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [81FFFCFF, 7D000300, 82121212, 12121212] test_vsldoi_2245_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vsldoi_2246_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FDFF7E00, 020081FF, FCFF7D00, 03008212] test_vsldoi_2247_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FF7E0002, 0081FFFC, FF7D0003, 00821234] test_vsldoi_2248_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [81FFFCFF, 7D000300, 82123456, 78876543] test_vsldoi_2249_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vsldoi_2250_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FDFF7E00, 020081FF, FCFF7D00, 0300823F] test_vsldoi_2251_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FF7E0002, 0081FFFC, FF7D0003, 00823F80] test_vsldoi_2252_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [81FFFCFF, 7D000300, 823F8000, 003FC000] test_vsldoi_2253_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vsldoi_2254_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FDFF7E00, 020081FF, FCFF7D00, 03008241] test_vsldoi_2255_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FF7E0002, 0081FFFC, FF7D0003, 00824120] test_vsldoi_2256_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [81FFFCFF, 7D000300, 82412000, 00C12000] test_vsldoi_2257_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vsldoi_2258_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FDFF7E00, 020081FF, FCFF7D00, 0300827F] test_vsldoi_2259_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FF7E0002, 0081FFFC, FF7D0003, 00827F80] test_vsldoi_2260_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [81FFFCFF, 7D000300, 827F8002, 03040506] test_vsldoi_2261_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vsldoi_2262_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [FDFF7E00, 020081FF, FCFF7D00, 03008280] test_vsldoi_2263_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [FF7E0002, 0081FFFC, FF7D0003, 00828008] test_vsldoi_2264_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [81FFFCFF, 7D000300, 82800810, 10808F00] test_vsldoi_2265_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vsldoi_2266_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [FDFF7E00, 020081FF, FCFF7D00, 030082BF] test_vsldoi_2267_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [FF7E0002, 0081FFFC, FF7D0003, 0082BF80] test_vsldoi_2268_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [81FFFCFF, 7D000300, 82BF8000, 00BFC000] test_vsldoi_2269_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vsldoi_2270_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [FDFF7E00, 020081FF, FCFF7D00, 030082C1] test_vsldoi_2271_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [FF7E0002, 0081FFFC, FF7D0003, 0082C120] test_vsldoi_2272_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [81FFFCFF, 7D000300, 82C12000, 0041A000] test_vsldoi_2273_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vsldoi_2274_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [FDFF7E00, 020081FF, FCFF7D00, 030082CD] test_vsldoi_2275_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [FF7E0002, 0081FFFC, FF7D0003, 0082CDCD] test_vsldoi_2276_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [81FFFCFF, 7D000300, 82CDCDCD, CDCDCDCD] test_vsldoi_2277_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vsldoi_2278_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [FDFF7E00, 020081FF, FCFF7D00, 030082F8] test_vsldoi_2279_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [FF7E0002, 0081FFFC, FF7D0003, 0082F8F9] test_vsldoi_2280_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [81FFFCFF, 7D000300, 82F8F9FA, FBFCFDFE] test_vsldoi_2281_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vsldoi_2282_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FDFF7E00, 020081FF, FCFF7D00, 030082FE] test_vsldoi_2283_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FF7E0002, 0081FFFC, FF7D0003, 0082FEFE] test_vsldoi_2284_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [81FFFCFF, 7D000300, 82FEFEFE, FEFEFEFE] test_vsldoi_2285_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vsldoi_2286_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FDFF7E00, 020081FF, FCFF7D00, 030082FF] test_vsldoi_2287_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FF7E0002, 0081FFFC, FF7D0003, 0082FFFC] test_vsldoi_2288_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [81FFFCFF, 7D000300, 82FFFCFF, FDFFFEFF] test_vsldoi_2289_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vsldoi_2290_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FDFF7E00, 020081FF, FCFF7D00, 030082FF] test_vsldoi_2291_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FF7E0002, 0081FFFC, FF7D0003, 0082FFFF] test_vsldoi_2292_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [81FFFCFF, 7D000300, 82FFFF01, 017070FF] test_vsldoi_2293_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vsldoi_2294_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FDFF7E00, 020081FF, FCFF7D00, 030082FF] test_vsldoi_2295_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FF7E0002, 0081FFFC, FF7D0003, 0082FFFF] test_vsldoi_2296_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [81FFFCFF, 7D000300, 82FFFFFF, 80000000] test_vsldoi_2297_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vsldoi_2298_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FDFF7E00, 020081FF, FCFF7D00, 030082FF] test_vsldoi_2299_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FF7E0002, 0081FFFC, FF7D0003, 0082FFFF] test_vsldoi_2300_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [81FFFCFF, 7D000300, 82FFFFFF, FFFFFFFF] test_vsldoi_2301_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] test_vsldoi_2302_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FF010170, 70FFFFFF, FFFFFF00, 00000000] test_vsldoi_2303_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [01017070, FFFFFFFF, FFFF0000, 00000000] test_vsldoi_2304_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FFFFFFFF, FF000000, 00000000, 00000000] test_vsldoi_2305_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] test_vsldoi_2306_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FF010170, 70FFFFFF, FFFFFF00, 00000000] test_vsldoi_2307_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [01017070, FFFFFFFF, FFFF0000, 00000000] test_vsldoi_2308_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FFFFFFFF, FF000000, 00000000, 01000000] test_vsldoi_2309_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] test_vsldoi_2310_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FF010170, 70FFFFFF, FFFFFF00, 00000000] test_vsldoi_2311_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [01017070, FFFFFFFF, FFFF0000, 00000000] test_vsldoi_2312_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FFFFFFFF, FF000000, 000000FF, FFFFFF00] test_vsldoi_2313_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] test_vsldoi_2314_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FF010170, 70FFFFFF, FFFFFF00, 00000000] test_vsldoi_2315_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [01017070, FFFFFFFF, FFFF0000, 00000001] test_vsldoi_2316_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFFFFFF, FF000000, 00000102, 03040506] test_vsldoi_2317_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] test_vsldoi_2318_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FF010170, 70FFFFFF, FFFFFF00, 00000000] test_vsldoi_2319_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [01017070, FFFFFFFF, FFFF0000, 0000000D] test_vsldoi_2320_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FFFFFFFF, FF000000, 00000D00, 0D000D00] test_vsldoi_2321_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] test_vsldoi_2322_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FF010170, 70FFFFFF, FFFFFF00, 00000000] test_vsldoi_2323_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [01017070, FFFFFFFF, FFFF0000, 00000011] test_vsldoi_2324_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FFFFFFFF, FF000000, 00001122, 33445566] test_vsldoi_2325_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] test_vsldoi_2326_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FF010170, 70FFFFFF, FFFFFF00, 00000000] test_vsldoi_2327_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [01017070, FFFFFFFF, FFFF0000, 000000FF] test_vsldoi_2328_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FFFFFFFF, FF000000, 0000FFFF, 000000FF] test_vsldoi_2329_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] test_vsldoi_2330_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FF010170, 70FFFFFF, FFFFFF00, 00000004] test_vsldoi_2331_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [01017070, FFFFFFFF, FFFF0000, 00000404] test_vsldoi_2332_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FFFFFFFF, FF000000, 00040404, 04040404] test_vsldoi_2333_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] test_vsldoi_2334_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FF010170, 70FFFFFF, FFFFFF00, 00000007] test_vsldoi_2335_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [01017070, FFFFFFFF, FFFF0000, 00000707] test_vsldoi_2336_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FFFFFFFF, FF000000, 00070707, 07070707] test_vsldoi_2337_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] test_vsldoi_2338_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FF010170, 70FFFFFF, FFFFFF00, 00000008] test_vsldoi_2339_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [01017070, FFFFFFFF, FFFF0000, 00000808] test_vsldoi_2340_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FFFFFFFF, FF000000, 00080808, 08080808] test_vsldoi_2341_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] test_vsldoi_2342_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FF010170, 70FFFFFF, FFFFFF00, 00000012] test_vsldoi_2343_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [01017070, FFFFFFFF, FFFF0000, 00001212] test_vsldoi_2344_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FFFFFFFF, FF000000, 00121212, 12121212] test_vsldoi_2345_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] test_vsldoi_2346_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FF010170, 70FFFFFF, FFFFFF00, 00000012] test_vsldoi_2347_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [01017070, FFFFFFFF, FFFF0000, 00001234] test_vsldoi_2348_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FFFFFFFF, FF000000, 00123456, 78876543] test_vsldoi_2349_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] test_vsldoi_2350_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FF010170, 70FFFFFF, FFFFFF00, 0000003F] test_vsldoi_2351_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [01017070, FFFFFFFF, FFFF0000, 00003F80] test_vsldoi_2352_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FFFFFFFF, FF000000, 003F8000, 003FC000] test_vsldoi_2353_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] test_vsldoi_2354_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FF010170, 70FFFFFF, FFFFFF00, 00000041] test_vsldoi_2355_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [01017070, FFFFFFFF, FFFF0000, 00004120] test_vsldoi_2356_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FFFFFFFF, FF000000, 00412000, 00C12000] test_vsldoi_2357_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] test_vsldoi_2358_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FF010170, 70FFFFFF, FFFFFF00, 0000007F] test_vsldoi_2359_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [01017070, FFFFFFFF, FFFF0000, 00007F80] test_vsldoi_2360_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFFFFFF, FF000000, 007F8002, 03040506] test_vsldoi_2361_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] test_vsldoi_2362_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [FF010170, 70FFFFFF, FFFFFF00, 00000080] test_vsldoi_2363_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [01017070, FFFFFFFF, FFFF0000, 00008008] test_vsldoi_2364_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FF000000, 00800810, 10808F00] test_vsldoi_2365_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] test_vsldoi_2366_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [FF010170, 70FFFFFF, FFFFFF00, 000000BF] test_vsldoi_2367_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [01017070, FFFFFFFF, FFFF0000, 0000BF80] test_vsldoi_2368_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [FFFFFFFF, FF000000, 00BF8000, 00BFC000] test_vsldoi_2369_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] test_vsldoi_2370_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [FF010170, 70FFFFFF, FFFFFF00, 000000C1] test_vsldoi_2371_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [01017070, FFFFFFFF, FFFF0000, 0000C120] test_vsldoi_2372_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [FFFFFFFF, FF000000, 00C12000, 0041A000] test_vsldoi_2373_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] test_vsldoi_2374_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [FF010170, 70FFFFFF, FFFFFF00, 000000CD] test_vsldoi_2375_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [01017070, FFFFFFFF, FFFF0000, 0000CDCD] test_vsldoi_2376_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [FFFFFFFF, FF000000, 00CDCDCD, CDCDCDCD] test_vsldoi_2377_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] test_vsldoi_2378_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [FF010170, 70FFFFFF, FFFFFF00, 000000F8] test_vsldoi_2379_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [01017070, FFFFFFFF, FFFF0000, 0000F8F9] test_vsldoi_2380_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [FFFFFFFF, FF000000, 00F8F9FA, FBFCFDFE] test_vsldoi_2381_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] test_vsldoi_2382_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FF010170, 70FFFFFF, FFFFFF00, 000000FE] test_vsldoi_2383_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [01017070, FFFFFFFF, FFFF0000, 0000FEFE] test_vsldoi_2384_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FFFFFFFF, FF000000, 00FEFEFE, FEFEFEFE] test_vsldoi_2385_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] test_vsldoi_2386_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FF010170, 70FFFFFF, FFFFFF00, 000000FF] test_vsldoi_2387_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [01017070, FFFFFFFF, FFFF0000, 0000FFFC] test_vsldoi_2388_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFFFFFF, FF000000, 00FFFCFF, FDFFFEFF] test_vsldoi_2389_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] test_vsldoi_2390_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FF010170, 70FFFFFF, FFFFFF00, 000000FF] test_vsldoi_2391_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [01017070, FFFFFFFF, FFFF0000, 0000FFFD] test_vsldoi_2392_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFFFFFF, FF000000, 00FFFDFF, 7E000200] test_vsldoi_2393_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] test_vsldoi_2394_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FF010170, 70FFFFFF, FFFFFF00, 000000FF] test_vsldoi_2395_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [01017070, FFFFFFFF, FFFF0000, 0000FFFF] test_vsldoi_2396_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFFFF, FF000000, 00FFFFFF, 80000000] test_vsldoi_2397_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] test_vsldoi_2398_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FF010170, 70FFFFFF, FFFFFF00, 000000FF] test_vsldoi_2399_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [01017070, FFFFFFFF, FFFF0000, 0000FFFF] test_vsldoi_2400_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FF000000, 00FFFFFF, FFFFFFFF] test_vsldoi_2401_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vsldoi_2402_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FFFF8000, 00007FFF, FEFF7F00, 01008000] test_vsldoi_2403_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FF800000, 007FFFFE, FF7F0001, 00800000] test_vsldoi_2404_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [7FFFFEFF, 7F000100, 80000000, 00000000] test_vsldoi_2405_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vsldoi_2406_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FFFF8000, 00007FFF, FEFF7F00, 01008000] test_vsldoi_2407_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FF800000, 007FFFFE, FF7F0001, 00800000] test_vsldoi_2408_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [7FFFFEFF, 7F000100, 80000000, 01000000] test_vsldoi_2409_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vsldoi_2410_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FFFF8000, 00007FFF, FEFF7F00, 01008000] test_vsldoi_2411_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FF800000, 007FFFFE, FF7F0001, 00800000] test_vsldoi_2412_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [7FFFFEFF, 7F000100, 800000FF, FFFFFF00] test_vsldoi_2413_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vsldoi_2414_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFF8000, 00007FFF, FEFF7F00, 01008000] test_vsldoi_2415_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FF800000, 007FFFFE, FF7F0001, 00800001] test_vsldoi_2416_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7FFFFEFF, 7F000100, 80000102, 03040506] test_vsldoi_2417_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vsldoi_2418_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FFFF8000, 00007FFF, FEFF7F00, 01008000] test_vsldoi_2419_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FF800000, 007FFFFE, FF7F0001, 0080000D] test_vsldoi_2420_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [7FFFFEFF, 7F000100, 80000D00, 0D000D00] test_vsldoi_2421_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vsldoi_2422_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FFFF8000, 00007FFF, FEFF7F00, 01008000] test_vsldoi_2423_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FF800000, 007FFFFE, FF7F0001, 00800011] test_vsldoi_2424_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [7FFFFEFF, 7F000100, 80001122, 33445566] test_vsldoi_2425_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vsldoi_2426_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FFFF8000, 00007FFF, FEFF7F00, 01008000] test_vsldoi_2427_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FF800000, 007FFFFE, FF7F0001, 008000FF] test_vsldoi_2428_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [7FFFFEFF, 7F000100, 8000FFFF, 000000FF] test_vsldoi_2429_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vsldoi_2430_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FFFF8000, 00007FFF, FEFF7F00, 01008004] test_vsldoi_2431_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FF800000, 007FFFFE, FF7F0001, 00800404] test_vsldoi_2432_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [7FFFFEFF, 7F000100, 80040404, 04040404] test_vsldoi_2433_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vsldoi_2434_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FFFF8000, 00007FFF, FEFF7F00, 01008007] test_vsldoi_2435_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FF800000, 007FFFFE, FF7F0001, 00800707] test_vsldoi_2436_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [7FFFFEFF, 7F000100, 80070707, 07070707] test_vsldoi_2437_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vsldoi_2438_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FFFF8000, 00007FFF, FEFF7F00, 01008008] test_vsldoi_2439_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FF800000, 007FFFFE, FF7F0001, 00800808] test_vsldoi_2440_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [7FFFFEFF, 7F000100, 80080808, 08080808] test_vsldoi_2441_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vsldoi_2442_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FFFF8000, 00007FFF, FEFF7F00, 01008012] test_vsldoi_2443_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FF800000, 007FFFFE, FF7F0001, 00801212] test_vsldoi_2444_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [7FFFFEFF, 7F000100, 80121212, 12121212] test_vsldoi_2445_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vsldoi_2446_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FFFF8000, 00007FFF, FEFF7F00, 01008012] test_vsldoi_2447_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FF800000, 007FFFFE, FF7F0001, 00801234] test_vsldoi_2448_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [7FFFFEFF, 7F000100, 80123456, 78876543] test_vsldoi_2449_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vsldoi_2450_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FFFF8000, 00007FFF, FEFF7F00, 0100803F] test_vsldoi_2451_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FF800000, 007FFFFE, FF7F0001, 00803F80] test_vsldoi_2452_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [7FFFFEFF, 7F000100, 803F8000, 003FC000] test_vsldoi_2453_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vsldoi_2454_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FFFF8000, 00007FFF, FEFF7F00, 01008041] test_vsldoi_2455_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FF800000, 007FFFFE, FF7F0001, 00804120] test_vsldoi_2456_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [7FFFFEFF, 7F000100, 80412000, 00C12000] test_vsldoi_2457_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vsldoi_2458_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFF8000, 00007FFF, FEFF7F00, 0100807F] test_vsldoi_2459_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FF800000, 007FFFFE, FF7F0001, 00807F80] test_vsldoi_2460_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7FFFFEFF, 7F000100, 807F8002, 03040506] test_vsldoi_2461_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vsldoi_2462_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [FFFF8000, 00007FFF, FEFF7F00, 01008080] test_vsldoi_2463_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [FF800000, 007FFFFE, FF7F0001, 00808008] test_vsldoi_2464_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [7FFFFEFF, 7F000100, 80800810, 10808F00] test_vsldoi_2465_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vsldoi_2466_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [FFFF8000, 00007FFF, FEFF7F00, 010080BF] test_vsldoi_2467_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [FF800000, 007FFFFE, FF7F0001, 0080BF80] test_vsldoi_2468_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [7FFFFEFF, 7F000100, 80BF8000, 00BFC000] test_vsldoi_2469_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vsldoi_2470_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [FFFF8000, 00007FFF, FEFF7F00, 010080C1] test_vsldoi_2471_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [FF800000, 007FFFFE, FF7F0001, 0080C120] test_vsldoi_2472_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [7FFFFEFF, 7F000100, 80C12000, 0041A000] test_vsldoi_2473_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vsldoi_2474_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [FFFF8000, 00007FFF, FEFF7F00, 010080CD] test_vsldoi_2475_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [FF800000, 007FFFFE, FF7F0001, 0080CDCD] test_vsldoi_2476_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [7FFFFEFF, 7F000100, 80CDCDCD, CDCDCDCD] test_vsldoi_2477_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vsldoi_2478_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [FFFF8000, 00007FFF, FEFF7F00, 010080F8] test_vsldoi_2479_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [FF800000, 007FFFFE, FF7F0001, 0080F8F9] test_vsldoi_2480_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [7FFFFEFF, 7F000100, 80F8F9FA, FBFCFDFE] test_vsldoi_2481_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vsldoi_2482_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FFFF8000, 00007FFF, FEFF7F00, 010080FE] test_vsldoi_2483_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FF800000, 007FFFFE, FF7F0001, 0080FEFE] test_vsldoi_2484_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [7FFFFEFF, 7F000100, 80FEFEFE, FEFEFEFE] test_vsldoi_2485_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vsldoi_2486_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFF8000, 00007FFF, FEFF7F00, 010080FF] test_vsldoi_2487_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FF800000, 007FFFFE, FF7F0001, 0080FFFC] test_vsldoi_2488_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [7FFFFEFF, 7F000100, 80FFFCFF, FDFFFEFF] test_vsldoi_2489_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vsldoi_2490_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFF8000, 00007FFF, FEFF7F00, 010080FF] test_vsldoi_2491_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FF800000, 007FFFFE, FF7F0001, 0080FFFD] test_vsldoi_2492_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [7FFFFEFF, 7F000100, 80FFFDFF, 7E000200] test_vsldoi_2493_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vsldoi_2494_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF8000, 00007FFF, FEFF7F00, 010080FF] test_vsldoi_2495_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FF800000, 007FFFFE, FF7F0001, 0080FFFF] test_vsldoi_2496_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [7FFFFEFF, 7F000100, 80FFFF01, 017070FF] test_vsldoi_2497_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vsldoi_2498_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFF8000, 00007FFF, FEFF7F00, 010080FF] test_vsldoi_2499_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FF800000, 007FFFFE, FF7F0001, 0080FFFF] test_vsldoi_2500_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [7FFFFEFF, 7F000100, 80FFFFFF, FFFFFFFF] test_vsldoi_2501_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vsldoi_2502_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFF00] test_vsldoi_2503_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFF0000] test_vsldoi_2504_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FF000000, 00000000] test_vsldoi_2505_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vsldoi_2506_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFF00] test_vsldoi_2507_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFF0000] test_vsldoi_2508_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FF000000, 01000000] test_vsldoi_2509_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vsldoi_2510_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFF00] test_vsldoi_2511_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFF0000] test_vsldoi_2512_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FF0000FF, FFFFFF00] test_vsldoi_2513_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vsldoi_2514_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFF00] test_vsldoi_2515_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFF0001] test_vsldoi_2516_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FF000102, 03040506] test_vsldoi_2517_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vsldoi_2518_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFF00] test_vsldoi_2519_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFF000D] test_vsldoi_2520_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FF000D00, 0D000D00] test_vsldoi_2521_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vsldoi_2522_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFF00] test_vsldoi_2523_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFF0011] test_vsldoi_2524_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FF001122, 33445566] test_vsldoi_2525_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vsldoi_2526_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFF00] test_vsldoi_2527_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFF00FF] test_vsldoi_2528_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FF00FFFF, 000000FF] test_vsldoi_2529_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vsldoi_2530_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFF04] test_vsldoi_2531_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFF0404] test_vsldoi_2532_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FF040404, 04040404] test_vsldoi_2533_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vsldoi_2534_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFF07] test_vsldoi_2535_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFF0707] test_vsldoi_2536_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FF070707, 07070707] test_vsldoi_2537_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vsldoi_2538_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFF08] test_vsldoi_2539_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFF0808] test_vsldoi_2540_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FF080808, 08080808] test_vsldoi_2541_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vsldoi_2542_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFF12] test_vsldoi_2543_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFF1212] test_vsldoi_2544_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FF121212, 12121212] test_vsldoi_2545_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vsldoi_2546_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFF12] test_vsldoi_2547_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFF1234] test_vsldoi_2548_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FF123456, 78876543] test_vsldoi_2549_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vsldoi_2550_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFF3F] test_vsldoi_2551_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFF3F80] test_vsldoi_2552_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FF3F8000, 003FC000] test_vsldoi_2553_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vsldoi_2554_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFF41] test_vsldoi_2555_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFF4120] test_vsldoi_2556_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FF412000, 00C12000] test_vsldoi_2557_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vsldoi_2558_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFF7F] test_vsldoi_2559_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFF7F80] test_vsldoi_2560_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FF7F8002, 03040506] test_vsldoi_2561_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vsldoi_2562_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFF80] test_vsldoi_2563_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFF8008] test_vsldoi_2564_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FF800810, 10808F00] test_vsldoi_2565_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vsldoi_2566_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFBF] test_vsldoi_2567_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFBF80] test_vsldoi_2568_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFBF8000, 00BFC000] test_vsldoi_2569_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vsldoi_2570_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFC1] test_vsldoi_2571_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFC120] test_vsldoi_2572_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFC12000, 0041A000] test_vsldoi_2573_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vsldoi_2574_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFCD] test_vsldoi_2575_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFCDCD] test_vsldoi_2576_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFCDCDCD, CDCDCDCD] test_vsldoi_2577_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vsldoi_2578_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFF8] test_vsldoi_2579_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFF8F9] test_vsldoi_2580_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFF8F9FA, FBFCFDFE] test_vsldoi_2581_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vsldoi_2582_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFE] test_vsldoi_2583_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFEFE] test_vsldoi_2584_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFEFEFE, FEFEFEFE] test_vsldoi_2585_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vsldoi_2586_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vsldoi_2587_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFC] test_vsldoi_2588_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFCFF, FDFFFEFF] test_vsldoi_2589_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vsldoi_2590_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vsldoi_2591_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFD] test_vsldoi_2592_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFDFF, 7E000200] test_vsldoi_2593_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vsldoi_2594_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vsldoi_2595_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vsldoi_2596_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFF01, 017070FF] test_vsldoi_2597_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 0 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vsldoi_2598_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 1 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vsldoi_2599_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vsldoi_2600_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vsldoi v3, v1, v2, 7 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, 80000000]