test_vmrglw_1:
  #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
  #_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
  vmrglw v5, v3, v4
  blr
  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
  #_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
  #_ REGISTER_OUT v5 [08090a0b, 18191a1b, 0c0d0e0f, 1c1d1e1f]

test_vmrglw_2:
  #_ REGISTER_IN v3 [00000000, 00000001, 00000002, 00000003]
  #_ REGISTER_IN v4 [00000004, 00000005, 00000006, 00000007]
  vmrglw v5, v3, v4
  blr
  #_ REGISTER_OUT v3 [00000000, 00000001, 00000002, 00000003]
  #_ REGISTER_OUT v4 [00000004, 00000005, 00000006, 00000007]
  #_ REGISTER_OUT v5 [00000002, 00000006, 00000003, 00000007]

test_vmrglw_3:
  #_ REGISTER_IN v3 [C0800000, C0400000, C0000000, BF800000]
  #_ REGISTER_IN v4 [00000000, 3F800000, 40000000, 40400000]
  vmrglw v5, v3, v4
  blr
  #_ REGISTER_OUT v3 [C0800000, C0400000, C0000000, BF800000]
  #_ REGISTER_OUT v4 [00000000, 3F800000, 40000000, 40400000]
  #_ REGISTER_OUT v5 [C0000000, 40000000, BF800000, 40400000]

test_vmrglw_4:
  #_ REGISTER_IN v3 [FFFFFFFC, FFFFFFFD, FFFFFFFE, FFFFFFFF]
  #_ REGISTER_IN v4 [00000000, 00000001, 00000002, 00000003]
  vmrglw v5, v3, v4
  blr
  #_ REGISTER_OUT v3 [FFFFFFFC, FFFFFFFD, FFFFFFFE, FFFFFFFF]
  #_ REGISTER_OUT v4 [00000000, 00000001, 00000002, 00000003]
  #_ REGISTER_OUT v5 [FFFFFFFE, 00000002, FFFFFFFF, 00000003]