test_vrlw_1:
  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
  #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
  vrlw v3, v3, v4
  blr
  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
  #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]

test_vrlw_2:
  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
  vrlw v3, v3, v4
  blr
  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]

test_vrlw_3:
  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
  #_ REGISTER_IN v4 [0000001F, 0000001F, 0000001F, 0000001F]
  vrlw v3, v3, v4
  blr
  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
  #_ REGISTER_OUT v4 [0000001F, 0000001F, 0000001F, 0000001F]

test_vrlw_4:
  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
  #_ REGISTER_IN v4 [00000020, 00000020, 00000020, 00000020]
  vrlw v3, v3, v4
  blr
  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
  #_ REGISTER_OUT v4 [00000020, 00000020, 00000020, 00000020]

test_vrlw_5:
  #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
  #_ REGISTER_IN v4 [00000021, 00000021, 00000021, 00000021]
  vrlw v3, v3, v4
  blr
  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
  #_ REGISTER_OUT v4 [00000021, 00000021, 00000021, 00000021]

test_vrlw_6:
  #_ REGISTER_IN v3 [80000000, 80000000, 80000000, 80000000]
  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
  vrlw v3, v3, v4
  blr
  #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]

test_vrlw_7:
  #_ REGISTER_IN v3 [00000001, 00000001, 00000001, 00000001]
  #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
  vrlw v3, v3, v4
  blr
  #_ REGISTER_OUT v3 [00000002, 00000002, 00000002, 00000002]
  #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]

test_vrlw_8:
  #_ REGISTER_IN v3 [12345678, 87654321, ABCDEF01, FEDCBA98]
  #_ REGISTER_IN v4 [00000008, 00000010, 00000004, 0000000C]
  vrlw v3, v3, v4
  blr
  #_ REGISTER_OUT v3 [34567812, 43218765, BCDEF01A, CBA98FED]
  #_ REGISTER_OUT v4 [00000008, 00000010, 00000004, 0000000C]

test_vrlw_9:
  #_ REGISTER_IN v3 [C0000003, C0000003, C0000003, C0000003]
  #_ REGISTER_IN v4 [00000004, 00000004, 00000004, 00000004]
  vrlw v3, v3, v4
  blr
  #_ REGISTER_OUT v3 [0000003C, 0000003C, 0000003C, 0000003C]
  #_ REGISTER_OUT v4 [00000004, 00000004, 00000004, 00000004]