test_vsubuhs_1: #_ REGISTER_IN v3 [00020002, 00020002, 00020002, 00020002] #_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001] vsubuhs v5, v3, v4 blr #_ REGISTER_OUT v3 [00020002, 00020002, 00020002, 00020002] #_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001] #_ REGISTER_OUT v5 [00010001, 00010001, 00010001, 00010001] test_vsubuhs_2: #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001] vsubuhs v5, v3, v4 blr #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001] #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000] test_vsubuhs_3: #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsubuhs v5, v3, v4 blr #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000] test_vsubuhs_4: #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000] vsubuhs v5, v3, v4 blr #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vsubuhs_5: #_ REGISTER_IN v3 [00010001, 00010001, 00010001, 00010001] #_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001] vsubuhs v5, v3, v4 blr #_ REGISTER_OUT v3 [00010001, 00010001, 00010001, 00010001] #_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001] #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000] test_vsubuhs_6: #_ REGISTER_IN v3 [80004000, 20001000, FFFF0FFF, 10000800] #_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001] vsubuhs v5, v3, v4 blr #_ REGISTER_OUT v3 [80004000, 20001000, FFFF0FFF, 10000800] #_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001] #_ REGISTER_OUT v5 [7FFF3FFF, 1FFF0FFF, FFFE0FFE, 0FFF07FF]