test_vsubuws_1: #_ REGISTER_IN v3 [00000002, 00000002, 00000002, 00000002] #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001] vsubuws v5, v3, v4 blr #_ REGISTER_OUT v3 [00000002, 00000002, 00000002, 00000002] #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v5 [00000001, 00000001, 00000001, 00000001] test_vsubuws_2: #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001] vsubuws v5, v3, v4 blr #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000] test_vsubuws_3: #_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vsubuws v5, v3, v4 blr #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000] test_vsubuws_4: #_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000] vsubuws v5, v3, v4 blr #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vsubuws_5: #_ REGISTER_IN v3 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001] vsubuws v5, v3, v4 blr #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000] test_vsubuws_6: #_ REGISTER_IN v3 [80000000, 40000000, FFFFFFFF, 10000000] #_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001] vsubuws v5, v3, v4 blr #_ REGISTER_OUT v3 [80000000, 40000000, FFFFFFFF, 10000000] #_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v5 [7FFFFFFF, 3FFFFFFF, FFFFFFFE, 0FFFFFFF]