//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer xe_system_cbuffer
// {
//
//   uint xe_flags;                     // Offset:    0 Size:     4 [unused]
//   uint xe_line_loop_closing_index;   // Offset:    4 Size:     4 [unused]
//   uint xe_vertex_index_endian;       // Offset:    8 Size:     4
//   int xe_vertex_base_index;          // Offset:   12 Size:     4
//   float4 xe_user_clip_planes[6];     // Offset:   16 Size:    96 [unused]
//   float3 xe_ndc_scale;               // Offset:  112 Size:    12 [unused]
//   uint xe_ps_param_gen;              // Offset:  124 Size:     4 [unused]
//   float3 xe_ndc_offset;              // Offset:  128 Size:    12 [unused]
//   float xe_alpha_test_reference;     // Offset:  140 Size:     4 [unused]
//   float2 xe_point_size;              // Offset:  144 Size:     8 [unused]
//   float2 xe_point_size_min_max;      // Offset:  152 Size:     8 [unused]
//   float2 xe_point_screen_to_ndc;     // Offset:  160 Size:     8 [unused]
//   uint2 xe_sample_count_log2;        // Offset:  168 Size:     8 [unused]
//   uint4 xe_texture_swizzled_signs[2];// Offset:  176 Size:    32 [unused]
//   uint xe_alpha_to_mask;             // Offset:  208 Size:     4 [unused]
//   uint xe_edram_resolution_square_scale;// Offset:  212 Size:     4 [unused]
//   uint xe_edram_pitch_tiles;         // Offset:  216 Size:     4 [unused]
//   uint xe_edram_depth_base_dwords;   // Offset:  220 Size:     4 [unused]
//   float4 xe_color_exp_bias;          // Offset:  224 Size:    16 [unused]
//   uint4 xe_color_output_map;         // Offset:  240 Size:    16 [unused]
//   float2 xe_tessellation_factor_range;// Offset:  256 Size:     8 [unused]
//   float2 xe_edram_depth_range;       // Offset:  264 Size:     8 [unused]
//   float2 xe_edram_poly_offset_front; // Offset:  272 Size:     8 [unused]
//   float2 xe_edram_poly_offset_back;  // Offset:  280 Size:     8 [unused]
//   uint4 xe_edram_stencil[2];         // Offset:  288 Size:    32 [unused]
//   uint4 xe_edram_rt_base_dwords_scaled;// Offset:  320 Size:    16 [unused]
//   uint4 xe_edram_rt_format_flags;    // Offset:  336 Size:    16 [unused]
//   float4 xe_edram_rt_clamp[4];       // Offset:  352 Size:    64 [unused]
//   uint4 xe_edram_rt_keep_mask[2];    // Offset:  416 Size:    32 [unused]
//   uint4 xe_edram_rt_blend_factors_ops;// Offset:  448 Size:    16 [unused]
//   float4 xe_edram_blend_constant;    // Offset:  464 Size:    16 [unused]
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_system_cbuffer                 cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_VertexID              0   x           0   VERTID    uint   x   
//
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// XEVERTEXID               0   x           0     NONE     int   x   
//
vs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][1], immediateIndexed, space=0
dcl_input_sgv v0.x, vertex_id
dcl_output o0.x
dcl_temps 1
ushr r0.x, CB0[0][0].z, l(1)
xor r0.x, r0.x, CB0[0][0].z
and r0.x, r0.x, l(1)
if_nz r0.x
  ishl r0.x, v0.x, l(8)
  ushr r0.y, v0.x, l(8)
  and r0.xy, r0.xyxx, l(0xff00ff00, 0x00ff00ff, 0, 0)
  iadd r0.x, r0.y, r0.x
else 
  mov r0.x, v0.x
endif 
and r0.y, CB0[0][0].z, l(2)
if_nz r0.y
  ushr r0.y, r0.x, l(16)
  bfi r0.x, l(16), l(16), r0.x, r0.y
endif 
iadd o0.x, r0.x, CB0[0][0].w
ret 
// Approximately 18 instruction slots used