test_vminsw_1_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminsw_2_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00000000, FFFF0000, 00000000, FFFF0000] test_vminsw_3_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminsw_4_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminsw_5_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00000000, 00000000, 8899AABB, CCDDEEFF] test_vminsw_6_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00000000, 00000000, FF0000FF, FFFF00FF] test_vminsw_7_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminsw_8_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminsw_9_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminsw_10_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminsw_11_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00000000, 87654321, 00000000, 00000000] test_vminsw_12_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminsw_13_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [00000000, C1200000, 00000000, C1700000] test_vminsw_14_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminsw_15_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80081010, 808F0000, 00000000, 8FFFFFFF] test_vminsw_16_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_17_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 00000000, C1A00000, 00000000] test_vminsw_18_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00000000] test_vminsw_19_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00000000, 00000000] test_vminsw_20_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminsw_21_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000000, 00000000] test_vminsw_22_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, 00000000, FFFCFF7D, 00000000] test_vminsw_23_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, 00000000, FFFFFFFF, 00000000] test_vminsw_24_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, 00000000, FFFEFF7F, 00000000] test_vminsw_25_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminsw_26_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminsw_27_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00000001, FFFF0000, 00000000, FFFF0000] test_vminsw_28_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminsw_29_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminsw_30_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00000001, 00000001, 8899AABB, CCDDEEFF] test_vminsw_31_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00000001, 00000001, FF0000FF, FFFF00FF] test_vminsw_32_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminsw_33_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminsw_34_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminsw_35_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminsw_36_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00000001, 87654321, 00000001, 00000001] test_vminsw_37_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminsw_38_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [00000001, C1200000, 00000001, C1700000] test_vminsw_39_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminsw_40_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80081010, 808F0000, 00000001, 8FFFFFFF] test_vminsw_41_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_42_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 00000001, C1A00000, 00000001] test_vminsw_43_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00000001] test_vminsw_44_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00000001, 00000001] test_vminsw_45_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminsw_46_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00000001] test_vminsw_47_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, 00000001, FFFCFF7D, 00000001] test_vminsw_48_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, 00000001, FFFFFFFF, 00000000] test_vminsw_49_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, 00000001, FFFEFF7F, 00000001] test_vminsw_50_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminsw_51_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, FFFF0000, 00000000, FFFF0000] test_vminsw_52_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000001, FFFF0000, 00000000, FFFF0000] test_vminsw_53_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vminsw_54_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vminsw_55_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 8899AABB, CCDDEEFF] test_vminsw_56_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, FF0000FF, FFFF0000] test_vminsw_57_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vminsw_58_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vminsw_59_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vminsw_60_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vminsw_61_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [0000FFFF, 87654321, 00000000, FFFF0000] test_vminsw_62_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vminsw_63_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [0000FFFF, C1200000, 00000000, C1700000] test_vminsw_64_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vminsw_65_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80081010, 808F0000, 00000000, 8FFFFFFF] test_vminsw_66_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_67_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, FFFF0000, C1A00000, FFFF0000] test_vminsw_68_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, FFFF0000] test_vminsw_69_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00000000, FFFF0000] test_vminsw_70_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminsw_71_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000000, FFFF0000] test_vminsw_72_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, FFFF0000, FFFCFF7D, FFFF0000] test_vminsw_73_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, FFFF0000, FFFFFFFF, FFFF0000] test_vminsw_74_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, FFFF0000, FFFEFF7F, FFFF0000] test_vminsw_75_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFF0000, FFFFFFFF, FFFF0000] test_vminsw_76_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminsw_77_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminsw_78_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vminsw_79_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00010203, 000D000D, 000D000D, 000D000D] test_vminsw_80_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00010203, 04050607, 8899AABB, CCDDEEFF] test_vminsw_81_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00010203, 0000FF00, FF0000FF, FFFF00FF] test_vminsw_82_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00010203, 04040404, 04040404, 04040404] test_vminsw_83_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00010203, 04050607, 07070707, 07070707] test_vminsw_84_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00010203, 04050607, 08080808, 08080808] test_vminsw_85_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vminsw_86_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00010203, 87654321, 08090A0B, 0C0D0E0F] test_vminsw_87_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vminsw_88_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [00010203, C1200000, 08090A0B, C1700000] test_vminsw_89_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vminsw_90_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80081010, 808F0000, 08090A0B, 8FFFFFFF] test_vminsw_91_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_92_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 04050607, C1A00000, 0C0D0E0F] test_vminsw_93_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminsw_94_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vminsw_95_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminsw_96_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vminsw_97_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vminsw_98_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, 04050607, FFFFFFFF, 00000000] test_vminsw_99_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vminsw_100_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminsw_101_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminsw_102_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminsw_103_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vminsw_104_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 000D000D, 000D000D, 000D000D] test_vminsw_105_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [000D000D, 000D000D, 8899AABB, CCDDEEFF] test_vminsw_106_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [000D000D, 0000FF00, FF0000FF, FFFF00FF] test_vminsw_107_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vminsw_108_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vminsw_109_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vminsw_110_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vminsw_111_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [000D000D, 87654321, 000D000D, 000D000D] test_vminsw_112_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vminsw_113_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [000D000D, C1200000, 000D000D, C1700000] test_vminsw_114_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vminsw_115_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80081010, 808F0000, 000D000D, 8FFFFFFF] test_vminsw_116_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_117_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 000D000D, C1A00000, 000D000D] test_vminsw_118_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 000D000D] test_vminsw_119_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 000D000D] test_vminsw_120_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminsw_121_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vminsw_122_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vminsw_123_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, 000D000D, FFFFFFFF, 00000000] test_vminsw_124_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vminsw_125_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminsw_126_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 8899AABB, CCDDEEFF] test_vminsw_127_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000001, 00000001, 8899AABB, CCDDEEFF] test_vminsw_128_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 8899AABB, CCDDEEFF] test_vminsw_129_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 8899AABB, CCDDEEFF] test_vminsw_130_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [000D000D, 000D000D, 8899AABB, CCDDEEFF] test_vminsw_131_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00112233, 0000FF00, 8899AABB, CCDDEEFF] test_vminsw_132_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00112233, 04040404, 8899AABB, CCDDEEFF] test_vminsw_133_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00112233, 07070707, 8899AABB, CCDDEEFF] test_vminsw_134_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00112233, 08080808, 8899AABB, CCDDEEFF] test_vminsw_135_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00112233, 12121212, 8899AABB, CCDDEEFF] test_vminsw_136_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00112233, 87654321, 8899AABB, CCDDEEFF] test_vminsw_137_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [00112233, 3FC00000, 8899AABB, CCDDEEFF] test_vminsw_138_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [00112233, C1200000, 8899AABB, C1700000] test_vminsw_139_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00112233, 04050607, 8899AABB, CCDDEEFF] test_vminsw_140_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80081010, 808F0000, 8899AABB, 8FFFFFFF] test_vminsw_141_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, 8899AABB, BFF33333] test_vminsw_142_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 41A00000, 8899AABB, CCDDEEFF] test_vminsw_143_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, 8899AABB, CCDDEEFF] test_vminsw_144_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 8899AABB, CCDDEEFF] test_vminsw_145_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, 8899AABB, CCDDEEFF] test_vminsw_146_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 8899AABB, CCDDEEFF] test_vminsw_147_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, 8899AABB, CCDDEEFF] test_vminsw_148_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, 44556677, 8899AABB, CCDDEEFF] test_vminsw_149_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, 8899AABB, CCDDEEFF] test_vminsw_150_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, 8899AABB, CCDDEEFF] test_vminsw_151_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, FF0000FF, FFFF00FF] test_vminsw_152_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000001, 00000001, FF0000FF, FFFF00FF] test_vminsw_153_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, FF0000FF, FFFF0000] test_vminsw_154_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 0000FF00, FF0000FF, FFFF00FF] test_vminsw_155_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [000D000D, 0000FF00, FF0000FF, FFFF00FF] test_vminsw_156_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00112233, 0000FF00, 8899AABB, CCDDEEFF] test_vminsw_157_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vminsw_158_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vminsw_159_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vminsw_160_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vminsw_161_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00FFFF00, 87654321, FF0000FF, FFFF00FF] test_vminsw_162_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vminsw_163_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [00FFFF00, C1200000, FF0000FF, C1700000] test_vminsw_164_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vminsw_165_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80081010, 808F0000, FF0000FF, 8FFFFFFF] test_vminsw_166_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_167_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 0000FF00, C1A00000, FFFF00FF] test_vminsw_168_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, FFFF00FF] test_vminsw_169_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, FF0000FF, FFFF00FF] test_vminsw_170_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminsw_171_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, FF0000FF, FFFF00FF] test_vminsw_172_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, 0000FF00, FF0000FF, FFFF00FF] test_vminsw_173_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, 0000FF00, FF0000FF, FFFF00FF] test_vminsw_174_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FF0000FF, FFFF00FF] test_vminsw_175_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FF0000FF, FFFF00FF] test_vminsw_176_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminsw_177_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminsw_178_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vminsw_179_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04040404, 04040404, 04040404] test_vminsw_180_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vminsw_181_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00112233, 04040404, 8899AABB, CCDDEEFF] test_vminsw_182_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vminsw_183_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vminsw_184_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vminsw_185_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vminsw_186_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [04040404, 87654321, 04040404, 04040404] test_vminsw_187_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vminsw_188_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [04040404, C1200000, 04040404, C1700000] test_vminsw_189_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vminsw_190_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80081010, 808F0000, 04040404, 8FFFFFFF] test_vminsw_191_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_192_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 04040404, C1A00000, 04040404] test_vminsw_193_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminsw_194_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04040404] test_vminsw_195_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminsw_196_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vminsw_197_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vminsw_198_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, 04040404, FFFFFFFF, 00000000] test_vminsw_199_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vminsw_200_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminsw_201_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminsw_202_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminsw_203_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vminsw_204_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 07070707, 07070707] test_vminsw_205_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vminsw_206_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00112233, 07070707, 8899AABB, CCDDEEFF] test_vminsw_207_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vminsw_208_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vminsw_209_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vminsw_210_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vminsw_211_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [07070707, 87654321, 07070707, 07070707] test_vminsw_212_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vminsw_213_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [07070707, C1200000, 07070707, C1700000] test_vminsw_214_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [07070707, 04050607, 07070707, 07070707] test_vminsw_215_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80081010, 808F0000, 07070707, 8FFFFFFF] test_vminsw_216_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_217_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 07070707, C1A00000, 07070707] test_vminsw_218_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminsw_219_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vminsw_220_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminsw_221_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vminsw_222_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vminsw_223_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, 07070707, FFFFFFFF, 00000000] test_vminsw_224_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vminsw_225_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminsw_226_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminsw_227_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminsw_228_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vminsw_229_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08080808, 08080808] test_vminsw_230_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vminsw_231_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00112233, 08080808, 8899AABB, CCDDEEFF] test_vminsw_232_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vminsw_233_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vminsw_234_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vminsw_235_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vminsw_236_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [08080808, 87654321, 08080808, 08080808] test_vminsw_237_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vminsw_238_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [08080808, C1200000, 08080808, C1700000] test_vminsw_239_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [08080808, 04050607, 08080808, 08080808] test_vminsw_240_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80081010, 808F0000, 08080808, 8FFFFFFF] test_vminsw_241_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_242_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 08080808, C1A00000, 08080808] test_vminsw_243_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminsw_244_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vminsw_245_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminsw_246_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vminsw_247_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vminsw_248_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, 08080808, FFFFFFFF, 00000000] test_vminsw_249_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vminsw_250_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminsw_251_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminsw_252_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminsw_253_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vminsw_254_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vminsw_255_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vminsw_256_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00112233, 12121212, 8899AABB, CCDDEEFF] test_vminsw_257_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vminsw_258_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vminsw_259_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vminsw_260_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vminsw_261_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [12121212, 87654321, 11223344, 12121212] test_vminsw_262_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212] test_vminsw_263_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [12121212, C1200000, 12121212, C1700000] test_vminsw_264_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [12121212, 04050607, 12121212, 0C0D0E0F] test_vminsw_265_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80081010, 808F0000, 12121212, 8FFFFFFF] test_vminsw_266_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_267_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 12121212, C1A00000, 12121212] test_vminsw_268_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminsw_269_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vminsw_270_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminsw_271_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vminsw_272_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vminsw_273_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, 12121212, FFFFFFFF, 00000000] test_vminsw_274_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vminsw_275_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminsw_276_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 87654321, 00000000, 00000000] test_vminsw_277_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000001, 87654321, 00000001, 00000001] test_vminsw_278_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [0000FFFF, 87654321, 00000000, FFFF0000] test_vminsw_279_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 87654321, 08090A0B, 0C0D0E0F] test_vminsw_280_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [000D000D, 87654321, 000D000D, 000D000D] test_vminsw_281_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00112233, 87654321, 8899AABB, CCDDEEFF] test_vminsw_282_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00FFFF00, 87654321, FF0000FF, FFFF00FF] test_vminsw_283_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [04040404, 87654321, 04040404, 04040404] test_vminsw_284_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [07070707, 87654321, 07070707, 07070707] test_vminsw_285_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [08080808, 87654321, 08080808, 08080808] test_vminsw_286_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [12121212, 87654321, 11223344, 12121212] test_vminsw_287_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 3FF33333] test_vminsw_288_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, C1700000] test_vminsw_289_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 0C0D0E0F] test_vminsw_290_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80081010, 808F0000, 11223344, 8FFFFFFF] test_vminsw_291_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, 87654321, BF8CCCCD, BFF33333] test_vminsw_292_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 87654321, C1A00000, 41F00000] test_vminsw_293_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, 87654321, CDCDCDCD, 04010203] test_vminsw_294_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, 87654321, 00010203, 04050607] test_vminsw_295_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, 87654321, FEFEFEFE, FEFEFEFE] test_vminsw_296_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, 87654321, 00000001, 00020003] test_vminsw_297_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, 87654321, FFFCFF7D, 00030082] test_vminsw_298_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, 87654321, FFFFFFFF, 00000000] test_vminsw_299_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, 87654321, FFFEFF7F, 00010080] test_vminsw_300_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, 87654321, FFFFFFFF, FFFFFFFF] test_vminsw_301_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminsw_302_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminsw_303_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vminsw_304_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vminsw_305_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vminsw_306_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00112233, 3FC00000, 8899AABB, CCDDEEFF] test_vminsw_307_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vminsw_308_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vminsw_309_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vminsw_310_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vminsw_311_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212] test_vminsw_312_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 3FF33333] test_vminsw_313_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [3F800000, C1200000, 3F8CCCCD, C1700000] test_vminsw_314_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [3F800000, 04050607, 3F8CCCCD, 0C0D0E0F] test_vminsw_315_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80081010, 808F0000, 3F8CCCCD, 8FFFFFFF] test_vminsw_316_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_317_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 3FC00000, C1A00000, 3FF33333] test_vminsw_318_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminsw_319_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vminsw_320_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminsw_321_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vminsw_322_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vminsw_323_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, 3FC00000, FFFFFFFF, 00000000] test_vminsw_324_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vminsw_325_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminsw_326_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, C1200000, 00000000, C1700000] test_vminsw_327_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000001, C1200000, 00000001, C1700000] test_vminsw_328_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [0000FFFF, C1200000, 00000000, C1700000] test_vminsw_329_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, C1200000, 08090A0B, C1700000] test_vminsw_330_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [000D000D, C1200000, 000D000D, C1700000] test_vminsw_331_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00112233, C1200000, 8899AABB, C1700000] test_vminsw_332_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00FFFF00, C1200000, FF0000FF, C1700000] test_vminsw_333_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [04040404, C1200000, 04040404, C1700000] test_vminsw_334_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [07070707, C1200000, 07070707, C1700000] test_vminsw_335_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [08080808, C1200000, 08080808, C1700000] test_vminsw_336_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [12121212, C1200000, 12121212, C1700000] test_vminsw_337_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, C1700000] test_vminsw_338_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [3F800000, C1200000, 3F8CCCCD, C1700000] test_vminsw_339_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000] test_vminsw_340_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80081010, 808F0000, 41700000, 8FFFFFFF] test_vminsw_341_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_342_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, C1200000, C1A00000, C1700000] test_vminsw_343_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, C1200000, CDCDCDCD, C1700000] test_vminsw_344_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, C1200000, 00010203, C1700000] test_vminsw_345_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, C1200000, FEFEFEFE, C1700000] test_vminsw_346_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, C1200000, 00000001, C1700000] test_vminsw_347_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, C1200000, FFFCFF7D, C1700000] test_vminsw_348_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, C1200000, FFFFFFFF, C1700000] test_vminsw_349_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, C1200000, FFFEFF7F, C1700000] test_vminsw_350_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, C1200000, FFFFFFFF, C1700000] test_vminsw_351_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminsw_352_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminsw_353_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vminsw_354_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vminsw_355_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vminsw_356_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00112233, 04050607, 8899AABB, CCDDEEFF] test_vminsw_357_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vminsw_358_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vminsw_359_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [07070707, 04050607, 07070707, 07070707] test_vminsw_360_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [08080808, 04050607, 08080808, 08080808] test_vminsw_361_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [12121212, 04050607, 12121212, 0C0D0E0F] test_vminsw_362_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 0C0D0E0F] test_vminsw_363_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [3F800000, 04050607, 3F8CCCCD, 0C0D0E0F] test_vminsw_364_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000] test_vminsw_365_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80081010, 808F0000, 7F800A0B, 8FFFFFFF] test_vminsw_366_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_367_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 04050607, C1A00000, 0C0D0E0F] test_vminsw_368_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminsw_369_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vminsw_370_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminsw_371_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vminsw_372_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vminsw_373_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, 04050607, FFFFFFFF, 00000000] test_vminsw_374_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vminsw_375_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminsw_376_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [80081010, 808F0000, 00000000, 8FFFFFFF] test_vminsw_377_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [80081010, 808F0000, 00000001, 8FFFFFFF] test_vminsw_378_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [80081010, 808F0000, 00000000, 8FFFFFFF] test_vminsw_379_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [80081010, 808F0000, 08090A0B, 8FFFFFFF] test_vminsw_380_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [80081010, 808F0000, 000D000D, 8FFFFFFF] test_vminsw_381_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [80081010, 808F0000, 8899AABB, 8FFFFFFF] test_vminsw_382_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [80081010, 808F0000, FF0000FF, 8FFFFFFF] test_vminsw_383_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [80081010, 808F0000, 04040404, 8FFFFFFF] test_vminsw_384_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [80081010, 808F0000, 07070707, 8FFFFFFF] test_vminsw_385_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [80081010, 808F0000, 08080808, 8FFFFFFF] test_vminsw_386_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [80081010, 808F0000, 12121212, 8FFFFFFF] test_vminsw_387_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [80081010, 808F0000, 11223344, 8FFFFFFF] test_vminsw_388_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [80081010, 808F0000, 3F8CCCCD, 8FFFFFFF] test_vminsw_389_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [80081010, 808F0000, 41700000, 8FFFFFFF] test_vminsw_390_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [80081010, 808F0000, 7F800A0B, 8FFFFFFF] test_vminsw_391_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [80081010, 808F0000, BF8CCCCD, 8FFFFFFF] test_vminsw_392_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [80081010, 808F0000, C1A00000, 8FFFFFFF] test_vminsw_393_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [80081010, 808F0000, CDCDCDCD, 8FFFFFFF] test_vminsw_394_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [80081010, 808F0000, 00010203, 8FFFFFFF] test_vminsw_395_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [80081010, 808F0000, FEFEFEFE, 8FFFFFFF] test_vminsw_396_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [80081010, 808F0000, 00000001, 8FFFFFFF] test_vminsw_397_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [80081010, 808F0000, FFFCFF7D, 8FFFFFFF] test_vminsw_398_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [80081010, 808F0000, FFFFFFFF, 8FFFFFFF] test_vminsw_399_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [80081010, 808F0000, FFFEFF7F, 8FFFFFFF] test_vminsw_400_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [80081010, 808F0000, FFFFFFFF, 8FFFFFFF] test_vminsw_401_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_402_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_403_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_404_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_405_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_406_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [BF800000, BFC00000, 8899AABB, BFF33333] test_vminsw_407_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_408_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_409_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_410_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_411_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_412_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [BF800000, 87654321, BF8CCCCD, BFF33333] test_vminsw_413_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_414_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_415_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_416_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80081010, 808F0000, BF8CCCCD, 8FFFFFFF] test_vminsw_417_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_418_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_419_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_420_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_421_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_422_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_423_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_424_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_425_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_426_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [C1200000, 00000000, C1A00000, 00000000] test_vminsw_427_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [C1200000, 00000001, C1A00000, 00000001] test_vminsw_428_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [C1200000, FFFF0000, C1A00000, FFFF0000] test_vminsw_429_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [C1200000, 04050607, C1A00000, 0C0D0E0F] test_vminsw_430_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [C1200000, 000D000D, C1A00000, 000D000D] test_vminsw_431_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [C1200000, 41A00000, 8899AABB, CCDDEEFF] test_vminsw_432_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [C1200000, 0000FF00, C1A00000, FFFF00FF] test_vminsw_433_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [C1200000, 04040404, C1A00000, 04040404] test_vminsw_434_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [C1200000, 07070707, C1A00000, 07070707] test_vminsw_435_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [C1200000, 08080808, C1A00000, 08080808] test_vminsw_436_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [C1200000, 12121212, C1A00000, 12121212] test_vminsw_437_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [C1200000, 87654321, C1A00000, 41F00000] test_vminsw_438_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [C1200000, 3FC00000, C1A00000, 3FF33333] test_vminsw_439_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [C1200000, C1200000, C1A00000, C1700000] test_vminsw_440_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [C1200000, 04050607, C1A00000, 0C0D0E0F] test_vminsw_441_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80081010, 808F0000, C1A00000, 8FFFFFFF] test_vminsw_442_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_443_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [C1200000, CDCDCDCD, C1A00000, 04010203] test_vminsw_444_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [C1200000, FCFDFEFF, C1A00000, 04050607] test_vminsw_445_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [C1200000, FEFEFEFE, C1A00000, FEFEFEFE] test_vminsw_446_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [C1200000, FFFEFFFF, C1A00000, 00020003] test_vminsw_447_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [C1200000, 00020081, C1A00000, 00030082] test_vminsw_448_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 00000000] test_vminsw_449_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [C1200000, 0000007F, C1A00000, 00010080] test_vminsw_450_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [C1200000, FFFFFFFF, C1A00000, FFFFFFFF] test_vminsw_451_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00000000] test_vminsw_452_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00000001] test_vminsw_453_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, FFFF0000] test_vminsw_454_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminsw_455_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 000D000D] test_vminsw_456_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, 8899AABB, CCDDEEFF] test_vminsw_457_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, FFFF00FF] test_vminsw_458_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminsw_459_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminsw_460_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminsw_461_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminsw_462_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [CDCDCDCD, 87654321, CDCDCDCD, 04010203] test_vminsw_463_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminsw_464_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [CDCDCDCD, C1200000, CDCDCDCD, C1700000] test_vminsw_465_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminsw_466_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80081010, 808F0000, CDCDCDCD, 8FFFFFFF] test_vminsw_467_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_468_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, CDCDCDCD, C1A00000, 04010203] test_vminsw_469_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminsw_470_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, FEFEFEFE] test_vminsw_471_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00020003] test_vminsw_472_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00030082] test_vminsw_473_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00000000] test_vminsw_474_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00010080] test_vminsw_475_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, FFFFFFFF] test_vminsw_476_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00000000, 00000000] test_vminsw_477_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00000001, 00000001] test_vminsw_478_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00000000, FFFF0000] test_vminsw_479_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vminsw_480_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 000D000D] test_vminsw_481_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 8899AABB, CCDDEEFF] test_vminsw_482_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, FF0000FF, FFFF00FF] test_vminsw_483_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04040404] test_vminsw_484_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vminsw_485_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vminsw_486_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vminsw_487_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [F8F9FAFB, 87654321, 00010203, 04050607] test_vminsw_488_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vminsw_489_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [F8F9FAFB, C1200000, 00010203, C1700000] test_vminsw_490_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vminsw_491_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80081010, 808F0000, 00010203, 8FFFFFFF] test_vminsw_492_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_493_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, FCFDFEFF, C1A00000, 04050607] test_vminsw_494_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminsw_495_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, FEFEFEFE, FEFEFEFE] test_vminsw_496_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00000001, 00020003] test_vminsw_497_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, FFFCFF7D, 00030082] test_vminsw_498_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, FFFFFFFF, 00000000] test_vminsw_499_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, FFFEFF7F, 00010080] test_vminsw_500_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, FFFFFFFF, FFFFFFFF] test_vminsw_501_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminsw_502_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminsw_503_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminsw_504_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminsw_505_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminsw_506_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, 8899AABB, CCDDEEFF] test_vminsw_507_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminsw_508_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminsw_509_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminsw_510_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminsw_511_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminsw_512_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FEFEFEFE, 87654321, FEFEFEFE, FEFEFEFE] test_vminsw_513_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminsw_514_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FEFEFEFE, C1200000, FEFEFEFE, C1700000] test_vminsw_515_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminsw_516_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80081010, 808F0000, FEFEFEFE, 8FFFFFFF] test_vminsw_517_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_518_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, FEFEFEFE, C1A00000, FEFEFEFE] test_vminsw_519_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, FEFEFEFE] test_vminsw_520_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, FEFEFEFE, FEFEFEFE] test_vminsw_521_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminsw_522_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminsw_523_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminsw_524_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminsw_525_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminsw_526_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000000, 00000000] test_vminsw_527_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00000001] test_vminsw_528_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000000, FFFF0000] test_vminsw_529_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vminsw_530_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vminsw_531_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 8899AABB, CCDDEEFF] test_vminsw_532_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, FF0000FF, FFFF00FF] test_vminsw_533_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vminsw_534_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vminsw_535_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vminsw_536_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vminsw_537_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FFFCFFFD, 87654321, 00000001, 00020003] test_vminsw_538_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vminsw_539_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FFFCFFFD, C1200000, 00000001, C1700000] test_vminsw_540_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vminsw_541_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80081010, 808F0000, 00000001, 8FFFFFFF] test_vminsw_542_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_543_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, FFFEFFFF, C1A00000, 00020003] test_vminsw_544_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00020003] test_vminsw_545_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00000001, 00020003] test_vminsw_546_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminsw_547_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, FFFCFF7D, 00020003] test_vminsw_548_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, FFFFFFFF, 00000000] test_vminsw_549_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, FFFEFF7F, 00010080] test_vminsw_550_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, FFFFFFFF, FFFFFFFF] test_vminsw_551_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FFFDFF7E, 00000000, FFFCFF7D, 00000000] test_vminsw_552_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FFFDFF7E, 00000001, FFFCFF7D, 00000001] test_vminsw_553_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FFFDFF7E, FFFF0000, FFFCFF7D, FFFF0000] test_vminsw_554_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vminsw_555_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vminsw_556_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, 8899AABB, CCDDEEFF] test_vminsw_557_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FFFDFF7E, 0000FF00, FF0000FF, FFFF00FF] test_vminsw_558_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vminsw_559_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vminsw_560_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vminsw_561_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vminsw_562_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FFFDFF7E, 87654321, FFFCFF7D, 00030082] test_vminsw_563_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vminsw_564_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FFFDFF7E, C1200000, FFFCFF7D, C1700000] test_vminsw_565_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vminsw_566_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80081010, 808F0000, FFFCFF7D, 8FFFFFFF] test_vminsw_567_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_568_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 00020081, C1A00000, 00030082] test_vminsw_569_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00030082] test_vminsw_570_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, FFFCFF7D, 00030082] test_vminsw_571_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminsw_572_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, FFFCFF7D, 00020003] test_vminsw_573_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00000000] test_vminsw_574_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFDFF7E, 0000007F, FFFCFF7D, 00010080] test_vminsw_575_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFDFF7E, FFFFFFFF, FFFCFF7D, FFFFFFFF] test_vminsw_576_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FFFF0101, 00000000, FFFFFFFF, 00000000] test_vminsw_577_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FFFF0101, 00000001, FFFFFFFF, 00000000] test_vminsw_578_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FFFF0101, FFFF0000, FFFFFFFF, FFFF0000] test_vminsw_579_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFF0101, 04050607, FFFFFFFF, 00000000] test_vminsw_580_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FFFF0101, 000D000D, FFFFFFFF, 00000000] test_vminsw_581_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FFFF0101, 44556677, 8899AABB, CCDDEEFF] test_vminsw_582_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FFFF0101, 0000FF00, FF0000FF, FFFF00FF] test_vminsw_583_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FFFF0101, 04040404, FFFFFFFF, 00000000] test_vminsw_584_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FFFF0101, 07070707, FFFFFFFF, 00000000] test_vminsw_585_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FFFF0101, 08080808, FFFFFFFF, 00000000] test_vminsw_586_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FFFF0101, 12121212, FFFFFFFF, 00000000] test_vminsw_587_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FFFF0101, 87654321, FFFFFFFF, 00000000] test_vminsw_588_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FFFF0101, 3FC00000, FFFFFFFF, 00000000] test_vminsw_589_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FFFF0101, C1200000, FFFFFFFF, C1700000] test_vminsw_590_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFF0101, 04050607, FFFFFFFF, 00000000] test_vminsw_591_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80081010, 808F0000, FFFFFFFF, 8FFFFFFF] test_vminsw_592_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_593_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 00000000] test_vminsw_594_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00000000] test_vminsw_595_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, FFFFFFFF, 00000000] test_vminsw_596_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminsw_597_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, FFFFFFFF, 00000000] test_vminsw_598_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00000000] test_vminsw_599_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFF0101, 0000007F, FFFEFF7F, 00000000] test_vminsw_600_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFF0101, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminsw_601_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FFFFFF80, 00000000, FFFEFF7F, 00000000] test_vminsw_602_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FFFFFF80, 00000001, FFFEFF7F, 00000001] test_vminsw_603_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FFFFFF80, FFFF0000, FFFEFF7F, FFFF0000] test_vminsw_604_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vminsw_605_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vminsw_606_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, 8899AABB, CCDDEEFF] test_vminsw_607_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FF0000FF, FFFF00FF] test_vminsw_608_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vminsw_609_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vminsw_610_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vminsw_611_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vminsw_612_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FFFFFF80, 87654321, FFFEFF7F, 00010080] test_vminsw_613_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vminsw_614_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FFFFFF80, C1200000, FFFEFF7F, C1700000] test_vminsw_615_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vminsw_616_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80081010, 808F0000, FFFEFF7F, 8FFFFFFF] test_vminsw_617_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_618_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 0000007F, C1A00000, 00010080] test_vminsw_619_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00010080] test_vminsw_620_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, FFFEFF7F, 00010080] test_vminsw_621_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminsw_622_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, FFFEFF7F, 00010080] test_vminsw_623_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, 0000007F, FFFCFF7D, 00010080] test_vminsw_624_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, 0000007F, FFFEFF7F, 00000000] test_vminsw_625_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFF80, FFFFFFFF, FFFEFF7F, FFFFFFFF] test_vminsw_626_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminsw_627_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminsw_628_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [FFFFFFFF, FFFF0000, FFFFFFFF, FFFF0000] test_vminsw_629_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminsw_630_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminsw_631_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, 8899AABB, CCDDEEFF] test_vminsw_632_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FF0000FF, FFFF00FF] test_vminsw_633_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminsw_634_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminsw_635_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminsw_636_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminsw_637_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [FFFFFFFF, 87654321, FFFFFFFF, FFFFFFFF] test_vminsw_638_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminsw_639_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [FFFFFFFF, C1200000, FFFFFFFF, C1700000] test_vminsw_640_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminsw_641_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80081010, 808F0000, FFFFFFFF, 8FFFFFFF] test_vminsw_642_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminsw_643_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, FFFFFFFF, C1A00000, FFFFFFFF] test_vminsw_644_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, FFFFFFFF] test_vminsw_645_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, FFFFFFFF, FFFFFFFF] test_vminsw_646_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminsw_647_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, FFFFFFFF, FFFFFFFF] test_vminsw_648_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, FFFFFFFF, FFFCFF7D, FFFFFFFF] test_vminsw_649_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vminsw_650_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminsw v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, FFFFFFFF, FFFEFF7F, FFFFFFFF]