test_vminub_1_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_2_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_3_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_4_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_5_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_6_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_7_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_8_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_9_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_10_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_11_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_12_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_13_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_14_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_15_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_16_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_17_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_18_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_19_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_20_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_21_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_22_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_23_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_24_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_25_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_26_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_27_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00000001, 00000000, 00000000, 00000000] test_vminub_28_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminub_29_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminub_30_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminub_31_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00000000, 00000000, 00000001, 00000001] test_vminub_32_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminub_33_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminub_34_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminub_35_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminub_36_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminub_37_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [00000000, 00000000, 00000001, 00000001] test_vminub_38_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_39_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminub_40_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [00000001, 00000000, 00000001, 00000001] test_vminub_41_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [00000000, 00000000, 00000001, 00000001] test_vminub_42_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_43_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminub_44_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminub_45_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminub_46_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminub_47_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminub_48_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000000] test_vminub_49_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminub_50_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminub_51_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_52_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000001, 00000000, 00000000, 00000000] test_vminub_53_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000203, 04050000, 00000000, 0C0D0000] test_vminub_54_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [0000000D, 000D0000, 00000000, 000D0000] test_vminub_55_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00002233, 44550000, 00000000, CCDD0000] test_vminub_56_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [0000FF00, 00000000, 00000000, FFFF0000] test_vminub_57_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00000404, 04040000, 00000000, 04040000] test_vminub_58_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00000707, 07070000, 00000000, 07070000] test_vminub_59_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00000808, 08080000, 00000000, 08080000] test_vminub_60_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00001212, 12120000, 00000000, 12120000] test_vminub_61_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00005678, 87650000, 00000000, 55660000] test_vminub_62_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [00000000, 3FC00000, 00000000, 3FF30000] test_vminub_63_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [00000000, C1200000, 00000000, C1700000] test_vminub_64_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00000203, 04050000, 00000000, 0C0D0000] test_vminub_65_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [00001010, 808F0000, 00000000, 8FFF0000] test_vminub_66_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [00000000, BFC00000, 00000000, BFF30000] test_vminub_67_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [00000000, 41A00000, 00000000, 41F00000] test_vminub_68_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [0000CDCD, CDCD0000, 00000000, 04010000] test_vminub_69_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [0000FAFB, FCFD0000, 00000000, 04050000] test_vminub_70_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [0000FEFE, FEFE0000, 00000000, FEFE0000] test_vminub_71_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [0000FFFD, FFFE0000, 00000000, 00020000] test_vminub_72_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [0000FF7E, 00020000, 00000000, 00030000] test_vminub_73_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [00000101, 70700000, 00000000, 00000000] test_vminub_74_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [0000FF80, 00000000, 00000000, 00010000] test_vminub_75_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vminub_76_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_77_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminub_78_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00000203, 04050000, 00000000, 0C0D0000] test_vminub_79_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00010003, 00050007, 0009000B, 000D000D] test_vminub_80_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vminub_81_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00010200, 00000600, 0800000B, 0C0D000F] test_vminub_82_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00010203, 04040404, 04040404, 04040404] test_vminub_83_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00010203, 04050607, 07070707, 07070707] test_vminub_84_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00010203, 04050607, 08080808, 08080808] test_vminub_85_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vminub_86_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vminub_87_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [00010000, 04050000, 08090A0B, 0C0D0E0F] test_vminub_88_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [00010000, 04050000, 08090000, 0C0D0000] test_vminub_89_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vminub_90_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [00010203, 04050000, 08090A0B, 0C0D0E0F] test_vminub_91_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [00010000, 04050000, 08090A0B, 0C0D0E0F] test_vminub_92_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [00010000, 04050000, 08090000, 0C0D0000] test_vminub_93_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 04010203] test_vminub_94_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [00010203, 04050607, 00010203, 04050607] test_vminub_95_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vminub_96_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [00010203, 04050607, 00000001, 00020003] test_vminub_97_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [00010203, 00020007, 08090A0B, 0003000F] test_vminub_98_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [00010101, 04050607, 08090A0B, 00000000] test_vminub_99_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [00010203, 00000007, 08090A0B, 0001000F] test_vminub_100_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vminub_101_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_102_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminub_103_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [0000000D, 000D0000, 00000000, 000D0000] test_vminub_104_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010003, 00050007, 0009000B, 000D000D] test_vminub_105_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vminub_106_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [000D0000, 00000000, 0000000D, 000D000D] test_vminub_107_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00040004, 00040004, 00040004, 00040004] test_vminub_108_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00070007, 00070007, 00070007, 00070007] test_vminub_109_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00080008, 00080008, 00080008, 00080008] test_vminub_110_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vminub_111_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vminub_112_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [000D0000, 000D0000, 000D000D, 000D000D] test_vminub_113_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [000D0000, 000D0000, 000D0000, 000D0000] test_vminub_114_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [000D0003, 00050007, 000D000B, 000D000D] test_vminub_115_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [0008000D, 000D0000, 000D000D, 000D000D] test_vminub_116_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [000D0000, 000D0000, 000D000D, 000D000D] test_vminub_117_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [000D0000, 000D0000, 000D0000, 000D0000] test_vminub_118_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 00010003] test_vminub_119_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [000D000D, 000D000D, 00010003, 00050007] test_vminub_120_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vminub_121_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [000D000D, 000D000D, 00000001, 00020003] test_vminub_122_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [000D000D, 0002000D, 000D000D, 0003000D] test_vminub_123_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [000D0001, 000D000D, 000D000D, 00000000] test_vminub_124_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [000D000D, 0000000D, 000D000D, 0001000D] test_vminub_125_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vminub_126_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_127_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminub_128_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00002233, 44550000, 00000000, CCDD0000] test_vminub_129_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vminub_130_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vminub_131_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00112200, 00006600, 880000BB, CCDD00FF] test_vminub_132_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00040404, 04040404, 04040404, 04040404] test_vminub_133_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00070707, 07070707, 07070707, 07070707] test_vminub_134_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00080808, 08080808, 08080808, 08080808] test_vminub_135_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00111212, 12121212, 12121212, 12121212] test_vminub_136_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00112233, 44554321, 11223344, 55667788] test_vminub_137_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [00110000, 3F550000, 3F8CAABB, 3FDD3333] test_vminub_138_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [00110000, 44200000, 41700000, C1700000] test_vminub_139_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00110203, 04050607, 7F800A0B, 0C0D0E0F] test_vminub_140_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [00081010, 44550000, 7F99AABB, 8FDDEEFF] test_vminub_141_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [00110000, 44550000, 888CAABB, BFDD3333] test_vminub_142_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [00110000, 41550000, 88990000, 41DD0000] test_vminub_143_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, 04010203] test_vminub_144_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [00112233, 44556677, 00010203, 04050607] test_vminub_145_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFE] test_vminub_146_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [00112233, 44556677, 00000001, 00020003] test_vminub_147_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [00112233, 00020077, 8899AA7D, 00030082] test_vminub_148_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [00110101, 44556677, 8899AABB, 00000000] test_vminub_149_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [00112233, 00000077, 8899AA7F, 00010080] test_vminub_150_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF] test_vminub_151_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_152_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000000, 00000000, 00000001, 00000001] test_vminub_153_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [0000FF00, 00000000, 00000000, FFFF0000] test_vminub_154_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010200, 00000600, 0800000B, 0C0D000F] test_vminub_155_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [000D0000, 00000000, 0000000D, 000D000D] test_vminub_156_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00112200, 00006600, 880000BB, CCDD00FF] test_vminub_157_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [00040400, 00000400, 04000004, 04040004] test_vminub_158_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [00070700, 00000700, 07000007, 07070007] test_vminub_159_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [00080800, 00000800, 08000008, 08080008] test_vminub_160_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [00121200, 00001200, 12000012, 12120012] test_vminub_161_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [00345600, 00004300, 11000044, 55660088] test_vminub_162_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [00800000, 00000000, 3F0000CD, 3FF30033] test_vminub_163_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [00200000, 00000000, 41000000, C1700000] test_vminub_164_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00800200, 00000600, 7F00000B, 0C0D000F] test_vminub_165_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [00081000, 00000000, 7F0000FF, 8FFF00FF] test_vminub_166_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [00800000, 00000000, BF0000CD, BFF30033] test_vminub_167_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [00200000, 00000000, C1000000, 41F00000] test_vminub_168_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [00CDCD00, 0000CD00, CD0000CD, 04010003] test_vminub_169_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [00F9FA00, 0000FE00, 00000003, 04050007] test_vminub_170_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [00FEFE00, 0000FE00, FE0000FE, FEFE00FE] test_vminub_171_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [00FCFF00, 0000FF00, 00000001, 00020003] test_vminub_172_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [00FDFF00, 00000000, FF00007D, 00030082] test_vminub_173_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [00FF0100, 0000FF00, FF0000FF, 00000000] test_vminub_174_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [00FFFF00, 00000000, FF00007F, 00010080] test_vminub_175_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vminub_176_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_177_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminub_178_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00000404, 04040000, 00000000, 04040000] test_vminub_179_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04040404, 04040404, 04040404] test_vminub_180_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00040004, 00040004, 00040004, 00040004] test_vminub_181_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00040404, 04040404, 04040404, 04040404] test_vminub_182_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00040400, 00000400, 04000004, 04040004] test_vminub_183_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vminub_184_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vminub_185_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vminub_186_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vminub_187_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [04040000, 04040000, 04040404, 04040404] test_vminub_188_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [04040000, 04040000, 04040000, 04040000] test_vminub_189_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [04040203, 04040404, 04040404, 04040404] test_vminub_190_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [04040404, 04040000, 04040404, 04040404] test_vminub_191_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [04040000, 04040000, 04040404, 04040404] test_vminub_192_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [04040000, 04040000, 04040000, 04040000] test_vminub_193_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04010203] test_vminub_194_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [04040404, 04040404, 00010203, 04040404] test_vminub_195_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vminub_196_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [04040404, 04040404, 00000001, 00020003] test_vminub_197_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [04040404, 00020004, 04040404, 00030004] test_vminub_198_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [04040101, 04040404, 04040404, 00000000] test_vminub_199_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [04040404, 00000004, 04040404, 00010004] test_vminub_200_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vminub_201_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_202_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminub_203_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00000707, 07070000, 00000000, 07070000] test_vminub_204_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 07070707, 07070707] test_vminub_205_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00070007, 00070007, 00070007, 00070007] test_vminub_206_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00070707, 07070707, 07070707, 07070707] test_vminub_207_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00070700, 00000700, 07000007, 07070007] test_vminub_208_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vminub_209_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vminub_210_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vminub_211_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vminub_212_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [07070000, 07070000, 07070707, 07070707] test_vminub_213_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [07070000, 07070000, 07070000, 07070000] test_vminub_214_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [07070203, 04050607, 07070707, 07070707] test_vminub_215_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [07070707, 07070000, 07070707, 07070707] test_vminub_216_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [07070000, 07070000, 07070707, 07070707] test_vminub_217_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [07070000, 07070000, 07070000, 07070000] test_vminub_218_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 04010203] test_vminub_219_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [07070707, 07070707, 00010203, 04050607] test_vminub_220_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vminub_221_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [07070707, 07070707, 00000001, 00020003] test_vminub_222_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [07070707, 00020007, 07070707, 00030007] test_vminub_223_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [07070101, 07070707, 07070707, 00000000] test_vminub_224_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [07070707, 00000007, 07070707, 00010007] test_vminub_225_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vminub_226_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_227_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminub_228_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00000808, 08080000, 00000000, 08080000] test_vminub_229_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08080808, 08080808] test_vminub_230_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [00080008, 00080008, 00080008, 00080008] test_vminub_231_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00080808, 08080808, 08080808, 08080808] test_vminub_232_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00080800, 00000800, 08000008, 08080008] test_vminub_233_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vminub_234_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vminub_235_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vminub_236_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vminub_237_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [08080000, 08080000, 08080808, 08080808] test_vminub_238_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [08080000, 08080000, 08080000, 08080000] test_vminub_239_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [08080203, 04050607, 08080808, 08080808] test_vminub_240_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [08080808, 08080000, 08080808, 08080808] test_vminub_241_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [08080000, 08080000, 08080808, 08080808] test_vminub_242_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [08080000, 08080000, 08080000, 08080000] test_vminub_243_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 04010203] test_vminub_244_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [08080808, 08080808, 00010203, 04050607] test_vminub_245_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vminub_246_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [08080808, 08080808, 00000001, 00020003] test_vminub_247_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [08080808, 00020008, 08080808, 00030008] test_vminub_248_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [08080101, 08080808, 08080808, 00000000] test_vminub_249_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [08080808, 00000008, 08080808, 00010008] test_vminub_250_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vminub_251_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_252_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminub_253_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00001212, 12120000, 00000000, 12120000] test_vminub_254_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vminub_255_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vminub_256_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00111212, 12121212, 12121212, 12121212] test_vminub_257_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00121200, 00001200, 12000012, 12120012] test_vminub_258_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vminub_259_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vminub_260_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vminub_261_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [12121212, 12121212, 11121212, 12121212] test_vminub_262_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [12120000, 12120000, 12121212, 12121212] test_vminub_263_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [12120000, 12120000, 12120000, 12120000] test_vminub_264_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [12120203, 04050607, 12120A0B, 0C0D0E0F] test_vminub_265_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [12081010, 12120000, 12121212, 12121212] test_vminub_266_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [12120000, 12120000, 12121212, 12121212] test_vminub_267_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [12120000, 12120000, 12120000, 12120000] test_vminub_268_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 04010203] test_vminub_269_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [12121212, 12121212, 00010203, 04050607] test_vminub_270_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212] test_vminub_271_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [12121212, 12121212, 00000001, 00020003] test_vminub_272_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [12121212, 00020012, 12121212, 00030012] test_vminub_273_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [12120101, 12121212, 12121212, 00000000] test_vminub_274_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [12121212, 00000012, 12121212, 00010012] test_vminub_275_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212] test_vminub_276_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_277_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminub_278_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00005678, 87650000, 00000000, 55660000] test_vminub_279_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vminub_280_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vminub_281_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00112233, 44554321, 11223344, 55667788] test_vminub_282_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00345600, 00004300, 11000044, 55660088] test_vminub_283_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vminub_284_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vminub_285_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vminub_286_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [12121212, 12121212, 11121212, 12121212] test_vminub_287_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [12340000, 3F650000, 11223344, 3F663333] test_vminub_288_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [12200000, 87200000, 11220000, 55660000] test_vminub_289_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [12340203, 04050607, 11220A0B, 0C0D0E0F] test_vminub_290_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [12081010, 80650000, 11223344, 55667788] test_vminub_291_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [12340000, 87650000, 11223344, 55663333] test_vminub_292_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [12200000, 41650000, 11220000, 41660000] test_vminub_293_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 04010203] test_vminub_294_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [12345678, 87654321, 00010203, 04050607] test_vminub_295_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788] test_vminub_296_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [12345678, 87654321, 00000001, 00020003] test_vminub_297_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [12345678, 00020021, 11223344, 00030082] test_vminub_298_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [12340101, 70654321, 11223344, 00000000] test_vminub_299_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [12345678, 00000021, 11223344, 00010080] test_vminub_300_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788] test_vminub_301_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_302_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000000, 00000000, 00000001, 00000001] test_vminub_303_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00000000, 3FC00000, 00000000, 3FF30000] test_vminub_304_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010000, 04050000, 08090A0B, 0C0D0E0F] test_vminub_305_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [000D0000, 000D0000, 000D000D, 000D000D] test_vminub_306_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00110000, 3F550000, 3F8CAABB, 3FDD3333] test_vminub_307_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00800000, 00000000, 3F0000CD, 3FF30033] test_vminub_308_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [04040000, 04040000, 04040404, 04040404] test_vminub_309_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [07070000, 07070000, 07070707, 07070707] test_vminub_310_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [08080000, 08080000, 08080808, 08080808] test_vminub_311_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [12120000, 12120000, 12121212, 12121212] test_vminub_312_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [12340000, 3F650000, 11223344, 3F663333] test_vminub_313_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [3F200000, 3F200000, 3F700000, 3F700000] test_vminub_314_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [3F800000, 04050000, 3F800A0B, 0C0D0E0F] test_vminub_315_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [3F080000, 3F8F0000, 3F8CCCCD, 3FF33333] test_vminub_316_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] test_vminub_317_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [3F200000, 3FA00000, 3F8C0000, 3FF00000] test_vminub_318_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 04010203] test_vminub_319_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 00010203, 04050607] test_vminub_320_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] test_vminub_321_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 00000001, 00020003] test_vminub_322_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [3F800000, 00020000, 3F8CCC7D, 00030033] test_vminub_323_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [3F800000, 3F700000, 3F8CCCCD, 00000000] test_vminub_324_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [3F800000, 00000000, 3F8CCC7F, 00010033] test_vminub_325_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] test_vminub_326_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_327_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_328_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00000000, C1200000, 00000000, C1700000] test_vminub_329_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010000, 04050000, 08090000, 0C0D0000] test_vminub_330_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [000D0000, 000D0000, 000D0000, 000D0000] test_vminub_331_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00110000, 44200000, 41700000, C1700000] test_vminub_332_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00200000, 00000000, 41000000, C1700000] test_vminub_333_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [04040000, 04040000, 04040000, 04040000] test_vminub_334_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [07070000, 07070000, 07070000, 07070000] test_vminub_335_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [08080000, 08080000, 08080000, 08080000] test_vminub_336_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [12120000, 12120000, 12120000, 12120000] test_vminub_337_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [12200000, 87200000, 11220000, 55660000] test_vminub_338_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [3F200000, 3F200000, 3F700000, 3F700000] test_vminub_339_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [41200000, 04050000, 41700000, 0C0D0000] test_vminub_340_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [41080000, 80200000, 41700000, 8F700000] test_vminub_341_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [41200000, BF200000, 41700000, BF700000] test_vminub_342_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [41200000, 41200000, 41700000, 41700000] test_vminub_343_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, 04010000] test_vminub_344_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [41200000, C1200000, 00010000, 04050000] test_vminub_345_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000] test_vminub_346_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [41200000, C1200000, 00000000, 00020000] test_vminub_347_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [41200000, 00020000, 41700000, 00030000] test_vminub_348_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [41200000, 70200000, 41700000, 00000000] test_vminub_349_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [41200000, 00000000, 41700000, 00010000] test_vminub_350_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000] test_vminub_351_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_352_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminub_353_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00000203, 04050000, 00000000, 0C0D0000] test_vminub_354_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vminub_355_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [000D0003, 00050007, 000D000B, 000D000D] test_vminub_356_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00110203, 04050607, 7F800A0B, 0C0D0E0F] test_vminub_357_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00800200, 00000600, 7F00000B, 0C0D000F] test_vminub_358_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [04040203, 04040404, 04040404, 04040404] test_vminub_359_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [07070203, 04050607, 07070707, 07070707] test_vminub_360_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [08080203, 04050607, 08080808, 08080808] test_vminub_361_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [12120203, 04050607, 12120A0B, 0C0D0E0F] test_vminub_362_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [12340203, 04050607, 11220A0B, 0C0D0E0F] test_vminub_363_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [3F800000, 04050000, 3F800A0B, 0C0D0E0F] test_vminub_364_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [41200000, 04050000, 41700000, 0C0D0000] test_vminub_365_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [7F080203, 04050000, 7F800A0B, 0C0D0E0F] test_vminub_366_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [7F800000, 04050000, 7F800A0B, 0C0D0E0F] test_vminub_367_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [7F200000, 04050000, 7F800000, 0C0D0000] test_vminub_368_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 04010203] test_vminub_369_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [7F800203, 04050607, 00010203, 04050607] test_vminub_370_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] test_vminub_371_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [7F800203, 04050607, 00000001, 00020003] test_vminub_372_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [7F800203, 00020007, 7F800A0B, 0003000F] test_vminub_373_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [7F800101, 04050607, 7F800A0B, 00000000] test_vminub_374_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [7F800203, 00000007, 7F800A0B, 0001000F] test_vminub_375_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] test_vminub_376_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_377_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000001, 00000000, 00000001, 00000001] test_vminub_378_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00001010, 808F0000, 00000000, 8FFF0000] test_vminub_379_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050000, 08090A0B, 0C0D0E0F] test_vminub_380_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [0008000D, 000D0000, 000D000D, 000D000D] test_vminub_381_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00081010, 44550000, 7F99AABB, 8FDDEEFF] test_vminub_382_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00081000, 00000000, 7F0000FF, 8FFF00FF] test_vminub_383_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [04040404, 04040000, 04040404, 04040404] test_vminub_384_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [07070707, 07070000, 07070707, 07070707] test_vminub_385_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [08080808, 08080000, 08080808, 08080808] test_vminub_386_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [12081010, 12120000, 12121212, 12121212] test_vminub_387_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [12081010, 80650000, 11223344, 55667788] test_vminub_388_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [3F080000, 3F8F0000, 3F8CCCCD, 3FF33333] test_vminub_389_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [41080000, 80200000, 41700000, 8F700000] test_vminub_390_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7F080203, 04050000, 7F800A0B, 0C0D0E0F] test_vminub_391_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [80080000, 808F0000, 7F8CCCCD, 8FF33333] test_vminub_392_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [80080000, 418F0000, 7FA00000, 41F00000] test_vminub_393_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [80081010, 808F0000, 7FCDCDCD, 04010203] test_vminub_394_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [80081010, 808F0000, 00010203, 04050607] test_vminub_395_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [80081010, 808F0000, 7FFEFEFE, 8FFEFEFE] test_vminub_396_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [80081010, 808F0000, 00000001, 00020003] test_vminub_397_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [80081010, 00020000, 7FFCFF7D, 00030082] test_vminub_398_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [80080101, 70700000, 7FFFFFFF, 00000000] test_vminub_399_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [80081010, 00000000, 7FFEFF7F, 00010080] test_vminub_400_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vminub_401_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_402_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000000, 00000000, 00000001, 00000001] test_vminub_403_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00000000, BFC00000, 00000000, BFF30000] test_vminub_404_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010000, 04050000, 08090A0B, 0C0D0E0F] test_vminub_405_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [000D0000, 000D0000, 000D000D, 000D000D] test_vminub_406_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00110000, 44550000, 888CAABB, BFDD3333] test_vminub_407_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00800000, 00000000, BF0000CD, BFF30033] test_vminub_408_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [04040000, 04040000, 04040404, 04040404] test_vminub_409_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [07070000, 07070000, 07070707, 07070707] test_vminub_410_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [08080000, 08080000, 08080808, 08080808] test_vminub_411_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [12120000, 12120000, 12121212, 12121212] test_vminub_412_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [12340000, 87650000, 11223344, 55663333] test_vminub_413_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] test_vminub_414_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [41200000, BF200000, 41700000, BF700000] test_vminub_415_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7F800000, 04050000, 7F800A0B, 0C0D0E0F] test_vminub_416_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80080000, 808F0000, 7F8CCCCD, 8FF33333] test_vminub_417_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [BF200000, 41A00000, BF8C0000, 41F00000] test_vminub_418_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, 04010203] test_vminub_419_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [BF800000, BFC00000, 00010203, 04050607] test_vminub_420_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminub_421_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [BF800000, BFC00000, 00000001, 00020003] test_vminub_422_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [BF800000, 00020000, BF8CCC7D, 00030033] test_vminub_423_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [BF800000, 70700000, BF8CCCCD, 00000000] test_vminub_424_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [BF800000, 00000000, BF8CCC7F, 00010033] test_vminub_425_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminub_426_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_427_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_428_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00000000, 41A00000, 00000000, 41F00000] test_vminub_429_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010000, 04050000, 08090000, 0C0D0000] test_vminub_430_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [000D0000, 000D0000, 000D0000, 000D0000] test_vminub_431_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00110000, 41550000, 88990000, 41DD0000] test_vminub_432_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00200000, 00000000, C1000000, 41F00000] test_vminub_433_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [04040000, 04040000, 04040000, 04040000] test_vminub_434_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [07070000, 07070000, 07070000, 07070000] test_vminub_435_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [08080000, 08080000, 08080000, 08080000] test_vminub_436_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [12120000, 12120000, 12120000, 12120000] test_vminub_437_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [12200000, 41650000, 11220000, 41660000] test_vminub_438_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [3F200000, 3FA00000, 3F8C0000, 3FF00000] test_vminub_439_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [41200000, 41200000, 41700000, 41700000] test_vminub_440_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7F200000, 04050000, 7F800000, 0C0D0000] test_vminub_441_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80080000, 418F0000, 7FA00000, 41F00000] test_vminub_442_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF200000, 41A00000, BF8C0000, 41F00000] test_vminub_443_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 04010000] test_vminub_444_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [C1200000, 41A00000, 00010000, 04050000] test_vminub_445_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000] test_vminub_446_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [C1200000, 41A00000, 00000000, 00020000] test_vminub_447_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [C1200000, 00020000, C1A00000, 00030000] test_vminub_448_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [C1200000, 41700000, C1A00000, 00000000] test_vminub_449_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [C1200000, 00000000, C1A00000, 00010000] test_vminub_450_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000] test_vminub_451_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_452_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminub_453_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [0000CDCD, CDCD0000, 00000000, 04010000] test_vminub_454_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 04010203] test_vminub_455_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 00010003] test_vminub_456_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, 04010203] test_vminub_457_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00CDCD00, 0000CD00, CD0000CD, 04010003] test_vminub_458_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04010203] test_vminub_459_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 04010203] test_vminub_460_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 04010203] test_vminub_461_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 04010203] test_vminub_462_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 04010203] test_vminub_463_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 04010203] test_vminub_464_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, 04010000] test_vminub_465_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 04010203] test_vminub_466_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80081010, 808F0000, 7FCDCDCD, 04010203] test_vminub_467_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, 04010203] test_vminub_468_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 04010000] test_vminub_469_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, 00010203, 04010203] test_vminub_470_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminub_471_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, 00000001, 00010003] test_vminub_472_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [CDCDCD7E, 00020081, CDCDCD7D, 00010003] test_vminub_473_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [CDCD0101, 7070CDCD, CDCDCDCD, 00000000] test_vminub_474_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [CDCDCD80, 0000007F, CDCDCD7F, 00010003] test_vminub_475_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminub_476_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_477_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminub_478_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [0000FAFB, FCFD0000, 00000000, 04050000] test_vminub_479_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 00010203, 04050607] test_vminub_480_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [000D000D, 000D000D, 00010003, 00050007] test_vminub_481_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00112233, 44556677, 00010203, 04050607] test_vminub_482_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00F9FA00, 0000FE00, 00000003, 04050007] test_vminub_483_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [04040404, 04040404, 00010203, 04040404] test_vminub_484_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [07070707, 07070707, 00010203, 04050607] test_vminub_485_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [08080808, 08080808, 00010203, 04050607] test_vminub_486_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [12121212, 12121212, 00010203, 04050607] test_vminub_487_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [12345678, 87654321, 00010203, 04050607] test_vminub_488_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 00010203, 04050607] test_vminub_489_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [41200000, C1200000, 00010000, 04050000] test_vminub_490_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7F800203, 04050607, 00010203, 04050607] test_vminub_491_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80081010, 808F0000, 00010203, 04050607] test_vminub_492_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, 00010203, 04050607] test_vminub_493_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 41A00000, 00010000, 04050000] test_vminub_494_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, 00010203, 04010203] test_vminub_495_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFE, 00010203, 04050607] test_vminub_496_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00000001, 00020003] test_vminub_497_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [F8F9FA7E, 00020081, 00010203, 00030007] test_vminub_498_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [F8F90101, 7070FEFF, 00010203, 00000000] test_vminub_499_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [F8F9FA80, 0000007F, 00010203, 00010007] test_vminub_500_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vminub_501_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_502_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminub_503_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [0000FEFE, FEFE0000, 00000000, FEFE0000] test_vminub_504_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vminub_505_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vminub_506_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFE] test_vminub_507_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00FEFE00, 0000FE00, FE0000FE, FEFE00FE] test_vminub_508_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vminub_509_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vminub_510_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vminub_511_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212] test_vminub_512_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788] test_vminub_513_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] test_vminub_514_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000] test_vminub_515_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] test_vminub_516_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80081010, 808F0000, 7FFEFEFE, 8FFEFEFE] test_vminub_517_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminub_518_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000] test_vminub_519_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminub_520_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFE, 00010203, 04050607] test_vminub_521_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FEFCFEFD, FEFEFEFE, 00000001, 00020003] test_vminub_522_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FEFDFE7E, 00020081, FEFCFE7D, 00030082] test_vminub_523_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FEFE0101, 7070FEFE, FEFEFEFE, 00000000] test_vminub_524_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FEFEFE80, 0000007F, FEFEFE7F, 00010080] test_vminub_525_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminub_526_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_527_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminub_528_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [0000FFFD, FFFE0000, 00000000, 00020000] test_vminub_529_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 00000001, 00020003] test_vminub_530_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [000D000D, 000D000D, 00000001, 00020003] test_vminub_531_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00112233, 44556677, 00000001, 00020003] test_vminub_532_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00FCFF00, 0000FF00, 00000001, 00020003] test_vminub_533_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [04040404, 04040404, 00000001, 00020003] test_vminub_534_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [07070707, 07070707, 00000001, 00020003] test_vminub_535_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [08080808, 08080808, 00000001, 00020003] test_vminub_536_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [12121212, 12121212, 00000001, 00020003] test_vminub_537_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [12345678, 87654321, 00000001, 00020003] test_vminub_538_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 00000001, 00020003] test_vminub_539_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [41200000, C1200000, 00000000, 00020000] test_vminub_540_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7F800203, 04050607, 00000001, 00020003] test_vminub_541_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80081010, 808F0000, 00000001, 00020003] test_vminub_542_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, 00000001, 00020003] test_vminub_543_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 41A00000, 00000000, 00020000] test_vminub_544_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, 00000001, 00010003] test_vminub_545_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00000001, 00020003] test_vminub_546_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFCFEFD, FEFEFEFE, 00000001, 00020003] test_vminub_547_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFCFF7E, 00020081, 00000001, 00020003] test_vminub_548_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFC0101, 7070FFFF, 00000001, 00000000] test_vminub_549_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFCFF80, 0000007F, 00000001, 00010003] test_vminub_550_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vminub_551_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_552_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminub_553_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [0000FF7E, 00020000, 00000000, 00030000] test_vminub_554_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 00020007, 08090A0B, 0003000F] test_vminub_555_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [000D000D, 0002000D, 000D000D, 0003000D] test_vminub_556_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00112233, 00020077, 8899AA7D, 00030082] test_vminub_557_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00FDFF00, 00000000, FF00007D, 00030082] test_vminub_558_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [04040404, 00020004, 04040404, 00030004] test_vminub_559_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [07070707, 00020007, 07070707, 00030007] test_vminub_560_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [08080808, 00020008, 08080808, 00030008] test_vminub_561_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [12121212, 00020012, 12121212, 00030012] test_vminub_562_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [12345678, 00020021, 11223344, 00030082] test_vminub_563_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [3F800000, 00020000, 3F8CCC7D, 00030033] test_vminub_564_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [41200000, 00020000, 41700000, 00030000] test_vminub_565_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7F800203, 00020007, 7F800A0B, 0003000F] test_vminub_566_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80081010, 00020000, 7FFCFF7D, 00030082] test_vminub_567_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, 00020000, BF8CCC7D, 00030033] test_vminub_568_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 00020000, C1A00000, 00030000] test_vminub_569_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCD7E, 00020081, CDCDCD7D, 00010003] test_vminub_570_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FA7E, 00020081, 00010203, 00030007] test_vminub_571_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFDFE7E, 00020081, FEFCFE7D, 00030082] test_vminub_572_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFF7E, 00020081, 00000001, 00020003] test_vminub_573_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFD0101, 00020081, FFFCFF7D, 00000000] test_vminub_574_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFDFF7E, 0000007F, FFFCFF7D, 00010080] test_vminub_575_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vminub_576_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_577_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000000] test_vminub_578_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [00000101, 70700000, 00000000, 00000000] test_vminub_579_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010101, 04050607, 08090A0B, 00000000] test_vminub_580_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [000D0001, 000D000D, 000D000D, 00000000] test_vminub_581_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00110101, 44556677, 8899AABB, 00000000] test_vminub_582_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00FF0100, 0000FF00, FF0000FF, 00000000] test_vminub_583_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [04040101, 04040404, 04040404, 00000000] test_vminub_584_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [07070101, 07070707, 07070707, 00000000] test_vminub_585_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [08080101, 08080808, 08080808, 00000000] test_vminub_586_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [12120101, 12121212, 12121212, 00000000] test_vminub_587_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [12340101, 70654321, 11223344, 00000000] test_vminub_588_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [3F800000, 3F700000, 3F8CCCCD, 00000000] test_vminub_589_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [41200000, 70200000, 41700000, 00000000] test_vminub_590_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7F800101, 04050607, 7F800A0B, 00000000] test_vminub_591_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80080101, 70700000, 7FFFFFFF, 00000000] test_vminub_592_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, 70700000, BF8CCCCD, 00000000] test_vminub_593_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 41700000, C1A00000, 00000000] test_vminub_594_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCD0101, 7070CDCD, CDCDCDCD, 00000000] test_vminub_595_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F90101, 7070FEFF, 00010203, 00000000] test_vminub_596_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFE0101, 7070FEFE, FEFEFEFE, 00000000] test_vminub_597_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFC0101, 7070FFFF, 00000001, 00000000] test_vminub_598_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFD0101, 00020081, FFFCFF7D, 00000000] test_vminub_599_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFF0101, 0000007F, FFFEFF7F, 00000000] test_vminub_600_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] test_vminub_601_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_602_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminub_603_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [0000FF80, 00000000, 00000000, 00010000] test_vminub_604_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 00000007, 08090A0B, 0001000F] test_vminub_605_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [000D000D, 0000000D, 000D000D, 0001000D] test_vminub_606_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00112233, 00000077, 8899AA7F, 00010080] test_vminub_607_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00FFFF00, 00000000, FF00007F, 00010080] test_vminub_608_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [04040404, 00000004, 04040404, 00010004] test_vminub_609_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [07070707, 00000007, 07070707, 00010007] test_vminub_610_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [08080808, 00000008, 08080808, 00010008] test_vminub_611_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [12121212, 00000012, 12121212, 00010012] test_vminub_612_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [12345678, 00000021, 11223344, 00010080] test_vminub_613_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [3F800000, 00000000, 3F8CCC7F, 00010033] test_vminub_614_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [41200000, 00000000, 41700000, 00010000] test_vminub_615_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7F800203, 00000007, 7F800A0B, 0001000F] test_vminub_616_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80081010, 00000000, 7FFEFF7F, 00010080] test_vminub_617_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, 00000000, BF8CCC7F, 00010033] test_vminub_618_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 00000000, C1A00000, 00010000] test_vminub_619_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCD80, 0000007F, CDCDCD7F, 00010003] test_vminub_620_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FA80, 0000007F, 00010203, 00010007] test_vminub_621_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFE80, 0000007F, FEFEFE7F, 00010080] test_vminub_622_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFF80, 0000007F, 00000001, 00010003] test_vminub_623_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, 0000007F, FFFCFF7D, 00010080] test_vminub_624_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, 0000007F, FFFEFF7F, 00000000] test_vminub_625_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] test_vminub_626_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000] test_vminub_627_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001] test_vminub_628_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000] test_vminub_629_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] test_vminub_630_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D] test_vminub_631_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF] test_vminub_632_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] test_vminub_633_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404] test_vminub_634_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707] test_vminub_635_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808] test_vminub_636_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212] test_vminub_637_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788] test_vminub_638_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] test_vminub_639_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000] test_vminub_640_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] test_vminub_641_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] test_vminub_642_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333] test_vminub_643_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000] test_vminub_644_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] test_vminub_645_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] test_vminub_646_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vminub_647_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] test_vminub_648_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] test_vminub_649_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] test_vminub_650_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vminub v3, v1, v2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]