test_vspltw_1_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] vspltw v2, v1, 0 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] test_vspltw_2_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] vspltw v2, v1, 1 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] test_vspltw_3_GEN: #_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000] vspltw v2, v1, 2 blr #_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] test_vspltw_4_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] vspltw v2, v1, 0 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] test_vspltw_5_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] vspltw v2, v1, 1 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] test_vspltw_6_GEN: #_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001] vspltw v2, v1, 2 blr #_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] test_vspltw_7_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] vspltw v2, v1, 0 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [0000FFFF, 0000FFFF, 0000FFFF, 0000FFFF] test_vspltw_8_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] vspltw v2, v1, 1 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [FFFF0000, FFFF0000, FFFF0000, FFFF0000] test_vspltw_9_GEN: #_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] vspltw v2, v1, 2 blr #_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000] #_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000] test_vspltw_10_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] vspltw v2, v1, 0 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [00010203, 00010203, 00010203, 00010203] test_vspltw_11_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] vspltw v2, v1, 1 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [04050607, 04050607, 04050607, 04050607] test_vspltw_12_GEN: #_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] vspltw v2, v1, 2 blr #_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [08090A0B, 08090A0B, 08090A0B, 08090A0B] test_vspltw_13_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] vspltw v2, v1, 0 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] test_vspltw_14_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] vspltw v2, v1, 1 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] test_vspltw_15_GEN: #_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D] vspltw v2, v1, 2 blr #_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D] #_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D] test_vspltw_16_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] vspltw v2, v1, 0 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [00112233, 00112233, 00112233, 00112233] test_vspltw_17_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] vspltw v2, v1, 1 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [44556677, 44556677, 44556677, 44556677] test_vspltw_18_GEN: #_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF] vspltw v2, v1, 2 blr #_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF] #_ REGISTER_OUT v2 [8899AABB, 8899AABB, 8899AABB, 8899AABB] test_vspltw_19_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vspltw v2, v1, 0 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [00FFFF00, 00FFFF00, 00FFFF00, 00FFFF00] test_vspltw_20_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vspltw v2, v1, 1 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [0000FF00, 0000FF00, 0000FF00, 0000FF00] test_vspltw_21_GEN: #_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] vspltw v2, v1, 2 blr #_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF] #_ REGISTER_OUT v2 [FF0000FF, FF0000FF, FF0000FF, FF0000FF] test_vspltw_22_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] vspltw v2, v1, 0 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] test_vspltw_23_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] vspltw v2, v1, 1 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] test_vspltw_24_GEN: #_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404] vspltw v2, v1, 2 blr #_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404] #_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404] test_vspltw_25_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] vspltw v2, v1, 0 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] test_vspltw_26_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] vspltw v2, v1, 1 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] test_vspltw_27_GEN: #_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707] vspltw v2, v1, 2 blr #_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707] #_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707] test_vspltw_28_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] vspltw v2, v1, 0 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] test_vspltw_29_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] vspltw v2, v1, 1 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] test_vspltw_30_GEN: #_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808] vspltw v2, v1, 2 blr #_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808] #_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808] test_vspltw_31_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] vspltw v2, v1, 0 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] test_vspltw_32_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] vspltw v2, v1, 1 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] test_vspltw_33_GEN: #_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212] vspltw v2, v1, 2 blr #_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212] #_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212] test_vspltw_34_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] vspltw v2, v1, 0 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [12345678, 12345678, 12345678, 12345678] test_vspltw_35_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] vspltw v2, v1, 1 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [87654321, 87654321, 87654321, 87654321] test_vspltw_36_GEN: #_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788] vspltw v2, v1, 2 blr #_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788] #_ REGISTER_OUT v2 [11223344, 11223344, 11223344, 11223344] test_vspltw_37_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vspltw v2, v1, 0 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [3F800000, 3F800000, 3F800000, 3F800000] test_vspltw_38_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vspltw v2, v1, 1 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [3FC00000, 3FC00000, 3FC00000, 3FC00000] test_vspltw_39_GEN: #_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] vspltw v2, v1, 2 blr #_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333] #_ REGISTER_OUT v2 [3F8CCCCD, 3F8CCCCD, 3F8CCCCD, 3F8CCCCD] test_vspltw_40_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] vspltw v2, v1, 0 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [41200000, 41200000, 41200000, 41200000] test_vspltw_41_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] vspltw v2, v1, 1 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [C1200000, C1200000, C1200000, C1200000] test_vspltw_42_GEN: #_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000] vspltw v2, v1, 2 blr #_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000] #_ REGISTER_OUT v2 [41700000, 41700000, 41700000, 41700000] test_vspltw_43_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vspltw v2, v1, 0 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [7F800203, 7F800203, 7F800203, 7F800203] test_vspltw_44_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vspltw v2, v1, 1 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [04050607, 04050607, 04050607, 04050607] test_vspltw_45_GEN: #_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] vspltw v2, v1, 2 blr #_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F] #_ REGISTER_OUT v2 [7F800A0B, 7F800A0B, 7F800A0B, 7F800A0B] test_vspltw_46_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vspltw v2, v1, 0 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [80081010, 80081010, 80081010, 80081010] test_vspltw_47_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vspltw v2, v1, 1 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [808F0000, 808F0000, 808F0000, 808F0000] test_vspltw_48_GEN: #_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] vspltw v2, v1, 2 blr #_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF] #_ REGISTER_OUT v2 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF] test_vspltw_49_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] vspltw v2, v1, 0 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [BF800000, BF800000, BF800000, BF800000] test_vspltw_50_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] vspltw v2, v1, 1 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [BFC00000, BFC00000, BFC00000, BFC00000] test_vspltw_51_GEN: #_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] vspltw v2, v1, 2 blr #_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333] #_ REGISTER_OUT v2 [BF8CCCCD, BF8CCCCD, BF8CCCCD, BF8CCCCD] test_vspltw_52_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] vspltw v2, v1, 0 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [C1200000, C1200000, C1200000, C1200000] test_vspltw_53_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] vspltw v2, v1, 1 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [41A00000, 41A00000, 41A00000, 41A00000] test_vspltw_54_GEN: #_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000] vspltw v2, v1, 2 blr #_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000] #_ REGISTER_OUT v2 [C1A00000, C1A00000, C1A00000, C1A00000] test_vspltw_55_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vspltw v2, v1, 0 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD] test_vspltw_56_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vspltw v2, v1, 1 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD] test_vspltw_57_GEN: #_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] vspltw v2, v1, 2 blr #_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203] #_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD] test_vspltw_58_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vspltw v2, v1, 0 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [F8F9FAFB, F8F9FAFB, F8F9FAFB, F8F9FAFB] test_vspltw_59_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vspltw v2, v1, 1 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [FCFDFEFF, FCFDFEFF, FCFDFEFF, FCFDFEFF] test_vspltw_60_GEN: #_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] vspltw v2, v1, 2 blr #_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607] #_ REGISTER_OUT v2 [00010203, 00010203, 00010203, 00010203] test_vspltw_61_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vspltw v2, v1, 0 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vspltw_62_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vspltw v2, v1, 1 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vspltw_63_GEN: #_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] vspltw v2, v1, 2 blr #_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] #_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE] test_vspltw_64_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vspltw v2, v1, 0 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FFFCFFFD, FFFCFFFD, FFFCFFFD, FFFCFFFD] test_vspltw_65_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vspltw v2, v1, 1 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [FFFEFFFF, FFFEFFFF, FFFEFFFF, FFFEFFFF] test_vspltw_66_GEN: #_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] vspltw v2, v1, 2 blr #_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003] #_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001] test_vspltw_67_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vspltw v2, v1, 0 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FFFDFF7E, FFFDFF7E, FFFDFF7E, FFFDFF7E] test_vspltw_68_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vspltw v2, v1, 1 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [00020081, 00020081, 00020081, 00020081] test_vspltw_69_GEN: #_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] vspltw v2, v1, 2 blr #_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082] #_ REGISTER_OUT v2 [FFFCFF7D, FFFCFF7D, FFFCFF7D, FFFCFF7D] test_vspltw_70_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vspltw v2, v1, 0 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FFFF0101, FFFF0101, FFFF0101, FFFF0101] test_vspltw_71_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vspltw v2, v1, 1 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [7070FFFF, 7070FFFF, 7070FFFF, 7070FFFF] test_vspltw_72_GEN: #_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] vspltw v2, v1, 2 blr #_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vspltw_73_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vspltw v2, v1, 0 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FFFFFF80, FFFFFF80, FFFFFF80, FFFFFF80] test_vspltw_74_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vspltw v2, v1, 1 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [0000007F, 0000007F, 0000007F, 0000007F] test_vspltw_75_GEN: #_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] vspltw v2, v1, 2 blr #_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080] #_ REGISTER_OUT v2 [FFFEFF7F, FFFEFF7F, FFFEFF7F, FFFEFF7F] test_vspltw_76_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vspltw v2, v1, 0 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vspltw_77_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vspltw v2, v1, 1 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] test_vspltw_78_GEN: #_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] vspltw v2, v1, 2 blr #_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF] #_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]