Files
Xenia-Canary/src/xenia/cpu/frontend/test/bin/instr_slw.dis
2015-05-13 18:04:33 -07:00

92 lines
3.0 KiB
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Disassembly of section .text:
0000000000100000 <test_slw_1>:
100000: 7c 83 28 30 slw r3,r4,r5
100004: 4e 80 00 20 blr
0000000000100008 <test_slw_1_constant>:
100008: 38 80 00 01 li r4,1
10000c: 38 a0 00 00 li r5,0
100010: 7c 83 28 30 slw r3,r4,r5
100014: 4e 80 00 20 blr
0000000000100018 <test_slw_2>:
100018: 7c 83 28 30 slw r3,r4,r5
10001c: 4e 80 00 20 blr
0000000000100020 <test_slw_2_constant>:
100020: 38 80 ff ff li r4,-1
100024: 38 a0 00 00 li r5,0
100028: 7c 83 28 30 slw r3,r4,r5
10002c: 4e 80 00 20 blr
0000000000100030 <test_slw_3>:
100030: 7c 83 28 30 slw r3,r4,r5
100034: 4e 80 00 20 blr
0000000000100038 <test_slw_3_constant>:
100038: 38 80 ff ff li r4,-1
10003c: 38 a0 00 01 li r5,1
100040: 7c 83 28 30 slw r3,r4,r5
100044: 4e 80 00 20 blr
0000000000100048 <test_slw_4>:
100048: 7c 83 28 30 slw r3,r4,r5
10004c: 4e 80 00 20 blr
0000000000100050 <test_slw_4_constant>:
100050: 38 80 ff ff li r4,-1
100054: 38 a0 00 3f li r5,63
100058: 7c 83 28 30 slw r3,r4,r5
10005c: 4e 80 00 20 blr
0000000000100060 <test_slw_5>:
100060: 7c 83 28 30 slw r3,r4,r5
100064: 4e 80 00 20 blr
0000000000100068 <test_slw_5_constant>:
100068: 38 80 ff ff li r4,-1
10006c: 38 a0 00 40 li r5,64
100070: 7c 83 28 30 slw r3,r4,r5
100074: 4e 80 00 20 blr
0000000000100078 <test_slw_6>:
100078: 7c 83 28 30 slw r3,r4,r5
10007c: 4e 80 00 20 blr
0000000000100080 <test_slw_6_constant>:
100080: 38 80 ff ff li r4,-1
100084: 38 a0 00 64 li r5,100
100088: 7c 83 28 30 slw r3,r4,r5
10008c: 4e 80 00 20 blr
0000000000100090 <test_slw_7>:
100090: 7c 83 28 30 slw r3,r4,r5
100094: 4e 80 00 20 blr
0000000000100098 <test_slw_7_constant>:
100098: 38 80 ff ff li r4,-1
10009c: 38 a0 00 1e li r5,30
1000a0: 7c 83 28 30 slw r3,r4,r5
1000a4: 4e 80 00 20 blr
00000000001000a8 <test_slw_8>:
1000a8: 7c 83 28 30 slw r3,r4,r5
1000ac: 4e 80 00 20 blr
00000000001000b0 <test_slw_8_constant>:
1000b0: 38 80 ff ff li r4,-1
1000b4: 38 a0 00 1f li r5,31
1000b8: 7c 83 28 30 slw r3,r4,r5
1000bc: 4e 80 00 20 blr
00000000001000c0 <test_slw_9>:
1000c0: 7c 83 28 30 slw r3,r4,r5
1000c4: 4e 80 00 20 blr
00000000001000c8 <test_slw_9_constant>:
1000c8: 38 80 ff ff li r4,-1
1000cc: 38 a0 00 20 li r5,32
1000d0: 7c 83 28 30 slw r3,r4,r5
1000d4: 4e 80 00 20 blr