731 lines
20 KiB
C++
731 lines
20 KiB
C++
/*
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******************************************************************************
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* Xenia : Xbox 360 Emulator Research Project *
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******************************************************************************
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* Copyright 2013 Ben Vanik. All rights reserved. *
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* Released under the BSD license - see LICENSE in the root for more details. *
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******************************************************************************
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*/
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#include <xenia/cpu/x64/x64_emit.h>
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#include <xenia/cpu/cpu-private.h>
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using namespace xe::cpu;
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using namespace xe::cpu::ppc;
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using namespace xe::cpu::sdb;
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using namespace AsmJit;
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namespace xe {
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namespace cpu {
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namespace x64 {
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int XeEmitIndirectBranchTo(
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X64Emitter& e, X86Compiler& c, const char* src, uint32_t cia,
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bool lk, uint32_t reg) {
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// TODO(benvanik): run a DFA pass to see if we can detect whether this is
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// a normal function return that is pulling the LR from the stack that
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// it set in the prolog. If so, we can omit the dynamic check!
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// NOTE: we avoid spilling registers until we know that the target is not
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// a basic block within this function.
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GpVar target;
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switch (reg) {
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case kXEPPCRegLR:
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target = e.lr_value();
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break;
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case kXEPPCRegCTR:
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target = e.ctr_value();
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break;
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default:
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XEASSERTALWAYS();
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return 1;
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}
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// Dynamic test when branching to LR, which is usually used for the return.
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// We only do this if LK=0 as returns wouldn't set LR.
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// Ideally it's a return and we can just do a simple ret and be done.
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// If it's not, we fall through to the full indirection logic.
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if (!lk && reg == kXEPPCRegLR) {
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// The return block will spill registers for us.
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// TODO(benvanik): 'lr_mismatch' debug info.
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// Note: we need to test on *only* the 32-bit target, as the target ptr may
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// have garbage in the upper 32 bits.
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c.test(target.r32(), c.getGpArg(1).r32());
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// TODO(benvanik): evaluate hint here.
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c.jnz(e.GetReturnLabel(), kCondHintLikely);
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}
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// Defer to the generator, which will do fancy things.
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bool likely_local = !lk && reg == kXEPPCRegCTR;
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return e.GenerateIndirectionBranch(cia, target, lk, likely_local);
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}
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int XeEmitBranchTo(
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X64Emitter& e, X86Compiler& c, const char* src, uint32_t cia,
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bool lk, GpVar* condition = NULL) {
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FunctionBlock* fn_block = e.fn_block();
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// Fast-path for branches to other blocks.
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// Only valid when not tracing branches.
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if (!FLAGS_trace_branches &&
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fn_block->outgoing_type == FunctionBlock::kTargetBlock) {
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XEASSERT(!lk);
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Label target_label = e.GetBlockLabel(fn_block->outgoing_address);
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if (condition) {
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// Fast test -- if condition passed then jump to target.
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// TODO(benvanik): need to spill here? somehow?
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c.test((*condition).r8(), (*condition).r8());
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c.jnz(target_label);
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} else {
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// TODO(benvanik): need to spill here?
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//e.SpillRegisters();
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c.jmp(target_label);
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}
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return 0;
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}
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// Only branch of conditionals when we have one.
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Label post_jump_label;
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if (condition) {
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// TODO(benvanik): add debug info for this?
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post_jump_label = c.newLabel();
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c.test((*condition).r8(), (*condition).r8());
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// TODO(benvanik): experiment with various hints?
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c.jz(post_jump_label, kCondHintNone);
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}
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e.TraceBranch(cia);
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// Get the basic block and switch behavior based on outgoing type.
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int result = 0;
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switch (fn_block->outgoing_type) {
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case FunctionBlock::kTargetBlock:
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// Often taken care of above, when not tracing branches.
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XEASSERT(!lk);
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c.jmp(e.GetBlockLabel(fn_block->outgoing_address));
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break;
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case FunctionBlock::kTargetFunction:
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{
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// Spill all registers to memory.
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// TODO(benvanik): only spill ones used by the target function? Use
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// calling convention flags on the function to not spill temp
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// registers?
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e.SpillRegisters();
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XEASSERTNOTNULL(fn_block->outgoing_function);
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// TODO(benvanik): check to see if this is the last block in the function.
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// This would enable tail calls/etc.
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bool is_end = false;
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if (!lk || is_end) {
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// Tail. No need to refill the local register values, just return.
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// We optimize this by passing in the LR from our parent instead of the
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// next instruction. This allows the return from our callee to pop
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// all the way up.
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e.CallFunction(fn_block->outgoing_function, c.getGpArg(1), true);
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// No ret needed - we jumped!
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} else {
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// Will return here eventually.
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// Refill registers from state.
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GpVar lr(c.newGpVar());
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c.mov(lr, imm(cia + 4));
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e.CallFunction(fn_block->outgoing_function, lr, false);
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e.FillRegisters();
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}
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break;
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}
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case FunctionBlock::kTargetLR:
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{
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// An indirect jump.
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printf("INDIRECT JUMP VIA LR: %.8X\n", cia);
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result = XeEmitIndirectBranchTo(e, c, src, cia, lk, kXEPPCRegLR);
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break;
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}
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case FunctionBlock::kTargetCTR:
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{
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// An indirect jump.
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printf("INDIRECT JUMP VIA CTR: %.8X\n", cia);
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result = XeEmitIndirectBranchTo(e, c, src, cia, lk, kXEPPCRegCTR);
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break;
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}
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default:
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case FunctionBlock::kTargetNone:
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XEASSERTALWAYS();
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result = 1;
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break;
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}
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if (condition) {
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c.bind(post_jump_label);
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}
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return result;
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}
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XEEMITTER(bx, 0x48000000, I )(X64Emitter& e, X86Compiler& c, InstrData& i) {
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// if AA then
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// NIA <- EXTS(LI || 0b00)
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// else
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// NIA <- CIA + EXTS(LI || 0b00)
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// if LK then
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// LR <- CIA + 4
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uint32_t nia;
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if (i.I.AA) {
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nia = XEEXTS26(i.I.LI << 2);
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} else {
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nia = i.address + XEEXTS26(i.I.LI << 2);
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}
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if (i.I.LK) {
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e.update_lr_value(imm(i.address + 4));
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}
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return XeEmitBranchTo(e, c, "bx", i.address, i.I.LK);
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}
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XEEMITTER(bcx, 0x40000000, B )(X64Emitter& e, X86Compiler& c, InstrData& i) {
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// if ¬BO[2] then
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// CTR <- CTR - 1
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// ctr_ok <- BO[2] | ((CTR[0:63] != 0) XOR BO[3])
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// cond_ok <- BO[0] | (CR[BI+32] ≡ BO[1])
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// if ctr_ok & cond_ok then
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// if AA then
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// NIA <- EXTS(BD || 0b00)
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// else
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// NIA <- CIA + EXTS(BD || 0b00)
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// if LK then
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// LR <- CIA + 4
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// NOTE: the condition bits are reversed!
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// 01234 (docs)
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// 43210 (real)
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// TODO(benvanik): this may be wrong and overwrite LRs when not desired!
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// The docs say always, though...
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if (i.B.LK) {
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e.update_lr_value(imm(i.address + 4));
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}
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// TODO(benvanik): optimize to just use x64 ops.
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// Need to handle the case where both ctr and cond set.
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GpVar ctr_ok;
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if (XESELECTBITS(i.B.BO, 2, 2)) {
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// Ignore ctr.
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} else {
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// Decrement counter.
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GpVar ctr(c.newGpVar());
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c.mov(ctr, e.ctr_value());
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c.dec(ctr);
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e.update_ctr_value(ctr);
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// Ctr check.
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c.cmp(ctr, imm(0));
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ctr_ok = c.newGpVar();
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if (XESELECTBITS(i.B.BO, 1, 1)) {
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c.setz(ctr_ok.r8());
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} else {
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c.setnz(ctr_ok.r8());
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}
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}
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GpVar cond_ok;
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if (XESELECTBITS(i.B.BO, 4, 4)) {
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// Ignore cond.
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} else {
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GpVar cr(c.newGpVar());
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c.mov(cr, e.cr_value(i.XL.BI >> 2));
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c.and_(cr, imm(1 << (i.XL.BI & 3)));
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c.cmp(cr, imm(0));
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cond_ok = c.newGpVar();
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if (XESELECTBITS(i.XL.BO, 3, 3)) {
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c.setnz(cond_ok.r8());
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} else {
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c.setz(cond_ok.r8());
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}
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}
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// We do a bit of optimization here to make the llvm assembly easier to read.
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GpVar* ok = NULL;
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if (ctr_ok.getId() != kInvalidValue && cond_ok.getId() != kInvalidValue) {
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c.and_(ctr_ok, cond_ok);
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ok = &ctr_ok;
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} else if (ctr_ok.getId() != kInvalidValue) {
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ok = &ctr_ok;
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} else if (cond_ok.getId() != kInvalidValue) {
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ok = &cond_ok;
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}
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uint32_t nia;
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if (i.B.AA) {
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nia = XEEXTS26(i.B.BD << 2);
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} else {
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nia = i.address + XEEXTS26(i.B.BD << 2);
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}
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if (XeEmitBranchTo(e, c, "bcx", i.address, i.B.LK, ok)) {
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return 1;
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}
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return 0;
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}
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XEEMITTER(bcctrx, 0x4C000420, XL )(X64Emitter& e, X86Compiler& c, InstrData& i) {
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// cond_ok <- BO[0] | (CR[BI+32] ≡ BO[1])
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// if cond_ok then
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// NIA <- CTR[0:61] || 0b00
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// if LK then
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// LR <- CIA + 4
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// NOTE: the condition bits are reversed!
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// 01234 (docs)
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// 43210 (real)
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// TODO(benvanik): this may be wrong and overwrite LRs when not desired!
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// The docs say always, though...
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if (i.XL.LK) {
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e.update_lr_value(imm(i.address + 4));
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}
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GpVar cond_ok;
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if (XESELECTBITS(i.XL.BO, 4, 4)) {
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// Ignore cond.
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} else {
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GpVar cr(c.newGpVar());
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c.mov(cr, e.cr_value(i.XL.BI >> 2));
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c.and_(cr, imm(1 << (i.XL.BI & 3)));
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c.cmp(cr, imm(0));
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cond_ok = c.newGpVar();
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if (XESELECTBITS(i.XL.BO, 3, 3)) {
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c.setnz(cond_ok.r8());
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} else {
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c.setz(cond_ok.r8());
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}
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}
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// We do a bit of optimization here to make the llvm assembly easier to read.
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GpVar* ok = NULL;
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if (cond_ok.getId() != kInvalidValue) {
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ok = &cond_ok;
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}
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if (XeEmitBranchTo(e, c, "bcctrx", i.address, i.XL.LK, ok)) {
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return 1;
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}
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return 0;
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}
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XEEMITTER(bclrx, 0x4C000020, XL )(X64Emitter& e, X86Compiler& c, InstrData& i) {
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// if ¬BO[2] then
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// CTR <- CTR - 1
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// ctr_ok <- BO[2] | ((CTR[0:63] != 0) XOR BO[3]
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// cond_ok <- BO[0] | (CR[BI+32] ≡ BO[1])
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// if ctr_ok & cond_ok then
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// NIA <- LR[0:61] || 0b00
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// if LK then
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// LR <- CIA + 4
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// NOTE: the condition bits are reversed!
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// 01234 (docs)
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// 43210 (real)
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// TODO(benvanik): this may be wrong and overwrite LRs when not desired!
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// The docs say always, though...
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if (i.XL.LK) {
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e.update_lr_value(imm(i.address + 4));
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}
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GpVar ctr_ok;
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if (XESELECTBITS(i.XL.BO, 2, 2)) {
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// Ignore ctr.
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} else {
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// Decrement counter.
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GpVar ctr(c.newGpVar());
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c.mov(ctr, e.ctr_value());
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c.dec(ctr);
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e.update_ctr_value(ctr);
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// Ctr check.
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c.cmp(ctr, imm(0));
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ctr_ok = c.newGpVar();
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if (XESELECTBITS(i.XL.BO, 1, 1)) {
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c.setz(ctr_ok.r8());
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} else {
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c.setnz(ctr_ok.r8());
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}
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}
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GpVar cond_ok;
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if (XESELECTBITS(i.XL.BO, 4, 4)) {
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// Ignore cond.
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} else {
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GpVar cr(c.newGpVar());
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c.mov(cr, e.cr_value(i.XL.BI >> 2));
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c.and_(cr, imm(1 << (i.XL.BI & 3)));
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c.cmp(cr, imm(0));
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cond_ok = c.newGpVar();
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if (XESELECTBITS(i.XL.BO, 3, 3)) {
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c.setnz(cond_ok.r8());
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} else {
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c.setz(cond_ok.r8());
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}
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}
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// We do a bit of optimization here to make the llvm assembly easier to read.
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GpVar* ok = NULL;
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if (ctr_ok.getId() != kInvalidValue && cond_ok.getId() != kInvalidValue) {
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c.and_(ctr_ok, cond_ok);
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ok = &ctr_ok;
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} else if (ctr_ok.getId() != kInvalidValue) {
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ok = &ctr_ok;
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} else if (cond_ok.getId() != kInvalidValue) {
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ok = &cond_ok;
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}
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if (XeEmitBranchTo(e, c, "bclrx", i.address, i.XL.LK, ok)) {
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return 1;
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}
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return 0;
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}
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// Condition register logical (A-23)
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XEEMITTER(crand, 0x4C000202, XL )(X64Emitter& e, X86Compiler& c, InstrData& i) {
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XEINSTRNOTIMPLEMENTED();
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return 1;
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}
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XEEMITTER(crandc, 0x4C000102, XL )(X64Emitter& e, X86Compiler& c, InstrData& i) {
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XEINSTRNOTIMPLEMENTED();
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return 1;
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}
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XEEMITTER(creqv, 0x4C000242, XL )(X64Emitter& e, X86Compiler& c, InstrData& i) {
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XEINSTRNOTIMPLEMENTED();
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return 1;
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}
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XEEMITTER(crnand, 0x4C0001C2, XL )(X64Emitter& e, X86Compiler& c, InstrData& i) {
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XEINSTRNOTIMPLEMENTED();
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return 1;
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}
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XEEMITTER(crnor, 0x4C000042, XL )(X64Emitter& e, X86Compiler& c, InstrData& i) {
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XEINSTRNOTIMPLEMENTED();
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return 1;
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}
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XEEMITTER(cror, 0x4C000382, XL )(X64Emitter& e, X86Compiler& c, InstrData& i) {
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XEINSTRNOTIMPLEMENTED();
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return 1;
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}
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XEEMITTER(crorc, 0x4C000342, XL )(X64Emitter& e, X86Compiler& c, InstrData& i) {
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XEINSTRNOTIMPLEMENTED();
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return 1;
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}
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XEEMITTER(crxor, 0x4C000182, XL )(X64Emitter& e, X86Compiler& c, InstrData& i) {
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XEINSTRNOTIMPLEMENTED();
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return 1;
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}
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XEEMITTER(mcrf, 0x4C000000, XL )(X64Emitter& e, X86Compiler& c, InstrData& i) {
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XEINSTRNOTIMPLEMENTED();
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return 1;
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}
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// System linkage (A-24)
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XEEMITTER(sc, 0x44000002, SC )(X64Emitter& e, X86Compiler& c, InstrData& i) {
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XEINSTRNOTIMPLEMENTED();
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return 1;
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}
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// Trap (A-25)
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int XeEmitTrap(X64Emitter& e, X86Compiler& c, InstrData& i,
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GpVar& va, GpVar& vb, uint32_t TO) {
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// if (a < b) & TO[0] then TRAP
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// if (a > b) & TO[1] then TRAP
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// if (a = b) & TO[2] then TRAP
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// if (a <u b) & TO[3] then TRAP
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// if (a >u b) & TO[4] then TRAP
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// Bits swapped:
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// 01234
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// 43210
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if (!TO) {
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return 0;
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}
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XELOGCPU("twi not implemented - instruction ignored");
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// TODO(benvanik): port from LLVM
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// BasicBlock* after_bb = BasicBlock::Create(*e.context(), "", e.fn(),
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// e.GetNextBasicBlock());
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// BasicBlock* trap_bb = BasicBlock::Create(*e.context(), "", e.fn(),
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// after_bb);
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// // Create the basic blocks (so we can chain).
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// std::vector<BasicBlock*> bbs;
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// if (TO & (1 << 4)) {
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// bbs.push_back(BasicBlock::Create(*e.context(), "", e.fn(), trap_bb));
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// }
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// if (TO & (1 << 3)) {
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// bbs.push_back(BasicBlock::Create(*e.context(), "", e.fn(), trap_bb));
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// }
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// if (TO & (1 << 2)) {
|
|
// bbs.push_back(BasicBlock::Create(*e.context(), "", e.fn(), trap_bb));
|
|
// }
|
|
// if (TO & (1 << 1)) {
|
|
// bbs.push_back(BasicBlock::Create(*e.context(), "", e.fn(), trap_bb));
|
|
// }
|
|
// if (TO & (1 << 0)) {
|
|
// bbs.push_back(BasicBlock::Create(*e.context(), "", e.fn(), trap_bb));
|
|
// }
|
|
// bbs.push_back(after_bb);
|
|
|
|
// // Jump to the first bb.
|
|
// b.CreateBr(bbs.front());
|
|
|
|
// // Setup each basic block.
|
|
// std::vector<BasicBlock*>::iterator it = bbs.begin();
|
|
// if (TO & (1 << 4)) {
|
|
// // a < b
|
|
// BasicBlock* bb = *(it++);
|
|
// b.SetInsertPoint(bb);
|
|
// GpVar cmp = b.CreateICmpSLT(va, vb);
|
|
// b.CreateCondBr(cmp, trap_bb, *it);
|
|
// }
|
|
// if (TO & (1 << 3)) {
|
|
// // a > b
|
|
// BasicBlock* bb = *(it++);
|
|
// b.SetInsertPoint(bb);
|
|
// GpVar cmp = b.CreateICmpSGT(va, vb);
|
|
// b.CreateCondBr(cmp, trap_bb, *it);
|
|
// }
|
|
// if (TO & (1 << 2)) {
|
|
// // a = b
|
|
// BasicBlock* bb = *(it++);
|
|
// b.SetInsertPoint(bb);
|
|
// GpVar cmp = b.CreateICmpEQ(va, vb);
|
|
// b.CreateCondBr(cmp, trap_bb, *it);
|
|
// }
|
|
// if (TO & (1 << 1)) {
|
|
// // a <u b
|
|
// BasicBlock* bb = *(it++);
|
|
// b.SetInsertPoint(bb);
|
|
// GpVar cmp = b.CreateICmpULT(va, vb);
|
|
// b.CreateCondBr(cmp, trap_bb, *it);
|
|
// }
|
|
// if (TO & (1 << 0)) {
|
|
// // a >u b
|
|
// BasicBlock* bb = *(it++);
|
|
// b.SetInsertPoint(bb);
|
|
// GpVar cmp = b.CreateICmpUGT(va, vb);
|
|
// b.CreateCondBr(cmp, trap_bb, *it);
|
|
// }
|
|
|
|
// // Create trap BB.
|
|
// b.SetInsertPoint(trap_bb);
|
|
// e.SpillRegisters();
|
|
// // TODO(benvanik): use @llvm.debugtrap? could make debugging better
|
|
// b.CreateCall2(e.gen_module()->getFunction("XeTrap"),
|
|
// e.fn()->arg_begin(),
|
|
// e.get_uint64(i.address));
|
|
// b.CreateBr(after_bb);
|
|
|
|
// // Resume.
|
|
// b.SetInsertPoint(after_bb);
|
|
|
|
return 1;
|
|
}
|
|
|
|
XEEMITTER(td, 0x7C000088, X )(X64Emitter& e, X86Compiler& c, InstrData& i) {
|
|
// a <- (RA)
|
|
// b <- (RB)
|
|
// if (a < b) & TO[0] then TRAP
|
|
// if (a > b) & TO[1] then TRAP
|
|
// if (a = b) & TO[2] then TRAP
|
|
// if (a <u b) & TO[3] then TRAP
|
|
// if (a >u b) & TO[4] then TRAP
|
|
GpVar va = e.gpr_value(i.X.RA);
|
|
GpVar vb = e.gpr_value(i.X.RA);
|
|
return XeEmitTrap(e, c, i, va, vb, i.X.RT);
|
|
}
|
|
|
|
XEEMITTER(tdi, 0x08000000, D )(X64Emitter& e, X86Compiler& c, InstrData& i) {
|
|
// a <- (RA)
|
|
// if (a < EXTS(SI)) & TO[0] then TRAP
|
|
// if (a > EXTS(SI)) & TO[1] then TRAP
|
|
// if (a = EXTS(SI)) & TO[2] then TRAP
|
|
// if (a <u EXTS(SI)) & TO[3] then TRAP
|
|
// if (a >u EXTS(SI)) & TO[4] then TRAP
|
|
GpVar va = e.gpr_value(i.D.RA);
|
|
GpVar vb(c.newGpVar());
|
|
c.mov(vb, imm(XEEXTS16(i.D.DS)));
|
|
return XeEmitTrap(e, c, i, va, vb, i.D.RT);
|
|
}
|
|
|
|
XEEMITTER(tw, 0x7C000008, X )(X64Emitter& e, X86Compiler& c, InstrData& i) {
|
|
// a <- EXTS((RA)[32:63])
|
|
// b <- EXTS((RB)[32:63])
|
|
// if (a < b) & TO[0] then TRAP
|
|
// if (a > b) & TO[1] then TRAP
|
|
// if (a = b) & TO[2] then TRAP
|
|
// if (a <u b) & TO[3] then TRAP
|
|
// if (a >u b) & TO[4] then TRAP
|
|
GpVar va = e.sign_extend(e.gpr_value(i.X.RA), 4, 8);
|
|
GpVar vb = e.sign_extend(e.gpr_value(i.X.RA), 4, 8);
|
|
return XeEmitTrap(e, c, i, va, vb, i.X.RT);
|
|
}
|
|
|
|
XEEMITTER(twi, 0x0C000000, D )(X64Emitter& e, X86Compiler& c, InstrData& i) {
|
|
// a <- EXTS((RA)[32:63])
|
|
// if (a < EXTS(SI)) & TO[0] then TRAP
|
|
// if (a > EXTS(SI)) & TO[1] then TRAP
|
|
// if (a = EXTS(SI)) & TO[2] then TRAP
|
|
// if (a <u EXTS(SI)) & TO[3] then TRAP
|
|
// if (a >u EXTS(SI)) & TO[4] then TRAP
|
|
GpVar va = e.sign_extend(e.gpr_value(i.D.RA), 4, 8);
|
|
GpVar vb(c.newGpVar());
|
|
c.mov(vb, imm(XEEXTS16(i.D.DS)));
|
|
return XeEmitTrap(e, c, i, va, vb, i.D.RT);
|
|
}
|
|
|
|
|
|
// Processor control (A-26)
|
|
|
|
XEEMITTER(mfcr, 0x7C000026, X )(X64Emitter& e, X86Compiler& c, InstrData& i) {
|
|
XEINSTRNOTIMPLEMENTED();
|
|
return 1;
|
|
}
|
|
|
|
XEEMITTER(mfspr, 0x7C0002A6, XFX)(X64Emitter& e, X86Compiler& c, InstrData& i) {
|
|
// n <- spr[5:9] || spr[0:4]
|
|
// if length(SPR(n)) = 64 then
|
|
// RT <- SPR(n)
|
|
// else
|
|
// RT <- i32.0 || SPR(n)
|
|
|
|
const uint32_t n = ((i.XFX.spr & 0x1F) << 5) | ((i.XFX.spr >> 5) & 0x1F);
|
|
GpVar v;
|
|
switch (n) {
|
|
case 1:
|
|
// XER
|
|
v = e.xer_value();
|
|
break;
|
|
case 8:
|
|
// LR
|
|
v = e.lr_value();
|
|
break;
|
|
case 9:
|
|
// CTR
|
|
v = e.ctr_value();
|
|
break;
|
|
// 268 + 269 = TB + TBU
|
|
default:
|
|
XEINSTRNOTIMPLEMENTED();
|
|
return 1;
|
|
}
|
|
|
|
e.update_gpr_value(i.XFX.RT, v);
|
|
|
|
e.clear_constant_gpr_value(i.XFX.RT);
|
|
|
|
return 0;
|
|
}
|
|
|
|
XEEMITTER(mftb, 0x7C0002E6, XFX)(X64Emitter& e, X86Compiler& c, InstrData& i) {
|
|
LARGE_INTEGER counter;
|
|
if (QueryPerformanceCounter(&counter)) {
|
|
e.update_gpr_value(i.XFX.RT, e.get_uint64(counter.QuadPart));
|
|
} else {
|
|
e.update_gpr_value(i.XFX.RT, e.get_uint64(0));
|
|
}
|
|
|
|
e.clear_constant_gpr_value(i.XFX.RT);
|
|
|
|
return 0;
|
|
}
|
|
|
|
XEEMITTER(mtcrf, 0x7C000120, XFX)(X64Emitter& e, X86Compiler& c, InstrData& i) {
|
|
XEINSTRNOTIMPLEMENTED();
|
|
return 1;
|
|
}
|
|
|
|
XEEMITTER(mtspr, 0x7C0003A6, XFX)(X64Emitter& e, X86Compiler& c, InstrData& i) {
|
|
// n <- spr[5:9] || spr[0:4]
|
|
// if length(SPR(n)) = 64 then
|
|
// SPR(n) <- (RS)
|
|
// else
|
|
// SPR(n) <- (RS)[32:63]
|
|
|
|
GpVar v = e.gpr_value(i.XFX.RT);
|
|
|
|
const uint32_t n = ((i.XFX.spr & 0x1F) << 5) | ((i.XFX.spr >> 5) & 0x1F);
|
|
switch (n) {
|
|
case 1:
|
|
// XER
|
|
e.update_xer_value(v);
|
|
break;
|
|
case 8:
|
|
// LR
|
|
e.update_lr_value(v);
|
|
break;
|
|
case 9:
|
|
// CTR
|
|
e.update_ctr_value(v);
|
|
break;
|
|
default:
|
|
XEINSTRNOTIMPLEMENTED();
|
|
return 1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
void X64RegisterEmitCategoryControl() {
|
|
XEREGISTERINSTR(bx, 0x48000000);
|
|
XEREGISTERINSTR(bcx, 0x40000000);
|
|
XEREGISTERINSTR(bcctrx, 0x4C000420);
|
|
XEREGISTERINSTR(bclrx, 0x4C000020);
|
|
XEREGISTERINSTR(crand, 0x4C000202);
|
|
XEREGISTERINSTR(crandc, 0x4C000102);
|
|
XEREGISTERINSTR(creqv, 0x4C000242);
|
|
XEREGISTERINSTR(crnand, 0x4C0001C2);
|
|
XEREGISTERINSTR(crnor, 0x4C000042);
|
|
XEREGISTERINSTR(cror, 0x4C000382);
|
|
XEREGISTERINSTR(crorc, 0x4C000342);
|
|
XEREGISTERINSTR(crxor, 0x4C000182);
|
|
XEREGISTERINSTR(mcrf, 0x4C000000);
|
|
XEREGISTERINSTR(sc, 0x44000002);
|
|
XEREGISTERINSTR(td, 0x7C000088);
|
|
XEREGISTERINSTR(tdi, 0x08000000);
|
|
XEREGISTERINSTR(tw, 0x7C000008);
|
|
XEREGISTERINSTR(twi, 0x0C000000);
|
|
XEREGISTERINSTR(mfcr, 0x7C000026);
|
|
XEREGISTERINSTR(mfspr, 0x7C0002A6);
|
|
XEREGISTERINSTR(mftb, 0x7C0002E6);
|
|
XEREGISTERINSTR(mtcrf, 0x7C000120);
|
|
XEREGISTERINSTR(mtspr, 0x7C0003A6);
|
|
}
|
|
|
|
|
|
} // namespace x64
|
|
} // namespace cpu
|
|
} // namespace xe
|