472 lines
15 KiB
C++
472 lines
15 KiB
C++
/**
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******************************************************************************
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* Xenia : Xbox 360 Emulator Research Project *
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******************************************************************************
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* Copyright 2013 Ben Vanik. All rights reserved. *
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* Released under the BSD license - see LICENSE in the root for more details. *
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******************************************************************************
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*/
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#include "xenia/cpu/frontend/ppc_hir_builder.h"
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#include "xenia/base/byte_order.h"
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#include "xenia/base/logging.h"
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#include "xenia/base/memory.h"
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#include "xenia/cpu/cpu-private.h"
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#include "xenia/cpu/frontend/ppc_context.h"
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#include "xenia/cpu/frontend/ppc_disasm.h"
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#include "xenia/cpu/frontend/ppc_frontend.h"
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#include "xenia/cpu/frontend/ppc_instr.h"
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#include "xenia/cpu/hir/label.h"
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#include "xenia/cpu/processor.h"
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#include "xenia/profiling.h"
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namespace xe {
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namespace cpu {
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namespace frontend {
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// TODO(benvanik): remove when enums redefined.
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using namespace xe::cpu::hir;
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using xe::cpu::hir::Label;
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using xe::cpu::hir::TypeName;
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using xe::cpu::hir::Value;
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PPCHIRBuilder::PPCHIRBuilder(PPCFrontend* frontend)
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: HIRBuilder(), frontend_(frontend), comment_buffer_(4096) {}
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PPCHIRBuilder::~PPCHIRBuilder() = default;
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void PPCHIRBuilder::Reset() {
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start_address_ = 0;
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instr_offset_list_ = NULL;
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label_list_ = NULL;
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with_debug_info_ = false;
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HIRBuilder::Reset();
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}
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bool PPCHIRBuilder::Emit(FunctionInfo* symbol_info, uint32_t flags) {
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SCOPE_profile_cpu_f("cpu");
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Memory* memory = frontend_->memory();
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symbol_info_ = symbol_info;
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start_address_ = symbol_info->address();
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instr_count_ = (symbol_info->end_address() - symbol_info->address()) / 4 + 1;
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with_debug_info_ = (flags & EMIT_DEBUG_COMMENTS) == EMIT_DEBUG_COMMENTS;
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if (with_debug_info_) {
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Comment("%s fn %.8X-%.8X %s", symbol_info->module()->name().c_str(),
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symbol_info->address(), symbol_info->end_address(),
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symbol_info->name().c_str());
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}
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// Allocate offset list.
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// This is used to quickly map labels to instructions.
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// The list is built as the instructions are traversed, with the values
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// being the previous HIR Instr before the given instruction. An
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// instruction may have a label assigned to it if it hasn't been hit
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// yet.
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size_t list_size = instr_count_ * sizeof(void*);
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instr_offset_list_ = (Instr**)arena_->Alloc(list_size);
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label_list_ = (Label**)arena_->Alloc(list_size);
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std::memset(instr_offset_list_, 0, list_size);
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std::memset(label_list_, 0, list_size);
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// Always mark entry with label.
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label_list_[0] = NewLabel();
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uint32_t start_address = symbol_info->address();
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uint32_t end_address = symbol_info->end_address();
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InstrData i;
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for (uint32_t address = start_address, offset = 0; address <= end_address;
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address += 4, offset++) {
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i.address = address;
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i.code = xe::load_and_swap<uint32_t>(memory->TranslateVirtual(address));
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// TODO(benvanik): find a way to avoid using the opcode tables.
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i.type = GetInstrType(i.code);
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trace_info_.dest_count = 0;
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// Mark label, if we were assigned one earlier on in the walk.
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// We may still get a label, but it'll be inserted by LookupLabel
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// as needed.
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Label* label = label_list_[offset];
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if (label) {
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MarkLabel(label);
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}
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Instr* first_instr = 0;
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if (with_debug_info_) {
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if (label) {
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AnnotateLabel(address, label);
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}
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comment_buffer_.Reset();
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DisasmPPC(i, &comment_buffer_);
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Comment("%.8X %.8X %s", address, i.code, comment_buffer_.GetString());
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first_instr = last_instr();
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}
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// Mark source offset for debugging.
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// We could omit this if we never wanted to debug.
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SourceOffset(i.address);
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if (!first_instr) {
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first_instr = last_instr();
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}
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// Stash instruction offset. It's either the SOURCE_OFFSET or the COMMENT.
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instr_offset_list_[offset] = first_instr;
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if (!i.type) {
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XELOGE("Invalid instruction %.8llX %.8X", i.address, i.code);
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Comment("INVALID!");
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// TraceInvalidInstruction(i);
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continue;
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}
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++i.type->translation_count;
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typedef int (*InstrEmitter)(PPCHIRBuilder& f, InstrData& i);
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InstrEmitter emit = (InstrEmitter)i.type->emit;
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if (i.address == FLAGS_break_on_instruction) {
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Comment("--break-on-instruction target");
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DebugBreak();
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}
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if (!i.type->emit || emit(*this, i)) {
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XELOGE("Unimplemented instr %.8llX %.8X %s", i.address, i.code,
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i.type->name);
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Comment("UNIMPLEMENTED!");
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// DebugBreak();
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// TraceInvalidInstruction(i);
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}
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}
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return Finalize();
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}
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void PPCHIRBuilder::AnnotateLabel(uint32_t address, Label* label) {
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char name_buffer[13];
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snprintf(name_buffer, xe::countof(name_buffer), "loc_%.8X", address);
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label->name = (char*)arena_->Alloc(sizeof(name_buffer));
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memcpy(label->name, name_buffer, sizeof(name_buffer));
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}
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FunctionInfo* PPCHIRBuilder::LookupFunction(uint32_t address) {
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Processor* processor = frontend_->processor();
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FunctionInfo* symbol_info;
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if (!processor->LookupFunctionInfo(address, &symbol_info)) {
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return nullptr;
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}
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return symbol_info;
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}
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Label* PPCHIRBuilder::LookupLabel(uint32_t address) {
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if (address < start_address_) {
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return nullptr;
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}
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size_t offset = (address - start_address_) / 4;
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if (offset >= instr_count_) {
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return nullptr;
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}
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Label* label = label_list_[offset];
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if (label) {
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return label;
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}
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// No label. If we haven't yet hit the instruction in the walk
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// then create a label. Otherwise, we must go back and insert
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// the label.
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label = NewLabel();
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label_list_[offset] = label;
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Instr* instr = instr_offset_list_[offset];
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if (instr) {
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if (instr->prev) {
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// Insert label, breaking up existing instructions.
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InsertLabel(label, instr->prev);
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} else {
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// Instruction is at the head of a block, so just add the label.
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MarkLabel(label, instr->block);
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}
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// Annotate the label, as we won't do it later.
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if (with_debug_info_) {
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AnnotateLabel(address, label);
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}
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}
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return label;
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}
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// Value* PPCHIRBuilder::LoadXER() {
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//}
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//
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// void PPCHIRBuilder::StoreXER(Value* value) {
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//}
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Value* PPCHIRBuilder::LoadLR() {
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return LoadContext(offsetof(PPCContext, lr), INT64_TYPE);
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}
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void PPCHIRBuilder::StoreLR(Value* value) {
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assert_true(value->type == INT64_TYPE);
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StoreContext(offsetof(PPCContext, lr), value);
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auto& trace_reg = trace_info_.dests[trace_info_.dest_count++];
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trace_reg.reg = 64;
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trace_reg.value = value;
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}
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Value* PPCHIRBuilder::LoadCTR() {
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return LoadContext(offsetof(PPCContext, ctr), INT64_TYPE);
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}
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void PPCHIRBuilder::StoreCTR(Value* value) {
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assert_true(value->type == INT64_TYPE);
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StoreContext(offsetof(PPCContext, ctr), value);
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auto& trace_reg = trace_info_.dests[trace_info_.dest_count++];
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trace_reg.reg = 65;
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trace_reg.value = value;
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}
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Value* PPCHIRBuilder::LoadCR() {
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// All bits. This is expensive, but seems to be less used than the
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// field-specific LoadCR.
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Value* v = LoadCR(0);
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for (int i = 1; i <= 7; ++i) {
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v = Or(v, LoadCR(i));
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}
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return v;
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}
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Value* PPCHIRBuilder::LoadCR(uint32_t n) {
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// Construct the entire word of just the bits we care about.
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// This makes it easier for the optimizer to exclude things, though
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// we could be even more clever and watch sequences.
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Value* v = Shl(ZeroExtend(LoadContext(offsetof(PPCContext, cr0) + (4 * n) + 0,
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INT8_TYPE),
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INT64_TYPE),
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4 * (7 - n) + 3);
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v = Or(v, Shl(ZeroExtend(LoadContext(offsetof(PPCContext, cr0) + (4 * n) + 1,
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INT8_TYPE),
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INT64_TYPE),
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4 * (7 - n) + 2));
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v = Or(v, Shl(ZeroExtend(LoadContext(offsetof(PPCContext, cr0) + (4 * n) + 2,
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INT8_TYPE),
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INT64_TYPE),
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4 * (7 - n) + 1));
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v = Or(v, Shl(ZeroExtend(LoadContext(offsetof(PPCContext, cr0) + (4 * n) + 3,
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INT8_TYPE),
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INT64_TYPE),
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4 * (7 - n) + 0));
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return v;
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}
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Value* PPCHIRBuilder::LoadCRField(uint32_t n, uint32_t bit) {
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return LoadContext(offsetof(PPCContext, cr0) + (4 * n) + bit, INT8_TYPE);
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}
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void PPCHIRBuilder::StoreCR(Value* value) {
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// All bits. This is expensive, but seems to be less used than the
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// field-specific StoreCR.
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for (int i = 0; i <= 7; ++i) {
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StoreCR(i, value);
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}
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}
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void PPCHIRBuilder::StoreCR(uint32_t n, Value* value) {
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// Pull out the bits we are interested in.
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// Optimization passes will kill any unneeded stores (mostly).
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StoreContext(offsetof(PPCContext, cr0) + (4 * n) + 0,
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And(Truncate(Shr(value, 4 * (7 - n) + 3), INT8_TYPE),
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LoadConstant(uint8_t(1))));
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StoreContext(offsetof(PPCContext, cr0) + (4 * n) + 1,
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And(Truncate(Shr(value, 4 * (7 - n) + 2), INT8_TYPE),
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LoadConstant(uint8_t(1))));
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StoreContext(offsetof(PPCContext, cr0) + (4 * n) + 2,
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And(Truncate(Shr(value, 4 * (7 - n) + 1), INT8_TYPE),
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LoadConstant(uint8_t(1))));
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StoreContext(offsetof(PPCContext, cr0) + (4 * n) + 3,
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And(Truncate(Shr(value, 4 * (7 - n) + 0), INT8_TYPE),
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LoadConstant(uint8_t(1))));
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}
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void PPCHIRBuilder::StoreCRField(uint32_t n, uint32_t bit, Value* value) {
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StoreContext(offsetof(PPCContext, cr0) + (4 * n) + bit, value);
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// TODO(benvanik): trace CR.
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}
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void PPCHIRBuilder::UpdateCR(uint32_t n, Value* lhs, bool is_signed) {
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UpdateCR(n, Truncate(lhs, INT32_TYPE), LoadZero(INT32_TYPE), is_signed);
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}
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void PPCHIRBuilder::UpdateCR(uint32_t n, Value* lhs, Value* rhs,
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bool is_signed) {
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if (is_signed) {
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Value* lt = CompareSLT(lhs, rhs);
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StoreContext(offsetof(PPCContext, cr0) + (4 * n) + 0, lt);
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Value* gt = CompareSGT(lhs, rhs);
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StoreContext(offsetof(PPCContext, cr0) + (4 * n) + 1, gt);
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} else {
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Value* lt = CompareULT(lhs, rhs);
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StoreContext(offsetof(PPCContext, cr0) + (4 * n) + 0, lt);
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Value* gt = CompareUGT(lhs, rhs);
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StoreContext(offsetof(PPCContext, cr0) + (4 * n) + 1, gt);
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}
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Value* eq = CompareEQ(lhs, rhs);
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StoreContext(offsetof(PPCContext, cr0) + (4 * n) + 2, eq);
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// Value* so = AllocValue(UINT8_TYPE);
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// StoreContext(offsetof(PPCContext, cr) + (4 * n) + 3, so);
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// TOOD(benvanik): trace CR.
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}
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void PPCHIRBuilder::UpdateCR6(Value* src_value) {
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// Testing for all 1's and all 0's.
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// if (Rc) CR6 = all_equal | 0 | none_equal | 0
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// TODO(benvanik): efficient instruction?
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StoreContext(offsetof(PPCContext, cr6.cr6_1), LoadZero(INT8_TYPE));
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StoreContext(offsetof(PPCContext, cr6.cr6_3), LoadZero(INT8_TYPE));
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StoreContext(offsetof(PPCContext, cr6.cr6_all_equal),
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IsFalse(Not(src_value)));
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StoreContext(offsetof(PPCContext, cr6.cr6_none_equal), IsFalse(src_value));
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// TOOD(benvanik): trace CR.
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}
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Value* PPCHIRBuilder::LoadMSR() {
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// bit 48 = EE; interrupt enabled
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// bit 62 = RI; recoverable interrupt
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// return 8000h if unlocked, else 0
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CallExtern(frontend_->builtins()->check_global_lock);
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return LoadContext(offsetof(PPCContext, scratch), INT64_TYPE);
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}
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void PPCHIRBuilder::StoreMSR(Value* value) {
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// if & 0x8000 == 0, lock, else unlock
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StoreContext(offsetof(PPCContext, scratch), ZeroExtend(value, INT64_TYPE));
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CallExtern(frontend_->builtins()->handle_global_lock);
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}
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Value* PPCHIRBuilder::LoadFPSCR() {
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return LoadContext(offsetof(PPCContext, fpscr), INT64_TYPE);
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}
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void PPCHIRBuilder::StoreFPSCR(Value* value) {
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assert_true(value->type == INT64_TYPE);
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StoreContext(offsetof(PPCContext, fpscr), value);
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auto& trace_reg = trace_info_.dests[trace_info_.dest_count++];
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trace_reg.reg = 67;
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trace_reg.value = value;
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}
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Value* PPCHIRBuilder::LoadXER() {
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assert_always();
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return NULL;
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}
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void PPCHIRBuilder::StoreXER(Value* value) { assert_always(); }
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Value* PPCHIRBuilder::LoadCA() {
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return LoadContext(offsetof(PPCContext, xer_ca), INT8_TYPE);
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}
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void PPCHIRBuilder::StoreCA(Value* value) {
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assert_true(value->type == INT8_TYPE);
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StoreContext(offsetof(PPCContext, xer_ca), value);
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auto& trace_reg = trace_info_.dests[trace_info_.dest_count++];
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trace_reg.reg = 66;
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trace_reg.value = value;
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}
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Value* PPCHIRBuilder::LoadSAT() {
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return LoadContext(offsetof(PPCContext, vscr_sat), INT8_TYPE);
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}
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void PPCHIRBuilder::StoreSAT(Value* value) {
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value = Truncate(value, INT8_TYPE);
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StoreContext(offsetof(PPCContext, vscr_sat), value);
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auto& trace_reg = trace_info_.dests[trace_info_.dest_count++];
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trace_reg.reg = 44;
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trace_reg.value = value;
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}
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Value* PPCHIRBuilder::LoadGPR(uint32_t reg) {
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return LoadContext(offsetof(PPCContext, r) + reg * 8, INT64_TYPE);
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}
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void PPCHIRBuilder::StoreGPR(uint32_t reg, Value* value) {
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assert_true(value->type == INT64_TYPE);
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StoreContext(offsetof(PPCContext, r) + reg * 8, value);
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auto& trace_reg = trace_info_.dests[trace_info_.dest_count++];
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trace_reg.reg = reg;
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trace_reg.value = value;
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}
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Value* PPCHIRBuilder::LoadFPR(uint32_t reg) {
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return LoadContext(offsetof(PPCContext, f) + reg * 8, FLOAT64_TYPE);
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}
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void PPCHIRBuilder::StoreFPR(uint32_t reg, Value* value) {
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assert_true(value->type == FLOAT64_TYPE);
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StoreContext(offsetof(PPCContext, f) + reg * 8, value);
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auto& trace_reg = trace_info_.dests[trace_info_.dest_count++];
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trace_reg.reg = reg + 32;
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trace_reg.value = value;
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}
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Value* PPCHIRBuilder::LoadVR(uint32_t reg) {
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return LoadContext(offsetof(PPCContext, v) + reg * 16, VEC128_TYPE);
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}
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void PPCHIRBuilder::StoreVR(uint32_t reg, Value* value) {
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assert_true(value->type == VEC128_TYPE);
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StoreContext(offsetof(PPCContext, v) + reg * 16, value);
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auto& trace_reg = trace_info_.dests[trace_info_.dest_count++];
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trace_reg.reg = 128 + reg;
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trace_reg.value = value;
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}
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Value* PPCHIRBuilder::LoadAcquire(Value* address, TypeName type,
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uint32_t load_flags) {
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AtomicExchange(LoadContext(offsetof(PPCContext, reserve_address), INT64_TYPE),
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Truncate(address, INT32_TYPE));
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Value* value = Load(address, type, load_flags);
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// Save the value so that we can compare it later in StoreRelease.
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AtomicExchange(LoadContext(offsetof(PPCContext, reserve_value), INT64_TYPE),
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value);
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return value;
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}
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Value* PPCHIRBuilder::StoreRelease(Value* address, Value* value,
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uint32_t store_flags) {
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Value* old_address = AtomicExchange(
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LoadContext(offsetof(PPCContext, reserve_address), INT64_TYPE),
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LoadZero(INT32_TYPE));
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// HACK: ensure the reservation addresses match AND the value hasn't changed.
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Value* old_value = AtomicExchange(
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LoadContext(offsetof(PPCContext, reserve_value), INT64_TYPE),
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LoadZero(value->type));
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Value* current_value = Load(address, value->type);
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Value* eq = And(CompareEQ(Truncate(address, INT32_TYPE), old_address),
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CompareEQ(current_value, old_value));
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StoreContext(offsetof(PPCContext, cr0.cr0_eq), eq);
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StoreContext(offsetof(PPCContext, cr0.cr0_lt), LoadZero(INT8_TYPE));
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StoreContext(offsetof(PPCContext, cr0.cr0_gt), LoadZero(INT8_TYPE));
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auto skip_label = NewLabel();
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BranchFalse(eq, skip_label, BRANCH_UNLIKELY);
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Store(address, value, store_flags);
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MarkLabel(skip_label);
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return eq;
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|
}
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} // namespace frontend
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} // namespace cpu
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} // namespace xe
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