110 lines
2.2 KiB
ArmAsm
110 lines
2.2 KiB
ArmAsm
test_divw_1:
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#_ REGISTER_IN r4 1
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#_ REGISTER_IN r5 2
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divw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 2
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# TODO(benvanik): x64 ignore divide by zero (=0)
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#test_divw_2:
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# #_ REGISTER_IN r4 1
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# #_ REGISTER_IN r5 0
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# divw r3, r4, r5
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# blr
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# #_ REGISTER_OUT r3 0
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# #_ REGISTER_OUT r4 1
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# #_ REGISTER_OUT r5 0
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test_divw_3:
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#_ REGISTER_IN r4 2
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#_ REGISTER_IN r5 1
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divw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 2
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#_ REGISTER_OUT r4 2
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#_ REGISTER_OUT r5 1
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test_divw_4:
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#_ REGISTER_IN r4 35
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#_ REGISTER_IN r5 7
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divw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 5
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#_ REGISTER_OUT r4 35
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#_ REGISTER_OUT r5 7
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test_divw_5:
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#_ REGISTER_IN r4 0
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#_ REGISTER_IN r5 1
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divw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 0
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#_ REGISTER_OUT r5 1
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test_divw_6:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 1
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divw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0x00000000FFFFFFFF
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 1
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test_divw_7:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
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divw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 1
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
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test_divw_8:
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#_ REGISTER_IN r4 1
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#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
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divw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0x00000000FFFFFFFF
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
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test_divw_9:
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#_ REGISTER_IN r4 0x000000007FFFFFFF
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#_ REGISTER_IN r5 1
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divw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0x000000007FFFFFFF
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#_ REGISTER_OUT r4 0x000000007FFFFFFF
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#_ REGISTER_OUT r5 1
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test_divw_10:
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#_ REGISTER_IN r4 0x000000007FFFFFFF
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#_ REGISTER_IN r5 0x000000007FFFFFFF
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divw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 1
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#_ REGISTER_OUT r4 0x000000007FFFFFFF
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#_ REGISTER_OUT r5 0x000000007FFFFFFF
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test_divw_11:
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#_ REGISTER_IN r4 1
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#_ REGISTER_IN r5 0x000000007FFFFFFF
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divw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 0x000000007FFFFFFF
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# TODO(benvanik): integer overflow (=0)
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#test_divw_12:
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# #_ REGISTER_IN r4 0x80000000
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# #_ REGISTER_IN r5 -1
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# divw r3, r4, r5
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# blr
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# #_ REGISTER_OUT r3 0
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# #_ REGISTER_OUT r4 0x80000000
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# #_ REGISTER_OUT r5 -1
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