04d5c40d0d
Use the _xe suffix instead of the xesl_ prefix for quicker visual recognition of identifiers, also switch to snake_case for consistency. Also add the f suffix to float32 literals because the Metal Shading Language is based on C++.
61 lines
2.7 KiB
Plaintext
61 lines
2.7 KiB
Plaintext
/**
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******************************************************************************
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* Xenia : Xbox 360 Emulator Research Project *
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******************************************************************************
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* Copyright 2022 Ben Vanik. All rights reserved. *
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* Released under the BSD license - see LICENSE in the root for more details. *
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******************************************************************************
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*/
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#ifndef XENIA_GPU_SHADERS_EDRAM_XESLI_
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#define XENIA_GPU_SHADERS_EDRAM_XESLI_
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#include "pixel_formats.xesli"
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#define kXenosMsaaSamples_1X 0u
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#define kXenosMsaaSamples_2X 1u
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#define kXenosMsaaSamples_4X 2u
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// `wrap = false` can be used if it's known that the resulting tile indices
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// can't exceed 11 bits, and the modulo operator doesn't need to be performed to
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// access the data in the render targets that are located in both ends of the
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// EDRAM at the same time.
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uint XeEdramOffsetInts(uint2_xe pixel_index, uint base_tiles, bool wrap,
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uint pitch_tiles, uint msaa_samples, bool is_depth,
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uint format_ints_log2, uint pixel_sample_index,
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uint2_xe resolution_scale) {
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uint2_xe rt_sample_index =
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pixel_index <<
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uint2_xe(greater_than_equal_xe(
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uint_x2_xe(msaa_samples),
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uint2_xe(kXenosMsaaSamples_4X, kXenosMsaaSamples_2X)));
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rt_sample_index += (uint_x2_xe(pixel_sample_index) >> uint2_xe(1u, 0u)) & 1u;
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// For now, while the actual storage of 64bpp render targets in comparison to
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// 32bpp is not known, storing 40x16 64bpp samples per tile for simplicity of
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// addressing in different scenarios.
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uint2_xe tile_size_at_32bpp = uint2_xe(80u, 16u) * resolution_scale;
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uint2_xe tile_size_samples =
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tile_size_at_32bpp >> uint2_xe(format_ints_log2, 0u);
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uint2_xe tile_offset_xy = rt_sample_index / tile_size_samples;
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base_tiles += tile_offset_xy.y * pitch_tiles + tile_offset_xy.x;
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rt_sample_index -= tile_offset_xy * tile_size_samples;
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if (is_depth) {
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uint tile_width_half = tile_size_samples.x >> 1u;
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rt_sample_index.x =
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uint(int(rt_sample_index.x) +
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((rt_sample_index.x >= tile_width_half) ? -int(tile_width_half)
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: int(tile_width_half)));
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}
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uint address =
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base_tiles * (tile_size_at_32bpp.x * tile_size_at_32bpp.y) +
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((rt_sample_index.y * tile_size_samples.x + rt_sample_index.x) <<
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format_ints_log2);
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if (wrap) {
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// EDRAM addressing is periodic (modulo the EDRAM size).
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address %= tile_size_at_32bpp.x * tile_size_at_32bpp.y * 2048u;
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}
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return address;
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}
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#endif // XENIA_GPU_SHADERS_EDRAM_XESLI_
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