740 lines
26 KiB
C++
740 lines
26 KiB
C++
/**
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******************************************************************************
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* Xenia : Xbox 360 Emulator Research Project *
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******************************************************************************
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* Copyright 2013 Ben Vanik. All rights reserved. *
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* Released under the BSD license - see LICENSE in the root for more details. *
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******************************************************************************
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*/
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#include <xenia/gpu/ring_buffer_worker.h>
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#include <xenia/gpu/gpu-private.h>
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#include <xenia/gpu/graphics_driver.h>
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#include <xenia/gpu/graphics_system.h>
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#include <xenia/gpu/xenos/packets.h>
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#include <xenia/gpu/xenos/registers.h>
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using namespace xe;
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using namespace xe::gpu;
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using namespace xe::gpu::xenos;
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#define XETRACERB(fmt, ...) if (FLAGS_trace_ring_buffer) XELOGGPU(fmt, ##__VA_ARGS__)
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RingBufferWorker::RingBufferWorker(
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GraphicsSystem* graphics_system, xe_memory_ref memory) :
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graphics_system_(graphics_system), memory_(memory), driver_(0) {
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write_ptr_index_event_ = CreateEvent(
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NULL, FALSE, FALSE, NULL);
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primary_buffer_ptr_ = 0;
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primary_buffer_size_ = 0;
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read_ptr_index_ = 0;
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read_ptr_update_freq_ = 0;
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read_ptr_writeback_ptr_ = 0;
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write_ptr_index_ = 0;
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write_ptr_max_index_ = 0;
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LARGE_INTEGER perf_counter;
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QueryPerformanceCounter(&perf_counter);
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time_base_ = perf_counter.QuadPart;
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counter_ = 0;
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}
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RingBufferWorker::~RingBufferWorker() {
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SetEvent(write_ptr_index_event_);
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CloseHandle(write_ptr_index_event_);
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}
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uint64_t RingBufferWorker::QueryTime() {
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LARGE_INTEGER perf_counter;
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QueryPerformanceCounter(&perf_counter);
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return perf_counter.QuadPart - time_base_;
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}
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void RingBufferWorker::Initialize(GraphicsDriver* driver,
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uint32_t ptr, uint32_t page_count) {
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driver_ = driver;
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primary_buffer_ptr_ = ptr;
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// Not sure this is correct, but it's a way to take the page_count back to
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// the number of bytes allocated by the physical alloc.
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uint32_t original_size = 1 << (0x1C - page_count - 1);
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primary_buffer_size_ = original_size;
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read_ptr_index_ = 0;
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// Tell the driver what to use for translation.
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driver_->set_address_translation(primary_buffer_ptr_ & ~0x1FFFFFFF);
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}
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void RingBufferWorker::EnableReadPointerWriteBack(uint32_t ptr,
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uint32_t block_size) {
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// CP_RB_RPTR_ADDR Ring Buffer Read Pointer Address 0x70C
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// ptr = RB_RPTR_ADDR, pointer to write back the address to.
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read_ptr_writeback_ptr_ = (primary_buffer_ptr_ & ~0x1FFFFFFF) + ptr;
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// CP_RB_CNTL Ring Buffer Control 0x704
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// block_size = RB_BLKSZ, number of quadwords read between updates of the
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// read pointer.
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read_ptr_update_freq_ = (uint32_t)pow(2.0, (double)block_size) / 4;
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}
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void RingBufferWorker::UpdateWritePointer(uint32_t value) {
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write_ptr_max_index_ = MAX(write_ptr_max_index_, value);
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write_ptr_index_ = value;
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SetEvent(write_ptr_index_event_);
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}
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void RingBufferWorker::Pump() {
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uint8_t* p = xe_memory_addr(memory_);
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if (write_ptr_index_ == 0xBAADF00D ||
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read_ptr_index_ == write_ptr_index_) {
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// Check if the pointer has moved.
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// We wait a short bit here to yield time. Since we are also running the
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// main window display we don't want to pause too long, though.
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const int wait_time_ms = 1;
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if (WaitForSingleObject(write_ptr_index_event_,
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wait_time_ms) == WAIT_TIMEOUT) {
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return;
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}
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}
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// Bring local so we don't have to worry about them changing out from under
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// us.
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uint32_t write_ptr_index = write_ptr_index_;
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uint32_t write_ptr_max_index = write_ptr_max_index_;
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if (read_ptr_index_ == write_ptr_index) {
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return;
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}
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// Process the new commands.
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XETRACERB("Ring buffer thread work");
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// Execute. Note that we handle wraparound transparently.
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ExecutePrimaryBuffer(read_ptr_index_, write_ptr_index);
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read_ptr_index_ = write_ptr_index;
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// TODO(benvanik): use read_ptr_update_freq_ and only issue after moving
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// that many indices.
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if (read_ptr_writeback_ptr_) {
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XESETUINT32BE(p + read_ptr_writeback_ptr_, read_ptr_index_);
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}
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}
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void RingBufferWorker::ExecutePrimaryBuffer(
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uint32_t start_index, uint32_t end_index) {
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// Adjust pointer base.
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uint32_t ptr = primary_buffer_ptr_ + start_index * 4;
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ptr = (primary_buffer_ptr_ & ~0x1FFFFFFF) | (ptr & 0x1FFFFFFF);
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uint32_t end_ptr = primary_buffer_ptr_ + end_index * 4;
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end_ptr = (primary_buffer_ptr_ & ~0x1FFFFFFF) | (end_ptr & 0x1FFFFFFF);
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XETRACERB("[%.8X] ExecutePrimaryBuffer(%dw -> %dw)",
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ptr, start_index, end_index);
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// Execute commands!
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PacketArgs args;
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args.ptr = ptr;
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args.base_ptr = primary_buffer_ptr_;
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args.max_address = primary_buffer_ptr_ + primary_buffer_size_ * 4;
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args.ptr_mask = (primary_buffer_size_ / 4) - 1;
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uint32_t n = 0;
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while (args.ptr != end_ptr) {
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n += ExecutePacket(args);
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}
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if (end_index > start_index) {
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XEASSERT(n == (end_index - start_index));
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}
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XETRACERB(" ExecutePrimaryBuffer End");
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}
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void RingBufferWorker::ExecuteIndirectBuffer(uint32_t ptr, uint32_t length) {
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XETRACERB("[%.8X] ExecuteIndirectBuffer(%dw)", ptr, length);
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// Execute commands!
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PacketArgs args;
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args.ptr = ptr;
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args.base_ptr = ptr;
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args.max_address = ptr + length * 4;
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args.ptr_mask = 0;
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for (uint32_t n = 0; n < length;) {
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n += ExecutePacket(args);
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XEASSERT(n <= length);
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}
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XETRACERB(" ExecuteIndirectBuffer End");
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}
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#define LOG_DATA(count) \
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for (uint32_t __m = 0; __m < count; __m++) { \
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XETRACERB("[%.8X] %.8X", \
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packet_ptr + (1 + __m) * 4, \
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XEGETUINT32BE(packet_base + 1 * 4 + __m * 4)); \
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}
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void RingBufferWorker::AdvancePtr(PacketArgs& args, uint32_t n) {
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args.ptr = args.ptr + n * 4;
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if (args.ptr_mask) {
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args.ptr =
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args.base_ptr + (((args.ptr - args.base_ptr) / 4) & args.ptr_mask) * 4;
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}
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}
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#define ADVANCE_PTR(n) AdvancePtr(args, n)
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#define PEEK_PTR() \
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XEGETUINT32BE(p + args.ptr)
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#define READ_PTR() \
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XEGETUINT32BE(p + args.ptr); ADVANCE_PTR(1);
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uint32_t RingBufferWorker::ExecutePacket(PacketArgs& args) {
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uint8_t* p = xe_memory_addr(memory_);
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RegisterFile* regs = driver_->register_file();
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uint32_t packet_ptr = args.ptr;
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const uint8_t* packet_base = p + packet_ptr;
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const uint32_t packet = PEEK_PTR();
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ADVANCE_PTR(1);
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const uint32_t packet_type = packet >> 30;
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if (packet == 0) {
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XETRACERB("[%.8X] Packet(%.8X): 0?",
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packet_ptr, packet);
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return 1;
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}
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switch (packet_type) {
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case 0x00:
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{
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// Type-0 packet.
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// Write count registers in sequence to the registers starting at
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// (base_index << 2).
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XETRACERB("[%.8X] Packet(%.8X): set registers:",
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packet_ptr, packet);
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uint32_t count = ((packet >> 16) & 0x3FFF) + 1;
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uint32_t base_index = (packet & 0x7FFF);
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uint32_t write_one_reg = (packet >> 15) & 0x1;
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for (uint32_t m = 0; m < count; m++) {
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uint32_t reg_data = PEEK_PTR();
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uint32_t target_index = write_one_reg ? base_index : base_index + m;
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const char* reg_name = xenos::GetRegisterName(target_index);
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XETRACERB("[%.8X] %.8X -> %.4X %s",
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args.ptr,
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reg_data, target_index, reg_name ? reg_name : "");
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ADVANCE_PTR(1);
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WriteRegister(packet_ptr, target_index, reg_data);
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}
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return 1 + count;
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}
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break;
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case 0x01:
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{
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// Type-1 packet.
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// Contains two registers of data. Type-0 should be more common.
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XETRACERB("[%.8X] Packet(%.8X): set registers:",
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packet_ptr, packet);
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uint32_t reg_index_1 = packet & 0x7FF;
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uint32_t reg_index_2 = (packet >> 11) & 0x7FF;
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uint32_t reg_ptr_1 = args.ptr;
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uint32_t reg_data_1 = READ_PTR();
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uint32_t reg_ptr_2 = args.ptr;
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uint32_t reg_data_2 = READ_PTR();
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const char* reg_name_1 = xenos::GetRegisterName(reg_index_1);
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const char* reg_name_2 = xenos::GetRegisterName(reg_index_2);
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XETRACERB("[%.8X] %.8X -> %.4X %s",
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reg_ptr_1,
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reg_data_1, reg_index_1, reg_name_1 ? reg_name_1 : "");
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XETRACERB("[%.8X] %.8X -> %.4X %s",
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reg_ptr_2,
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reg_data_2, reg_index_2, reg_name_2 ? reg_name_2 : "");
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WriteRegister(packet_ptr, reg_index_1, reg_data_1);
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WriteRegister(packet_ptr, reg_index_2, reg_data_2);
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return 1 + 2;
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}
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break;
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case 0x02:
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// Type-2 packet.
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// No-op. Do nothing.
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XETRACERB("[%.8X] Packet(%.8X): padding",
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packet_ptr, packet);
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return 1;
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case 0x03:
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{
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// Type-3 packet.
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uint32_t count = ((packet >> 16) & 0x3FFF) + 1;
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uint32_t opcode = (packet >> 8) & 0x7F;
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// & 1 == predicate, maybe?
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switch (opcode) {
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case PM4_ME_INIT:
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// initialize CP's micro-engine
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XETRACERB("[%.8X] Packet(%.8X): PM4_ME_INIT",
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packet_ptr, packet);
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LOG_DATA(count);
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ADVANCE_PTR(count);
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break;
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case PM4_NOP:
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// skip N 32-bit words to get to the next packet
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// No-op, ignore some data.
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XETRACERB("[%.8X] Packet(%.8X): PM4_NOP",
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packet_ptr, packet);
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LOG_DATA(count);
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ADVANCE_PTR(count);
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break;
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case PM4_INTERRUPT:
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// generate interrupt from the command stream
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{
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XETRACERB("[%.8X] Packet(%.8X): PM4_INTERRUPT",
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packet_ptr, packet);
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LOG_DATA(count);
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uint32_t cpu_mask = READ_PTR();
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for (int n = 0; n < 6; n++) {
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if (cpu_mask & (1 << n)) {
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graphics_system_->DispatchInterruptCallback(1, n);
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}
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}
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}
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break;
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case PM4_INDIRECT_BUFFER:
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// indirect buffer dispatch
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{
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uint32_t list_ptr = READ_PTR();
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uint32_t list_length = READ_PTR();
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XETRACERB("[%.8X] Packet(%.8X): PM4_INDIRECT_BUFFER %.8X (%dw)",
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packet_ptr, packet, list_ptr, list_length);
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ExecuteIndirectBuffer(GpuToCpu(list_ptr), list_length);
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}
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break;
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case PM4_WAIT_REG_MEM:
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// wait until a register or memory location is a specific value
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{
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XETRACERB("[%.8X] Packet(%.8X): PM4_WAIT_REG_MEM",
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packet_ptr, packet);
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LOG_DATA(count);
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uint32_t wait_info = READ_PTR();
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uint32_t poll_reg_addr = READ_PTR();
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uint32_t ref = READ_PTR();
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uint32_t mask = READ_PTR();
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uint32_t wait = READ_PTR();
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bool matched = false;
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do {
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uint32_t value;
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if (wait_info & 0x10) {
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// Memory.
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XE_GPU_ENDIAN endianness = (XE_GPU_ENDIAN)(poll_reg_addr & 0x3);
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poll_reg_addr &= ~0x3;
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value = XEGETUINT32LE(p + GpuToCpu(packet_ptr, poll_reg_addr));
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value = GpuSwap(value, endianness);
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} else {
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// Register.
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XEASSERT(poll_reg_addr < kXEGpuRegisterCount);
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value = regs->values[poll_reg_addr].u32;
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}
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switch (wait_info & 0x7) {
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case 0x0: // Never.
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matched = false;
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break;
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case 0x1: // Less than reference.
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matched = (value & mask) < ref;
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break;
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case 0x2: // Less than or equal to reference.
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matched = (value & mask) <= ref;
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break;
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case 0x3: // Equal to reference.
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matched = (value & mask) == ref;
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break;
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case 0x4: // Not equal to reference.
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matched = (value & mask) != ref;
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break;
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case 0x5: // Greater than or equal to reference.
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matched = (value & mask) >= ref;
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break;
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case 0x6: // Greater than reference.
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matched = (value & mask) > ref;
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break;
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case 0x7: // Always
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matched = true;
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break;
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}
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if (!matched) {
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// Wait.
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if (wait >= 0x100) {
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Sleep(wait / 0x100);
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} else {
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SwitchToThread();
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}
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}
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} while (!matched);
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}
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break;
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case PM4_REG_RMW:
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// register read/modify/write
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// ? (used during shader upload and edram setup)
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{
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XETRACERB("[%.8X] Packet(%.8X): PM4_REG_RMW",
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packet_ptr, packet);
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LOG_DATA(count);
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uint32_t rmw_info = READ_PTR();
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uint32_t and_mask = READ_PTR();
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uint32_t or_mask = READ_PTR();
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uint32_t value = regs->values[rmw_info & 0x1FFF].u32;
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if ((rmw_info >> 30) & 0x1) {
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// | reg
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value |= regs->values[or_mask & 0x1FFF].u32;
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} else {
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// | imm
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value |= or_mask;
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}
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if ((rmw_info >> 31) & 0x1) {
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// & reg
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value &= regs->values[and_mask & 0x1FFF].u32;
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} else {
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// & imm
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value &= and_mask;
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}
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WriteRegister(packet_ptr, rmw_info & 0x1FFF, value);
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}
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break;
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case PM4_COND_WRITE:
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// conditional write to memory or register
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{
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XETRACERB("[%.8X] Packet(%.8X): PM4_COND_WRITE",
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packet_ptr, packet);
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LOG_DATA(count);
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uint32_t wait_info = READ_PTR();
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uint32_t poll_reg_addr = READ_PTR();
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uint32_t ref = READ_PTR();
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uint32_t mask = READ_PTR();
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uint32_t write_reg_addr = READ_PTR();
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uint32_t write_data = READ_PTR();
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uint32_t value;
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if (wait_info & 0x10) {
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// Memory.
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XE_GPU_ENDIAN endianness = (XE_GPU_ENDIAN)(poll_reg_addr & 0x3);
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poll_reg_addr &= ~0x3;
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value = XEGETUINT32LE(p + GpuToCpu(packet_ptr, poll_reg_addr));
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value = GpuSwap(value, endianness);
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} else {
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// Register.
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XEASSERT(poll_reg_addr < kXEGpuRegisterCount);
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value = regs->values[poll_reg_addr].u32;
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}
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bool matched = false;
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switch (wait_info & 0x7) {
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case 0x0: // Never.
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matched = false;
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break;
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case 0x1: // Less than reference.
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matched = (value & mask) < ref;
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break;
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case 0x2: // Less than or equal to reference.
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matched = (value & mask) <= ref;
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break;
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case 0x3: // Equal to reference.
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matched = (value & mask) == ref;
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break;
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case 0x4: // Not equal to reference.
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matched = (value & mask) != ref;
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break;
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case 0x5: // Greater than or equal to reference.
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matched = (value & mask) >= ref;
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break;
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case 0x6: // Greater than reference.
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matched = (value & mask) > ref;
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break;
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case 0x7: // Always
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matched = true;
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break;
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}
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if (matched) {
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// Write.
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if (wait_info & 0x100) {
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// Memory.
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XE_GPU_ENDIAN endianness = (XE_GPU_ENDIAN)(write_reg_addr & 0x3);
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write_reg_addr &= ~0x3;
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write_data = GpuSwap(write_data, endianness);
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XESETUINT32LE(p + GpuToCpu(packet_ptr, write_reg_addr),
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write_data);
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} else {
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// Register.
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WriteRegister(packet_ptr, write_reg_addr, write_data);
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}
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}
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}
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break;
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case PM4_EVENT_WRITE:
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// generate an event that creates a write to memory when completed
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{
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XETRACERB("[%.8X] Packet(%.8X): PM4_EVENT_WRITE (unimplemented!)",
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packet_ptr, packet);
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LOG_DATA(count);
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uint32_t initiator = READ_PTR();
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if (count == 1) {
|
|
// Just an event flag? Where does this write?
|
|
} else {
|
|
// Write to an address.
|
|
XEASSERTALWAYS();
|
|
ADVANCE_PTR(count - 1);
|
|
}
|
|
}
|
|
break;
|
|
case PM4_EVENT_WRITE_SHD:
|
|
// generate a VS|PS_done event
|
|
{
|
|
XETRACERB("[%.8X] Packet(%.8X): PM4_EVENT_WRITE_SHD",
|
|
packet_ptr, packet);
|
|
LOG_DATA(count);
|
|
uint32_t initiator = READ_PTR();
|
|
uint32_t address = READ_PTR();
|
|
uint32_t value = READ_PTR();
|
|
// Writeback initiator.
|
|
WriteRegister(packet_ptr, XE_GPU_REG_VGT_EVENT_INITIATOR,
|
|
initiator & 0x1F);
|
|
uint32_t data_value;
|
|
if ((initiator >> 31) & 0x1) {
|
|
// Write counter (GPU vblank counter?).
|
|
data_value = counter_;
|
|
} else {
|
|
// Write value.
|
|
data_value = value;
|
|
}
|
|
XE_GPU_ENDIAN endianness = (XE_GPU_ENDIAN)(address & 0x3);
|
|
address &= ~0x3;
|
|
data_value = GpuSwap(data_value, endianness);
|
|
XESETUINT32LE(p + GpuToCpu(packet_ptr, address), data_value);
|
|
}
|
|
break;
|
|
|
|
case PM4_DRAW_INDX:
|
|
// initiate fetch of index buffer and draw
|
|
{
|
|
XETRACERB("[%.8X] Packet(%.8X): PM4_DRAW_INDX",
|
|
packet_ptr, packet);
|
|
LOG_DATA(count);
|
|
// d0 = viz query info
|
|
uint32_t d0 = READ_PTR();
|
|
uint32_t d1 = READ_PTR();
|
|
uint32_t index_count = d1 >> 16;
|
|
uint32_t prim_type = d1 & 0x3F;
|
|
uint32_t src_sel = (d1 >> 6) & 0x3;
|
|
if (src_sel == 0x0) {
|
|
uint32_t index_base = READ_PTR();
|
|
uint32_t index_size = READ_PTR();
|
|
uint32_t endianness = index_size >> 29;
|
|
index_size &= 0x00FFFFFF;
|
|
bool index_32bit = (d1 >> 11) & 0x1;
|
|
index_size *= index_32bit ? 4 : 2;
|
|
driver_->DrawIndexBuffer(
|
|
(XE_GPU_PRIMITIVE_TYPE)prim_type,
|
|
index_32bit, index_count, index_base, index_size, endianness);
|
|
} else if (src_sel == 0x2) {
|
|
driver_->DrawIndexAuto(
|
|
(XE_GPU_PRIMITIVE_TYPE)prim_type,
|
|
index_count);
|
|
} else {
|
|
// Unknown source select.
|
|
XEASSERTALWAYS();
|
|
}
|
|
}
|
|
break;
|
|
case PM4_DRAW_INDX_2:
|
|
// draw using supplied indices in packet
|
|
{
|
|
XETRACERB("[%.8X] Packet(%.8X): PM4_DRAW_INDX_2",
|
|
packet_ptr, packet);
|
|
LOG_DATA(count);
|
|
uint32_t d0 = READ_PTR();
|
|
uint32_t index_count = d0 >> 16;
|
|
uint32_t prim_type = d0 & 0x3F;
|
|
uint32_t src_sel = (d0 >> 6) & 0x3;
|
|
XEASSERT(src_sel == 0x2); // 'SrcSel=AutoIndex'
|
|
driver_->DrawIndexAuto(
|
|
(XE_GPU_PRIMITIVE_TYPE)prim_type,
|
|
index_count);
|
|
}
|
|
break;
|
|
|
|
case PM4_SET_CONSTANT:
|
|
// load constant into chip and to memory
|
|
{
|
|
XETRACERB("[%.8X] Packet(%.8X): PM4_SET_CONSTANT",
|
|
packet_ptr, packet);
|
|
// PM4_REG(reg) ((0x4 << 16) | (GSL_HAL_SUBBLOCK_OFFSET(reg)))
|
|
// reg - 0x2000
|
|
uint32_t offset_type = READ_PTR();
|
|
uint32_t index = offset_type & 0x7FF;
|
|
uint32_t type = (offset_type >> 16) & 0xFF;
|
|
switch (type) {
|
|
case 0x4: // REGISTER
|
|
index += 0x2000; // registers
|
|
for (uint32_t n = 0; n < count - 1; n++, index++) {
|
|
uint32_t data = READ_PTR();
|
|
const char* reg_name = xenos::GetRegisterName(index);
|
|
XETRACERB("[%.8X] %.8X -> %.4X %s",
|
|
packet_ptr + (1 + n) * 4,
|
|
data, index, reg_name ? reg_name : "");
|
|
WriteRegister(packet_ptr, index, data);
|
|
}
|
|
break;
|
|
default:
|
|
XEASSERTALWAYS();
|
|
break;
|
|
}
|
|
}
|
|
break;
|
|
case PM4_LOAD_ALU_CONSTANT:
|
|
// load constants from memory
|
|
{
|
|
XETRACERB("[%.8X] Packet(%.8X): PM4_LOAD_ALU_CONSTANT",
|
|
packet_ptr, packet);
|
|
uint32_t address = READ_PTR();
|
|
address &= 0x3FFFFFFF;
|
|
uint32_t offset_type = READ_PTR();
|
|
uint32_t index = offset_type & 0x7FF;
|
|
uint32_t size = READ_PTR();
|
|
size &= 0xFFF;
|
|
index += 0x4000; // alu constants
|
|
for (uint32_t n = 0; n < size; n++, index++) {
|
|
uint32_t data = XEGETUINT32BE(
|
|
p + GpuToCpu(packet_ptr, address + n * 4));
|
|
const char* reg_name = xenos::GetRegisterName(index);
|
|
XETRACERB("[%.8X] %.8X -> %.4X %s",
|
|
packet_ptr,
|
|
data, index, reg_name ? reg_name : "");
|
|
WriteRegister(packet_ptr, index, data);
|
|
}
|
|
}
|
|
break;
|
|
|
|
case PM4_IM_LOAD:
|
|
// load sequencer instruction memory (pointer-based)
|
|
{
|
|
XETRACERB("[%.8X] Packet(%.8X): PM4_IM_LOAD",
|
|
packet_ptr, packet);
|
|
LOG_DATA(count);
|
|
uint32_t addr_type = READ_PTR();
|
|
uint32_t type = addr_type & 0x3;
|
|
uint32_t addr = addr_type & ~0x3;
|
|
uint32_t start_size = READ_PTR();
|
|
uint32_t start = start_size >> 16;
|
|
uint32_t size = start_size & 0xFFFF; // dwords
|
|
XEASSERT(start == 0);
|
|
driver_->SetShader(
|
|
(XE_GPU_SHADER_TYPE)type,
|
|
GpuToCpu(packet_ptr, addr),
|
|
start,
|
|
size * 4);
|
|
}
|
|
break;
|
|
case PM4_IM_LOAD_IMMEDIATE:
|
|
// load sequencer instruction memory (code embedded in packet)
|
|
{
|
|
XETRACERB("[%.8X] Packet(%.8X): PM4_IM_LOAD_IMMEDIATE",
|
|
packet_ptr, packet);
|
|
LOG_DATA(count);
|
|
uint32_t type = READ_PTR();
|
|
uint32_t start_size = READ_PTR();
|
|
uint32_t start = start_size >> 16;
|
|
uint32_t size = start_size & 0xFFFF; // dwords
|
|
XEASSERT(start == 0);
|
|
// TODO(benvanik): figure out if this could wrap.
|
|
XEASSERT(args.ptr + size * 4 < args.max_address);
|
|
driver_->SetShader(
|
|
(XE_GPU_SHADER_TYPE)type,
|
|
args.ptr,
|
|
start,
|
|
size * 4);
|
|
ADVANCE_PTR(size);
|
|
}
|
|
break;
|
|
|
|
case PM4_INVALIDATE_STATE:
|
|
// selective invalidation of state pointers
|
|
{
|
|
XETRACERB("[%.8X] Packet(%.8X): PM4_INVALIDATE_STATE",
|
|
packet_ptr, packet);
|
|
LOG_DATA(count);
|
|
uint32_t mask = READ_PTR();
|
|
driver_->InvalidateState(mask);
|
|
}
|
|
break;
|
|
|
|
case PM4_SET_BIN_MASK_LO:
|
|
{
|
|
uint32_t value = READ_PTR();
|
|
XETRACERB("[%.8X] Packet(%.8X): PM4_SET_BIN_MASK_LO = %.8X",
|
|
packet_ptr, packet, value);
|
|
}
|
|
break;
|
|
case PM4_SET_BIN_MASK_HI:
|
|
{
|
|
uint32_t value = READ_PTR();
|
|
XETRACERB("[%.8X] Packet(%.8X): PM4_SET_BIN_MASK_HI = %.8X",
|
|
packet_ptr, packet, value);
|
|
}
|
|
break;
|
|
case PM4_SET_BIN_SELECT_LO:
|
|
{
|
|
uint32_t value = READ_PTR();
|
|
XETRACERB("[%.8X] Packet(%.8X): PM4_SET_BIN_SELECT_LO = %.8X",
|
|
packet_ptr, packet, value);
|
|
}
|
|
break;
|
|
case PM4_SET_BIN_SELECT_HI:
|
|
{
|
|
uint32_t value = READ_PTR();
|
|
XETRACERB("[%.8X] Packet(%.8X): PM4_SET_BIN_SELECT_HI = %.8X",
|
|
packet_ptr, packet, value);
|
|
}
|
|
break;
|
|
|
|
// Ignored packets - useful if breaking on the default handler below.
|
|
case 0x50: // 0xC0015000 usually 2 words, 0xFFFFFFFF / 0x00000000
|
|
XETRACERB("[%.8X] Packet(%.8X): unknown!",
|
|
packet_ptr, packet);
|
|
LOG_DATA(count);
|
|
ADVANCE_PTR(count);
|
|
break;
|
|
|
|
default:
|
|
XETRACERB("[%.8X] Packet(%.8X): unknown!",
|
|
packet_ptr, packet);
|
|
LOG_DATA(count);
|
|
ADVANCE_PTR(count);
|
|
break;
|
|
}
|
|
|
|
return 1 + count;
|
|
}
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void RingBufferWorker::WriteRegister(
|
|
uint32_t packet_ptr, uint32_t index, uint32_t value) {
|
|
RegisterFile* regs = driver_->register_file();
|
|
XEASSERT(index < kXEGpuRegisterCount);
|
|
regs->values[index].u32 = value;
|
|
|
|
// Scratch register writeback.
|
|
if (index >= XE_GPU_REG_SCRATCH_REG0 && index <= XE_GPU_REG_SCRATCH_REG7) {
|
|
uint32_t scratch_reg = index - XE_GPU_REG_SCRATCH_REG0;
|
|
if ((1 << scratch_reg) & regs->values[XE_GPU_REG_SCRATCH_UMSK].u32) {
|
|
// Enabled - write to address.
|
|
uint8_t* p = xe_memory_addr(memory_);
|
|
uint32_t scratch_addr = regs->values[XE_GPU_REG_SCRATCH_ADDR].u32;
|
|
uint32_t mem_addr = scratch_addr + (scratch_reg * 4);
|
|
XESETUINT32BE(p + GpuToCpu(primary_buffer_ptr_, mem_addr), value);
|
|
}
|
|
}
|
|
}
|