90 lines
4.6 KiB
C++
90 lines
4.6 KiB
C++
/**
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******************************************************************************
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* Xenia : Xbox 360 Emulator Research Project *
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******************************************************************************
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* Copyright 2013 Ben Vanik. All rights reserved. *
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* Released under the BSD license - see LICENSE in the root for more details. *
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******************************************************************************
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*/
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#ifndef XENIA_GPU_XENOS_PACKETS_H_
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#define XENIA_GPU_XENOS_PACKETS_H_
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#include <xenia/core.h>
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namespace xe {
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namespace gpu {
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namespace xenos {
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// Opcodes (IT_OPCODE) for Type-3 commands in the ringbuffer.
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// https://github.com/freedreno/amd-gpu/blob/master/include/api/gsl_pm4types.h
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// Not sure if all of these are used.
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enum Type3Opcode {
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PM4_ME_INIT = 0x48, // initialize CP's micro-engine
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PM4_NOP = 0x10, // skip N 32-bit words to get to the next packet
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PM4_INDIRECT_BUFFER = 0x3f, // indirect buffer dispatch. prefetch parser uses this packet type to determine whether to pre-fetch the IB
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PM4_INDIRECT_BUFFER_PFD = 0x37, // indirect buffer dispatch. same as IB, but init is pipelined
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PM4_WAIT_FOR_IDLE = 0x26, // wait for the IDLE state of the engine
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PM4_WAIT_REG_MEM = 0x3c, // wait until a register or memory location is a specific value
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PM4_WAIT_REG_EQ = 0x52, // wait until a register location is equal to a specific value
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PM4_WAT_REG_GTE = 0x53, // wait until a register location is >= a specific value
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PM4_WAIT_UNTIL_READ = 0x5c, // wait until a read completes
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PM4_WAIT_IB_PFD_COMPLETE = 0x5d, // wait until all base/size writes from an IB_PFD packet have completed
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PM4_REG_RMW = 0x21, // register read/modify/write
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PM4_REG_TO_MEM = 0x3e, // reads register in chip and writes to memory
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PM4_MEM_WRITE = 0x3d, // write N 32-bit words to memory
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PM4_MEM_WRITE_CNTR = 0x4f, // write CP_PROG_COUNTER value to memory
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PM4_COND_EXEC = 0x44, // conditional execution of a sequence of packets
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PM4_COND_WRITE = 0x45, // conditional write to memory or register
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PM4_EVENT_WRITE = 0x46, // generate an event that creates a write to memory when completed
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PM4_EVENT_WRITE_SHD = 0x58, // generate a VS|PS_done event
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PM4_EVENT_WRITE_CFL = 0x59, // generate a cache flush done event
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PM4_EVENT_WRITE_ZPD = 0x5b, // generate a z_pass done event
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PM4_DRAW_INDX = 0x22, // initiate fetch of index buffer and draw
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PM4_DRAW_INDX_2 = 0x36, // draw using supplied indices in packet
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PM4_DRAW_INDX_BIN = 0x34, // initiate fetch of index buffer and binIDs and draw
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PM4_DRAW_INDX_2_BIN = 0x35, // initiate fetch of bin IDs and draw using supplied indices
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PM4_VIZ_QUERY = 0x23, // begin/end initiator for viz query extent processing
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PM4_SET_STATE = 0x25, // fetch state sub-blocks and initiate shader code DMAs
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PM4_SET_CONSTANT = 0x2d, // load constant into chip and to memory
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PM4_LOAD_ALU_CONSTANT = 0x2f, // load constants from memory
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PM4_IM_LOAD = 0x27, // load sequencer instruction memory (pointer-based)
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PM4_IM_LOAD_IMMEDIATE = 0x2b, // load sequencer instruction memory (code embedded in packet)
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PM4_LOAD_CONSTANT_CONTEXT = 0x2e, // load constants from a location in memory
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PM4_INVALIDATE_STATE = 0x3b, // selective invalidation of state pointers
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PM4_SET_SHADER_BASES = 0x4A, // dynamically changes shader instruction memory partition
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PM4_SET_BIN_BASE_OFFSET = 0x4B, // program an offset that will added to the BIN_BASE value of the 3D_DRAW_INDX_BIN packet
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PM4_SET_BIN_MASK = 0x50, // sets the 64-bit BIN_MASK register in the PFP
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PM4_SET_BIN_SELECT = 0x51, // sets the 64-bit BIN_SELECT register in the PFP
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PM4_CONTEXT_UPDATE = 0x5e, // updates the current context, if needed
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PM4_INTERRUPT = 0x54, // generate interrupt from the command stream
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PM4_IM_STORE = 0x2c, // copy sequencer instruction memory to system memory
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// Tiled rendering:
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// https://www.google.com/patents/US20060055701
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PM4_SET_BIN_MASK_LO = 0x60,
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PM4_SET_BIN_MASK_HI = 0x61,
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PM4_SET_BIN_SELECT_LO = 0x62,
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PM4_SET_BIN_SELECT_HI = 0x63,
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};
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} // namespace xenos
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} // namespace gpu
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} // namespace xe
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#endif // XENIA_GPU_XENOS_PACKETS_H_
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