2737 lines
73 KiB
ArmAsm
2737 lines
73 KiB
ArmAsm
test_fadd_1_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
fadd f3, f1, f2
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|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
|
|
test_fadd_1_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_2_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
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#_ REGISTER_IN f2 0x8000000000000000
|
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fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
|
|
test_fadd_2_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_3_GEN:
|
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#_ REGISTER_IN f1 0x0000000000000000
|
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#_ REGISTER_IN f2 0x0000000000000001
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fadd f3, f1, f2
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|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
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#_ REGISTER_OUT f2 0x0000000000000001
|
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#_ REGISTER_OUT f3 0x0000000000000001
|
|
|
|
test_fadd_3_cr_GEN:
|
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#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
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fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_4_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
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#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
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fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
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#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
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#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
|
|
test_fadd_4_cr_GEN:
|
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#_ REGISTER_IN f1 0x0000000000000000
|
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#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
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fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
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#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
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#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_5_GEN:
|
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x3FF0000000000000
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fadd f3, f1, f2
|
|
blr
|
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#_ REGISTER_OUT f1 0x0000000000000000
|
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#_ REGISTER_OUT f2 0x3FF0000000000000
|
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#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
|
|
test_fadd_5_cr_GEN:
|
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#_ REGISTER_IN f1 0x0000000000000000
|
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#_ REGISTER_IN f2 0x3FF0000000000000
|
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fadd. f3, f1, f2
|
|
blr
|
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#_ REGISTER_OUT f1 0x0000000000000000
|
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#_ REGISTER_OUT f2 0x3FF0000000000000
|
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#_ REGISTER_OUT f3 0x3FF0000000000000
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#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_6_GEN:
|
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#_ REGISTER_IN f1 0x0000000000000000
|
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#_ REGISTER_IN f2 0xBFF0000000000000
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fadd f3, f1, f2
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blr
|
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#_ REGISTER_OUT f1 0x0000000000000000
|
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#_ REGISTER_OUT f2 0xBFF0000000000000
|
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#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
|
|
test_fadd_6_cr_GEN:
|
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#_ REGISTER_IN f1 0x0000000000000000
|
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#_ REGISTER_IN f2 0xBFF0000000000000
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fadd. f3, f1, f2
|
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blr
|
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#_ REGISTER_OUT f1 0x0000000000000000
|
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#_ REGISTER_OUT f2 0xBFF0000000000000
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#_ REGISTER_OUT f3 0xBFF0000000000000
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#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_7_GEN:
|
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#_ REGISTER_IN f1 0x0000000000000000
|
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#_ REGISTER_IN f2 0xC1E0000000000000
|
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fadd f3, f1, f2
|
|
blr
|
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#_ REGISTER_OUT f1 0x0000000000000000
|
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#_ REGISTER_OUT f2 0xC1E0000000000000
|
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#_ REGISTER_OUT f3 0xC1E0000000000000
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|
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test_fadd_7_cr_GEN:
|
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#_ REGISTER_IN f1 0x0000000000000000
|
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#_ REGISTER_IN f2 0xC1E0000000000000
|
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fadd. f3, f1, f2
|
|
blr
|
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0xC1E0000000000000
|
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#_ REGISTER_OUT f3 0xC1E0000000000000
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#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_8_GEN:
|
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#_ REGISTER_IN f1 0x0000000000000000
|
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#_ REGISTER_IN f2 0x41DFFFFFFFC00000
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fadd f3, f1, f2
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blr
|
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
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#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
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test_fadd_8_cr_GEN:
|
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#_ REGISTER_IN f1 0x0000000000000000
|
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#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
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fadd. f3, f1, f2
|
|
blr
|
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#_ REGISTER_OUT f1 0x0000000000000000
|
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#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
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#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
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#_ REGISTER_OUT cr 0x00000000
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|
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test_fadd_9_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
|
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#_ REGISTER_IN f2 0x7FF0000000000000
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fadd f3, f1, f2
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blr
|
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#_ REGISTER_OUT f1 0x0000000000000000
|
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#_ REGISTER_OUT f2 0x7FF0000000000000
|
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#_ REGISTER_OUT f3 0x7FF0000000000000
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|
|
|
test_fadd_9_cr_GEN:
|
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#_ REGISTER_IN f1 0x0000000000000000
|
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#_ REGISTER_IN f2 0x7FF0000000000000
|
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fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
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#_ REGISTER_OUT f3 0x7FF0000000000000
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#_ REGISTER_OUT cr 0x00000000
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test_fadd_10_GEN:
|
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#_ REGISTER_IN f1 0x0000000000000000
|
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#_ REGISTER_IN f2 0xFFF0000000000000
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|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
|
|
test_fadd_10_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
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#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
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#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_11_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
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#_ REGISTER_IN f2 0xFFF8000000000000
|
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fadd f3, f1, f2
|
|
blr
|
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#_ REGISTER_OUT f1 0x0000000000000000
|
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#_ REGISTER_OUT f2 0xFFF8000000000000
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#_ REGISTER_OUT f3 0xFFF8000000000000
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|
|
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test_fadd_11_cr_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0xFFF8000000000000
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fadd. f3, f1, f2
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blr
|
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#_ REGISTER_OUT f1 0x0000000000000000
|
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#_ REGISTER_OUT f2 0xFFF8000000000000
|
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#_ REGISTER_OUT f3 0xFFF8000000000000
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#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_12_GEN:
|
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#_ REGISTER_IN f1 0x0000000000000000
|
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#_ REGISTER_IN f2 0xFFF4000000000000
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fadd f3, f1, f2
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blr
|
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0xFFF4000000000000
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#_ REGISTER_OUT f3 0xFFFC000000000000
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|
|
|
test_fadd_12_cr_GEN:
|
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#_ REGISTER_IN f1 0x0000000000000000
|
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#_ REGISTER_IN f2 0xFFF4000000000000
|
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fadd. f3, f1, f2
|
|
blr
|
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#_ REGISTER_OUT f1 0x0000000000000000
|
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#_ REGISTER_OUT f2 0xFFF4000000000000
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#_ REGISTER_OUT f3 0xFFFC000000000000
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#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fadd_13_GEN:
|
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#_ REGISTER_IN f1 0x8000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
|
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fadd f3, f1, f2
|
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blr
|
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#_ REGISTER_OUT f1 0x8000000000000000
|
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#_ REGISTER_OUT f2 0x0000000000000000
|
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#_ REGISTER_OUT f3 0x0000000000000000
|
|
|
|
test_fadd_13_cr_GEN:
|
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#_ REGISTER_IN f1 0x8000000000000000
|
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#_ REGISTER_IN f2 0x0000000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
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#_ REGISTER_OUT f1 0x8000000000000000
|
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#_ REGISTER_OUT f2 0x0000000000000000
|
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#_ REGISTER_OUT f3 0x0000000000000000
|
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#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_14_GEN:
|
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#_ REGISTER_IN f1 0x8000000000000000
|
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#_ REGISTER_IN f2 0x8000000000000000
|
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fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
|
|
test_fadd_14_cr_GEN:
|
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#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
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#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
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#_ REGISTER_OUT f3 0x8000000000000000
|
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#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_15_GEN:
|
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#_ REGISTER_IN f1 0x8000000000000000
|
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#_ REGISTER_IN f2 0x0000000000000001
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
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#_ REGISTER_OUT f3 0x0000000000000001
|
|
|
|
test_fadd_15_cr_GEN:
|
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#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_16_GEN:
|
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#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
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fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
|
|
test_fadd_16_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_17_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
|
|
test_fadd_17_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_18_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
|
|
test_fadd_18_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_19_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
|
|
test_fadd_19_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_20_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
|
|
test_fadd_20_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_21_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
|
|
test_fadd_21_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_22_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
|
|
test_fadd_22_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_23_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
|
|
test_fadd_23_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_24_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
|
|
test_fadd_24_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fadd_25_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
|
|
test_fadd_25_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_26_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
|
|
test_fadd_26_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_27_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000002
|
|
|
|
test_fadd_27_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000002
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_28_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0010000000000000
|
|
|
|
test_fadd_28_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0010000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_29_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
|
|
test_fadd_29_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fadd_30_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
|
|
test_fadd_30_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fadd_31_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
|
|
test_fadd_31_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fadd_32_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
|
|
test_fadd_32_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fadd_33_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
|
|
test_fadd_33_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_34_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
|
|
test_fadd_34_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_35_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
|
|
test_fadd_35_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_36_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
|
|
test_fadd_36_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fadd_37_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
|
|
test_fadd_37_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_38_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
|
|
test_fadd_38_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_39_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0010000000000000
|
|
|
|
test_fadd_39_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0010000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_40_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x001FFFFFFFFFFFFE
|
|
|
|
test_fadd_40_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x001FFFFFFFFFFFFE
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_41_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
|
|
test_fadd_41_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fadd_42_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
|
|
test_fadd_42_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fadd_43_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
|
|
test_fadd_43_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fadd_44_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
|
|
test_fadd_44_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fadd_45_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
|
|
test_fadd_45_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_46_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
|
|
test_fadd_46_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_47_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
|
|
test_fadd_47_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_48_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
|
|
test_fadd_48_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fadd_49_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
|
|
test_fadd_49_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_50_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
|
|
test_fadd_50_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_51_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
|
|
test_fadd_51_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fadd_52_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
|
|
test_fadd_52_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fadd_53_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x4000000000000000
|
|
|
|
test_fadd_53_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x4000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_54_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
|
|
test_fadd_54_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_55_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1DFFFFFFFC00000
|
|
|
|
test_fadd_55_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_56_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41E0000000000000
|
|
|
|
test_fadd_56_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_57_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
|
|
test_fadd_57_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_58_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
|
|
test_fadd_58_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_59_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
|
|
test_fadd_59_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_60_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
|
|
test_fadd_60_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fadd_61_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
|
|
test_fadd_61_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_62_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
|
|
test_fadd_62_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_63_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
|
|
test_fadd_63_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fadd_64_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
|
|
test_fadd_64_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fadd_65_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
|
|
test_fadd_65_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_66_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC000000000000000
|
|
|
|
test_fadd_66_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_67_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000200000
|
|
|
|
test_fadd_67_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000200000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_68_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFF800000
|
|
|
|
test_fadd_68_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFF800000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_69_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
|
|
test_fadd_69_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_70_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
|
|
test_fadd_70_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_71_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
|
|
test_fadd_71_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_72_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
|
|
test_fadd_72_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fadd_73_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
|
|
test_fadd_73_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_74_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
|
|
test_fadd_74_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_75_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
|
|
test_fadd_75_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fadd_76_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
|
|
test_fadd_76_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fadd_77_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1DFFFFFFFC00000
|
|
|
|
test_fadd_77_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_78_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000200000
|
|
|
|
test_fadd_78_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000200000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_79_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1F0000000000000
|
|
|
|
test_fadd_79_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1F0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_80_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
|
|
test_fadd_80_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_81_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
|
|
test_fadd_81_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_82_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
|
|
test_fadd_82_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_83_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
|
|
test_fadd_83_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_84_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
|
|
test_fadd_84_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fadd_85_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
|
|
test_fadd_85_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_86_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
|
|
test_fadd_86_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_87_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
|
|
test_fadd_87_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fadd_88_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
|
|
test_fadd_88_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fadd_89_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41E0000000000000
|
|
|
|
test_fadd_89_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_90_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFF800000
|
|
|
|
test_fadd_90_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFF800000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_91_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
|
|
test_fadd_91_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_92_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41EFFFFFFFC00000
|
|
|
|
test_fadd_92_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41EFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_93_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
|
|
test_fadd_93_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_94_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
|
|
test_fadd_94_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_95_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
|
|
test_fadd_95_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_96_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
|
|
test_fadd_96_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fadd_97_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
|
|
test_fadd_97_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_98_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
|
|
test_fadd_98_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_99_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
|
|
test_fadd_99_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_100_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
|
|
test_fadd_100_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_101_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
|
|
test_fadd_101_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_102_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
|
|
test_fadd_102_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_103_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
|
|
test_fadd_103_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_104_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
|
|
test_fadd_104_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_105_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
|
|
test_fadd_105_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_106_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF8000000000000
|
|
|
|
test_fadd_106_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fadd_107_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
|
|
test_fadd_107_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_108_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
|
|
test_fadd_108_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fadd_109_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
|
|
test_fadd_109_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_110_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
|
|
test_fadd_110_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_111_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
|
|
test_fadd_111_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_112_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
|
|
test_fadd_112_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_113_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
|
|
test_fadd_113_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_114_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
|
|
test_fadd_114_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_115_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
|
|
test_fadd_115_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_116_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
|
|
test_fadd_116_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_117_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF8000000000000
|
|
|
|
test_fadd_117_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fadd_118_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
|
|
test_fadd_118_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_119_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
|
|
test_fadd_119_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_120_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
|
|
test_fadd_120_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fadd_121_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
|
|
test_fadd_121_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_122_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
|
|
test_fadd_122_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_123_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
|
|
test_fadd_123_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_124_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
|
|
test_fadd_124_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_125_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
|
|
test_fadd_125_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_126_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
|
|
test_fadd_126_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_127_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
|
|
test_fadd_127_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_128_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
|
|
test_fadd_128_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_129_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
|
|
test_fadd_129_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_130_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
|
|
test_fadd_130_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_131_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
|
|
test_fadd_131_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fadd_132_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
|
|
test_fadd_132_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fadd_133_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
|
|
test_fadd_133_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fadd_134_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
|
|
test_fadd_134_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fadd_135_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
|
|
test_fadd_135_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fadd_136_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
|
|
test_fadd_136_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fadd_137_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
|
|
test_fadd_137_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fadd_138_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
|
|
test_fadd_138_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fadd_139_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
|
|
test_fadd_139_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fadd_140_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
|
|
test_fadd_140_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fadd_141_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
|
|
test_fadd_141_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fadd_142_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
|
|
test_fadd_142_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fadd_143_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
|
|
test_fadd_143_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fadd_144_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
fadd f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
|
|
test_fadd_144_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
fadd. f3, f1, f2
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|