5851 lines
223 KiB
ArmAsm
5851 lines
223 KiB
ArmAsm
test_vslw_1_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_2_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_3_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_4_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_5_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_6_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_7_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_8_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_9_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_10_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_11_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_12_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_13_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_14_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_15_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_16_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_17_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_18_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_19_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_20_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_21_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_22_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_23_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_24_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_25_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_26_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
|
|
|
|
test_vslw_27_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [80000000, 00000001, 00000001, 00000001]
|
|
|
|
test_vslw_28_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00000008, 00000080, 00000800, 00008000]
|
|
|
|
test_vslw_29_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [00002000, 00002000, 00002000, 00002000]
|
|
|
|
test_vslw_30_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [00080000, 00800000, 08000000, 80000000]
|
|
|
|
test_vslw_31_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [00000001, 00000001, 80000000, 80000000]
|
|
|
|
test_vslw_32_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [00000010, 00000010, 00000010, 00000010]
|
|
|
|
test_vslw_33_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [00000080, 00000080, 00000080, 00000080]
|
|
|
|
test_vslw_34_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [00000100, 00000100, 00000100, 00000100]
|
|
|
|
test_vslw_35_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [00040000, 00040000, 00040000, 00040000]
|
|
|
|
test_vslw_36_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [01000000, 00000002, 00000010, 00000100]
|
|
|
|
test_vslw_37_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [00000001, 00000001, 00002000, 00080000]
|
|
|
|
test_vslw_38_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
|
|
|
|
test_vslw_39_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00000008, 00000080, 00000800, 00008000]
|
|
|
|
test_vslw_40_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [00010000, 00000001, 80000000, 80000000]
|
|
|
|
test_vslw_41_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [00000001, 00000001, 00002000, 00080000]
|
|
|
|
test_vslw_42_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
|
|
|
|
test_vslw_43_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00002000, 00002000, 00002000, 00000008]
|
|
|
|
test_vslw_44_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [08000000, 80000000, 00000008, 00000080]
|
|
|
|
test_vslw_45_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [40000000, 40000000, 40000000, 40000000]
|
|
|
|
test_vslw_46_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [20000000, 80000000, 00000002, 00000008]
|
|
|
|
test_vslw_47_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [40000000, 00000002, 20000000, 00000004]
|
|
|
|
test_vslw_48_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00000002, 80000000, 80000000, 00000001]
|
|
|
|
test_vslw_49_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000001, 80000000, 80000000, 00000001]
|
|
|
|
test_vslw_50_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 80000000]
|
|
|
|
test_vslw_51_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
|
|
test_vslw_52_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [0001FFFE, FFFE0000, 00000000, FFFE0000]
|
|
|
|
test_vslw_53_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [0007FFF8, FF800000, 00000000, 80000000]
|
|
|
|
test_vslw_54_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [1FFFE000, E0000000, 00000000, E0000000]
|
|
|
|
test_vslw_55_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [FFF80000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_56_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, 00000000]
|
|
|
|
test_vslw_57_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [000FFFF0, FFF00000, 00000000, FFF00000]
|
|
|
|
test_vslw_58_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [007FFF80, FF800000, 00000000, FF800000]
|
|
|
|
test_vslw_59_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [00FFFF00, FF000000, 00000000, FF000000]
|
|
|
|
test_vslw_60_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [FFFC0000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_61_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [FF000000, FFFE0000, 00000000, FF000000]
|
|
|
|
test_vslw_62_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, 00000000]
|
|
|
|
test_vslw_63_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
|
|
test_vslw_64_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [0007FFF8, FF800000, 00000000, 80000000]
|
|
|
|
test_vslw_65_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [FFFF0000, FFFF0000, 00000000, 00000000]
|
|
|
|
test_vslw_66_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, 00000000]
|
|
|
|
test_vslw_67_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
|
|
test_vslw_68_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [1FFFE000, E0000000, 00000000, FFF80000]
|
|
|
|
test_vslw_69_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [F8000000, 00000000, 00000000, FF800000]
|
|
|
|
test_vslw_70_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [C0000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_71_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [E0000000, 00000000, 00000000, FFF80000]
|
|
|
|
test_vslw_72_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [C0000000, FFFE0000, 00000000, FFFC0000]
|
|
|
|
test_vslw_73_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [0001FFFE, 00000000, 00000000, FFFF0000]
|
|
|
|
test_vslw_74_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [0000FFFF, 00000000, 00000000, FFFF0000]
|
|
|
|
test_vslw_75_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [80000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_76_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
|
|
test_vslw_77_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [00020406, 080A0C0E, 10121416, 181A1C1E]
|
|
|
|
test_vslw_78_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [80000000, 04050607, 08090A0B, 0C0D0E0F]
|
|
|
|
test_vslw_79_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [20406000, A0C0E000, 21416000, A1C1E000]
|
|
|
|
test_vslw_80_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [10180000, 03800000, 58000000, 80000000]
|
|
|
|
test_vslw_81_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [00010203, 04050607, 80000000, 80000000]
|
|
|
|
test_vslw_82_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [00102030, 40506070, 8090A0B0, C0D0E0F0]
|
|
|
|
test_vslw_83_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [00810180, 02830380, 04850580, 06870780]
|
|
|
|
test_vslw_84_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [01020300, 05060700, 090A0B00, 0D0E0F00]
|
|
|
|
test_vslw_85_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [080C0000, 181C0000, 282C0000, 383C0000]
|
|
|
|
test_vslw_86_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [03000000, 080A0C0E, 8090A0B0, 0D0E0F00]
|
|
|
|
test_vslw_87_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [00010203, 04050607, 21416000, 70780000]
|
|
|
|
test_vslw_88_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
|
|
test_vslw_89_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00081018, 02830380, 48505800, 87078000]
|
|
|
|
test_vslw_90_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [02030000, 04050607, 80000000, 80000000]
|
|
|
|
test_vslw_91_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [00010203, 04050607, 21416000, 70780000]
|
|
|
|
test_vslw_92_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
|
|
test_vslw_93_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [20406000, A0C0E000, 21416000, 60687078]
|
|
|
|
test_vslw_94_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [18000000, 80000000, 40485058, 06870780]
|
|
|
|
test_vslw_95_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [C0000000, C0000000, C0000000, C0000000]
|
|
|
|
test_vslw_96_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [60000000, 80000000, 10121416, 60687078]
|
|
|
|
test_vslw_97_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [C0000000, 080A0C0E, 60000000, 3034383C]
|
|
|
|
test_vslw_98_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00020406, 80000000, 80000000, 0C0D0E0F]
|
|
|
|
test_vslw_99_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00010203, 80000000, 80000000, 0C0D0E0F]
|
|
|
|
test_vslw_100_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 80000000]
|
|
|
|
test_vslw_101_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
|
|
test_vslw_102_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [001A001A, 001A001A, 001A001A, 001A001A]
|
|
|
|
test_vslw_103_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [80000000, 000D000D, 000D000D, 000D000D]
|
|
|
|
test_vslw_104_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00680068, 06800680, 68006800, 80068000]
|
|
|
|
test_vslw_105_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [00680000, 06800000, 68000000, 80000000]
|
|
|
|
test_vslw_106_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [000D000D, 000D000D, 80000000, 80000000]
|
|
|
|
test_vslw_107_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [00D000D0, 00D000D0, 00D000D0, 00D000D0]
|
|
|
|
test_vslw_108_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [06800680, 06800680, 06800680, 06800680]
|
|
|
|
test_vslw_109_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [0D000D00, 0D000D00, 0D000D00, 0D000D00]
|
|
|
|
test_vslw_110_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [00340000, 00340000, 00340000, 00340000]
|
|
|
|
test_vslw_111_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [0D000000, 001A001A, 00D000D0, 0D000D00]
|
|
|
|
test_vslw_112_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [000D000D, 000D000D, A001A000, 00680000]
|
|
|
|
test_vslw_113_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
|
|
test_vslw_114_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00680068, 06800680, 68006800, 80068000]
|
|
|
|
test_vslw_115_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [000D0000, 000D000D, 80000000, 80000000]
|
|
|
|
test_vslw_116_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [000D000D, 000D000D, A001A000, 00680000]
|
|
|
|
test_vslw_117_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
|
|
test_vslw_118_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [A001A000, A001A000, A001A000, 00680068]
|
|
|
|
test_vslw_119_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [68000000, 80000000, 00680068, 06800680]
|
|
|
|
test_vslw_120_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [40000000, 40000000, 40000000, 40000000]
|
|
|
|
test_vslw_121_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [A0000000, 80000000, 001A001A, 00680068]
|
|
|
|
test_vslw_122_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [40000000, 001A001A, A0000000, 00340034]
|
|
|
|
test_vslw_123_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [001A001A, 80000000, 80000000, 000D000D]
|
|
|
|
test_vslw_124_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [000D000D, 80000000, 80000000, 000D000D]
|
|
|
|
test_vslw_125_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 80000000]
|
|
|
|
test_vslw_126_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
|
|
test_vslw_127_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [00224466, 88AACCEE, 11335576, 99BBDDFE]
|
|
|
|
test_vslw_128_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [80000000, 44556677, 8899AABB, CCDDEEFF]
|
|
|
|
test_vslw_129_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00891198, 2AB33B80, CD55D800, F77F8000]
|
|
|
|
test_vslw_130_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [24466000, ACCEE000, 35576000, BDDFE000]
|
|
|
|
test_vslw_131_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [00112233, 44556677, 80000000, 80000000]
|
|
|
|
test_vslw_132_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [01122330, 45566770, 899AABB0, CDDEEFF0]
|
|
|
|
test_vslw_133_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [08911980, 2AB33B80, 4CD55D80, 6EF77F80]
|
|
|
|
test_vslw_134_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [11223300, 55667700, 99AABB00, DDEEFF00]
|
|
|
|
test_vslw_135_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [88CC0000, 99DC0000, AAEC0000, BBFC0000]
|
|
|
|
test_vslw_136_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [33000000, 88AACCEE, 899AABB0, DDEEFF00]
|
|
|
|
test_vslw_137_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [00112233, 44556677, 35576000, 77F80000]
|
|
|
|
test_vslw_138_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
|
|
test_vslw_139_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00891198, 2AB33B80, CD55D800, F77F8000]
|
|
|
|
test_vslw_140_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [22330000, 44556677, 80000000, 80000000]
|
|
|
|
test_vslw_141_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [00112233, 44556677, 35576000, 77F80000]
|
|
|
|
test_vslw_142_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
|
|
test_vslw_143_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [24466000, ACCEE000, 35576000, 66EF77F8]
|
|
|
|
test_vslw_144_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [98000000, 80000000, 44CD55D8, 6EF77F80]
|
|
|
|
test_vslw_145_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [C0000000, C0000000, C0000000, C0000000]
|
|
|
|
test_vslw_146_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [60000000, 80000000, 11335576, 66EF77F8]
|
|
|
|
test_vslw_147_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [C0000000, 88AACCEE, 60000000, 3377BBFC]
|
|
|
|
test_vslw_148_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00224466, 80000000, 80000000, CCDDEEFF]
|
|
|
|
test_vslw_149_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00112233, 80000000, 80000000, CCDDEEFF]
|
|
|
|
test_vslw_150_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 80000000]
|
|
|
|
test_vslw_151_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
|
|
test_vslw_152_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [01FFFE00, 0001FE00, FE0001FE, FFFE01FE]
|
|
|
|
test_vslw_153_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [00000000, 0000FF00, FF0000FF, FFFF00FF]
|
|
|
|
test_vslw_154_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [07FFF800, 007F8000, 0007F800, 807F8000]
|
|
|
|
test_vslw_155_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [FFE00000, 1FE00000, 001FE000, E01FE000]
|
|
|
|
test_vslw_156_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [F8000000, 80000000, F8000000, 80000000]
|
|
|
|
test_vslw_157_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [0FFFF000, 000FF000, F0000FF0, FFF00FF0]
|
|
|
|
test_vslw_158_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [7FFF8000, 007F8000, 80007F80, FF807F80]
|
|
|
|
test_vslw_159_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [FFFF0000, 00FF0000, 0000FF00, FF00FF00]
|
|
|
|
test_vslw_160_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [FC000000, FC000000, 03FC0000, 03FC0000]
|
|
|
|
test_vslw_161_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [00000000, 0001FE00, F0000FF0, FF00FF00]
|
|
|
|
test_vslw_162_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [00FFFF00, 0000FF00, 001FE000, 07F80000]
|
|
|
|
test_vslw_163_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
|
|
test_vslw_164_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [07FFF800, 007F8000, 0007F800, 807F8000]
|
|
|
|
test_vslw_165_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [FF000000, 0000FF00, 80000000, 80000000]
|
|
|
|
test_vslw_166_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [00FFFF00, 0000FF00, 001FE000, 07F80000]
|
|
|
|
test_vslw_167_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
|
|
test_vslw_168_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [FFE00000, 1FE00000, 001FE000, FFF807F8]
|
|
|
|
test_vslw_169_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, F80007F8, FF807F80]
|
|
|
|
test_vslw_170_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, C0000000, C0000000]
|
|
|
|
test_vslw_171_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, FE0001FE, FFF807F8]
|
|
|
|
test_vslw_172_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, 0001FE00, E0000000, FFFC03FC]
|
|
|
|
test_vslw_173_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [01FFFE00, 00000000, 80000000, FFFF00FF]
|
|
|
|
test_vslw_174_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00FFFF00, 00000000, 80000000, FFFF00FF]
|
|
|
|
test_vslw_175_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 80000000, 80000000]
|
|
|
|
test_vslw_176_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404]
|
|
|
|
test_vslw_177_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808]
|
|
|
|
test_vslw_178_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [00000000, 04040404, 04040404, 04040404]
|
|
|
|
test_vslw_179_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [20202020, 02020200, 20202000, 02020000]
|
|
|
|
test_vslw_180_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [80808000, 80808000, 80808000, 80808000]
|
|
|
|
test_vslw_181_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [20200000, 02000000, 20000000, 00000000]
|
|
|
|
test_vslw_182_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [04040404, 04040404, 00000000, 00000000]
|
|
|
|
test_vslw_183_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [02020200, 02020200, 02020200, 02020200]
|
|
|
|
test_vslw_184_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [04040400, 04040400, 04040400, 04040400]
|
|
|
|
test_vslw_185_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [10100000, 10100000, 10100000, 10100000]
|
|
|
|
test_vslw_186_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [04000000, 08080808, 40404040, 04040400]
|
|
|
|
test_vslw_187_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [04040404, 04040404, 80808000, 20200000]
|
|
|
|
test_vslw_188_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404]
|
|
|
|
test_vslw_189_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [20202020, 02020200, 20202000, 02020000]
|
|
|
|
test_vslw_190_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [04040000, 04040404, 00000000, 00000000]
|
|
|
|
test_vslw_191_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [04040404, 04040404, 80808000, 20200000]
|
|
|
|
test_vslw_192_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404]
|
|
|
|
test_vslw_193_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [80808000, 80808000, 80808000, 20202020]
|
|
|
|
test_vslw_194_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [20000000, 00000000, 20202020, 02020200]
|
|
|
|
test_vslw_195_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_196_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [80000000, 00000000, 08080808, 20202020]
|
|
|
|
test_vslw_197_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, 08080808, 80000000, 10101010]
|
|
|
|
test_vslw_198_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [08080808, 00000000, 00000000, 04040404]
|
|
|
|
test_vslw_199_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [04040404, 00000000, 00000000, 04040404]
|
|
|
|
test_vslw_200_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_201_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707]
|
|
|
|
test_vslw_202_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [0E0E0E0E, 0E0E0E0E, 0E0E0E0E, 0E0E0E0E]
|
|
|
|
test_vslw_203_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [80000000, 07070707, 07070707, 07070707]
|
|
|
|
test_vslw_204_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [38383838, 83838380, 38383800, 83838000]
|
|
|
|
test_vslw_205_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [E0E0E000, E0E0E000, E0E0E000, E0E0E000]
|
|
|
|
test_vslw_206_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [38380000, 83800000, 38000000, 80000000]
|
|
|
|
test_vslw_207_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [07070707, 07070707, 80000000, 80000000]
|
|
|
|
test_vslw_208_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [70707070, 70707070, 70707070, 70707070]
|
|
|
|
test_vslw_209_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [07070700, 07070700, 07070700, 07070700]
|
|
|
|
test_vslw_210_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [1C1C0000, 1C1C0000, 1C1C0000, 1C1C0000]
|
|
|
|
test_vslw_211_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [07000000, 0E0E0E0E, 70707070, 07070700]
|
|
|
|
test_vslw_212_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [07070707, 07070707, E0E0E000, 38380000]
|
|
|
|
test_vslw_213_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707]
|
|
|
|
test_vslw_214_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [38383838, 83838380, 38383800, 83838000]
|
|
|
|
test_vslw_215_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [07070000, 07070707, 80000000, 80000000]
|
|
|
|
test_vslw_216_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [07070707, 07070707, E0E0E000, 38380000]
|
|
|
|
test_vslw_217_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707]
|
|
|
|
test_vslw_218_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [E0E0E000, E0E0E000, E0E0E000, 38383838]
|
|
|
|
test_vslw_219_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [38000000, 80000000, 38383838, 83838380]
|
|
|
|
test_vslw_220_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [C0000000, C0000000, C0000000, C0000000]
|
|
|
|
test_vslw_221_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [E0000000, 80000000, 0E0E0E0E, 38383838]
|
|
|
|
test_vslw_222_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [C0000000, 0E0E0E0E, E0000000, 1C1C1C1C]
|
|
|
|
test_vslw_223_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [0E0E0E0E, 80000000, 80000000, 07070707]
|
|
|
|
test_vslw_224_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [07070707, 80000000, 80000000, 07070707]
|
|
|
|
test_vslw_225_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 80000000]
|
|
|
|
test_vslw_226_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808]
|
|
|
|
test_vslw_227_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [10101010, 10101010, 10101010, 10101010]
|
|
|
|
test_vslw_228_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [00000000, 08080808, 08080808, 08080808]
|
|
|
|
test_vslw_229_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [40404040, 04040400, 40404000, 04040000]
|
|
|
|
test_vslw_230_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [01010000, 01010000, 01010000, 01010000]
|
|
|
|
test_vslw_231_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [40400000, 04000000, 40000000, 00000000]
|
|
|
|
test_vslw_232_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [08080808, 08080808, 00000000, 00000000]
|
|
|
|
test_vslw_233_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [80808080, 80808080, 80808080, 80808080]
|
|
|
|
test_vslw_234_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [04040400, 04040400, 04040400, 04040400]
|
|
|
|
test_vslw_235_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [20200000, 20200000, 20200000, 20200000]
|
|
|
|
test_vslw_236_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [08000000, 10101010, 80808080, 08080800]
|
|
|
|
test_vslw_237_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [08080808, 08080808, 01010000, 40400000]
|
|
|
|
test_vslw_238_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808]
|
|
|
|
test_vslw_239_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [40404040, 04040400, 40404000, 04040000]
|
|
|
|
test_vslw_240_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [08080000, 08080808, 00000000, 00000000]
|
|
|
|
test_vslw_241_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [08080808, 08080808, 01010000, 40400000]
|
|
|
|
test_vslw_242_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808]
|
|
|
|
test_vslw_243_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [01010000, 01010000, 01010000, 40404040]
|
|
|
|
test_vslw_244_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [40000000, 00000000, 40404040, 04040400]
|
|
|
|
test_vslw_245_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_246_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 10101010, 40404040]
|
|
|
|
test_vslw_247_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, 10101010, 00000000, 20202020]
|
|
|
|
test_vslw_248_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [10101010, 00000000, 00000000, 08080808]
|
|
|
|
test_vslw_249_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [08080808, 00000000, 00000000, 08080808]
|
|
|
|
test_vslw_250_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_251_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212]
|
|
|
|
test_vslw_252_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [24242424, 24242424, 24242424, 24242424]
|
|
|
|
test_vslw_253_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [00000000, 12121212, 12121212, 12121212]
|
|
|
|
test_vslw_254_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [90909090, 09090900, 90909000, 09090000]
|
|
|
|
test_vslw_255_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [42424000, 42424000, 42424000, 42424000]
|
|
|
|
test_vslw_256_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [90900000, 09000000, 90000000, 00000000]
|
|
|
|
test_vslw_257_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [12121212, 12121212, 00000000, 00000000]
|
|
|
|
test_vslw_258_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [21212120, 21212120, 21212120, 21212120]
|
|
|
|
test_vslw_259_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [09090900, 09090900, 09090900, 09090900]
|
|
|
|
test_vslw_260_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [12121200, 12121200, 12121200, 12121200]
|
|
|
|
test_vslw_261_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [12000000, 24242424, 21212120, 12121200]
|
|
|
|
test_vslw_262_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [12121212, 12121212, 42424000, 90900000]
|
|
|
|
test_vslw_263_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212]
|
|
|
|
test_vslw_264_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [90909090, 09090900, 90909000, 09090000]
|
|
|
|
test_vslw_265_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [12120000, 12121212, 00000000, 00000000]
|
|
|
|
test_vslw_266_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [12121212, 12121212, 42424000, 90900000]
|
|
|
|
test_vslw_267_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212]
|
|
|
|
test_vslw_268_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [42424000, 42424000, 42424000, 90909090]
|
|
|
|
test_vslw_269_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [90000000, 00000000, 90909090, 09090900]
|
|
|
|
test_vslw_270_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 80000000]
|
|
|
|
test_vslw_271_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [40000000, 00000000, 24242424, 90909090]
|
|
|
|
test_vslw_272_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [80000000, 24242424, 40000000, 48484848]
|
|
|
|
test_vslw_273_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [24242424, 00000000, 00000000, 12121212]
|
|
|
|
test_vslw_274_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [12121212, 00000000, 00000000, 12121212]
|
|
|
|
test_vslw_275_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_276_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788]
|
|
|
|
test_vslw_277_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [2468ACF0, 0ECA8642, 22446688, AACCEF10]
|
|
|
|
test_vslw_278_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [00000000, 87654321, 11223344, 55667788]
|
|
|
|
test_vslw_279_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [91A2B3C0, B2A19080, 119A2000, 3BC40000]
|
|
|
|
test_vslw_280_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [8ACF0000, A8642000, 46688000, CEF10000]
|
|
|
|
test_vslw_281_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [B3C00000, 90800000, 20000000, 00000000]
|
|
|
|
test_vslw_282_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [12345678, 87654321, 00000000, 00000000]
|
|
|
|
test_vslw_283_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [23456780, 76543210, 12233440, 56677880]
|
|
|
|
test_vslw_284_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [1A2B3C00, B2A19080, 9119A200, B33BC400]
|
|
|
|
test_vslw_285_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [34567800, 65432100, 22334400, 66778800]
|
|
|
|
test_vslw_286_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [59E00000, 0C840000, CD100000, DE200000]
|
|
|
|
test_vslw_287_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [12345678, 87654321, 46688000, BC400000]
|
|
|
|
test_vslw_288_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788]
|
|
|
|
test_vslw_289_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [91A2B3C0, B2A19080, 119A2000, 3BC40000]
|
|
|
|
test_vslw_290_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [56780000, 87654321, 00000000, 00000000]
|
|
|
|
test_vslw_291_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [12345678, 87654321, 46688000, BC400000]
|
|
|
|
test_vslw_292_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788]
|
|
|
|
test_vslw_293_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [8ACF0000, A8642000, 46688000, AB33BC40]
|
|
|
|
test_vslw_294_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [C0000000, 80000000, 89119A20, B33BC400]
|
|
|
|
test_vslw_295_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000000, 40000000, 00000000, 00000000]
|
|
|
|
test_vslw_296_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 80000000, 22446688, AB33BC40]
|
|
|
|
test_vslw_297_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, 0ECA8642, 80000000, 5599DE20]
|
|
|
|
test_vslw_298_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [2468ACF0, 80000000, 00000000, 55667788]
|
|
|
|
test_vslw_299_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [12345678, 80000000, 00000000, 55667788]
|
|
|
|
test_vslw_300_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 80000000, 00000000, 00000000]
|
|
|
|
test_vslw_301_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
|
|
test_vslw_302_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [7F000000, 7F800000, 7F19999A, 7FE66666]
|
|
|
|
test_vslw_303_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [00000000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
|
|
test_vslw_304_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [FC000000, E0000000, 66666800, 99998000]
|
|
|
|
test_vslw_305_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 9999A000, 66666000]
|
|
|
|
test_vslw_306_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 68000000, 80000000]
|
|
|
|
test_vslw_307_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [3F800000, 3FC00000, 80000000, 80000000]
|
|
|
|
test_vslw_308_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [F8000000, FC000000, F8CCCCD0, FF333330]
|
|
|
|
test_vslw_309_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [C0000000, E0000000, C6666680, F9999980]
|
|
|
|
test_vslw_310_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [80000000, C0000000, 8CCCCD00, F3333300]
|
|
|
|
test_vslw_311_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 33340000, CCCC0000]
|
|
|
|
test_vslw_312_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [00000000, 7F800000, F8CCCCD0, F3333300]
|
|
|
|
test_vslw_313_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
|
|
test_vslw_314_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [FC000000, E0000000, 66666800, 99998000]
|
|
|
|
test_vslw_315_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 3FC00000, 80000000, 80000000]
|
|
|
|
test_vslw_316_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [3F800000, 3FC00000, 9999A000, 99980000]
|
|
|
|
test_vslw_317_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
|
|
test_vslw_318_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 9999A000, FF999998]
|
|
|
|
test_vslw_319_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, FC666668, F9999980]
|
|
|
|
test_vslw_320_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 40000000, C0000000]
|
|
|
|
test_vslw_321_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 7F19999A, FF999998]
|
|
|
|
test_vslw_322_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, 7F800000, A0000000, FFCCCCCC]
|
|
|
|
test_vslw_323_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [7F000000, 00000000, 80000000, 3FF33333]
|
|
|
|
test_vslw_324_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [3F800000, 00000000, 80000000, 3FF33333]
|
|
|
|
test_vslw_325_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 80000000, 80000000]
|
|
|
|
test_vslw_326_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000]
|
|
|
|
test_vslw_327_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [82400000, 82400000, 82E00000, 82E00000]
|
|
|
|
test_vslw_328_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [00000000, C1200000, 41700000, C1700000]
|
|
|
|
test_vslw_329_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [09000000, 90000000, 80000000, 00000000]
|
|
|
|
test_vslw_330_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_331_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_332_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [41200000, C1200000, 00000000, 00000000]
|
|
|
|
test_vslw_333_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [12000000, 12000000, 17000000, 17000000]
|
|
|
|
test_vslw_334_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [90000000, 90000000, B8000000, B8000000]
|
|
|
|
test_vslw_335_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [20000000, 20000000, 70000000, 70000000]
|
|
|
|
test_vslw_336_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_337_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [00000000, 82400000, 17000000, 70000000]
|
|
|
|
test_vslw_338_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [41200000, C1200000, 00000000, 00000000]
|
|
|
|
test_vslw_339_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [09000000, 90000000, 80000000, 00000000]
|
|
|
|
test_vslw_340_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, C1200000, 00000000, 00000000]
|
|
|
|
test_vslw_341_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [41200000, C1200000, 00000000, 00000000]
|
|
|
|
test_vslw_342_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000]
|
|
|
|
test_vslw_343_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 0B800000]
|
|
|
|
test_vslw_344_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 0B800000, B8000000]
|
|
|
|
test_vslw_345_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_346_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 82E00000, 0B800000]
|
|
|
|
test_vslw_347_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, 82400000, 00000000, 05C00000]
|
|
|
|
test_vslw_348_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [82400000, 00000000, 00000000, C1700000]
|
|
|
|
test_vslw_349_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [41200000, 00000000, 00000000, C1700000]
|
|
|
|
test_vslw_350_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_351_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
|
|
test_vslw_352_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [FF000406, 080A0C0E, FF001416, 181A1C1E]
|
|
|
|
test_vslw_353_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [80000000, 04050607, 7F800A0B, 0C0D0E0F]
|
|
|
|
test_vslw_354_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [FC001018, 02830380, 00505800, 87078000]
|
|
|
|
test_vslw_355_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [00406000, A0C0E000, 01416000, A1C1E000]
|
|
|
|
test_vslw_356_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [10180000, 03800000, 58000000, 80000000]
|
|
|
|
test_vslw_357_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [7F800203, 04050607, 80000000, 80000000]
|
|
|
|
test_vslw_358_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [F8002030, 40506070, F800A0B0, C0D0E0F0]
|
|
|
|
test_vslw_359_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [C0010180, 02830380, C0050580, 06870780]
|
|
|
|
test_vslw_360_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [80020300, 05060700, 800A0B00, 0D0E0F00]
|
|
|
|
test_vslw_361_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [080C0000, 181C0000, 282C0000, 383C0000]
|
|
|
|
test_vslw_362_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [03000000, 080A0C0E, F800A0B0, 0D0E0F00]
|
|
|
|
test_vslw_363_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [7F800203, 04050607, 01416000, 70780000]
|
|
|
|
test_vslw_364_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
|
|
test_vslw_365_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [02030000, 04050607, 80000000, 80000000]
|
|
|
|
test_vslw_366_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [7F800203, 04050607, 01416000, 70780000]
|
|
|
|
test_vslw_367_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
|
|
test_vslw_368_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00406000, A0C0E000, 01416000, 60687078]
|
|
|
|
test_vslw_369_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [18000000, 80000000, FC005058, 06870780]
|
|
|
|
test_vslw_370_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [C0000000, C0000000, C0000000, C0000000]
|
|
|
|
test_vslw_371_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [60000000, 80000000, FF001416, 60687078]
|
|
|
|
test_vslw_372_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [C0000000, 080A0C0E, 60000000, 3034383C]
|
|
|
|
test_vslw_373_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [FF000406, 80000000, 80000000, 0C0D0E0F]
|
|
|
|
test_vslw_374_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [7F800203, 80000000, 80000000, 0C0D0E0F]
|
|
|
|
test_vslw_375_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 80000000]
|
|
|
|
test_vslw_376_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
|
|
test_vslw_377_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [00102020, 011E0000, FFFFFFFE, 1FFFFFFE]
|
|
|
|
test_vslw_378_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [00000000, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
|
|
test_vslw_379_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00408080, 47800000, FFFFF800, FFFF8000]
|
|
|
|
test_vslw_380_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [02020000, E0000000, FFFFE000, FFFFE000]
|
|
|
|
test_vslw_381_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [80800000, 00000000, F8000000, 80000000]
|
|
|
|
test_vslw_382_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [80081010, 808F0000, 80000000, 80000000]
|
|
|
|
test_vslw_383_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [00810100, 08F00000, FFFFFFF0, FFFFFFF0]
|
|
|
|
test_vslw_384_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [04080800, 47800000, FFFFFF80, FFFFFF80]
|
|
|
|
test_vslw_385_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [08101000, 8F000000, FFFFFF00, FFFFFF00]
|
|
|
|
test_vslw_386_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [40400000, 00000000, FFFC0000, FFFC0000]
|
|
|
|
test_vslw_387_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [10000000, 011E0000, FFFFFFF0, FFFFFF00]
|
|
|
|
test_vslw_388_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [80081010, 808F0000, FFFFE000, FFF80000]
|
|
|
|
test_vslw_389_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
|
|
test_vslw_390_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00408080, 47800000, FFFFF800, FFFF8000]
|
|
|
|
test_vslw_391_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [80081010, 808F0000, FFFFE000, FFF80000]
|
|
|
|
test_vslw_392_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
|
|
test_vslw_393_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [02020000, E0000000, FFFFE000, 7FFFFFF8]
|
|
|
|
test_vslw_394_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [80000000, 00000000, FFFFFFF8, FFFFFF80]
|
|
|
|
test_vslw_395_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, C0000000, C0000000]
|
|
|
|
test_vslw_396_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, FFFFFFFE, 7FFFFFF8]
|
|
|
|
test_vslw_397_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, 011E0000, E0000000, 3FFFFFFC]
|
|
|
|
test_vslw_398_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00102020, 00000000, 80000000, 8FFFFFFF]
|
|
|
|
test_vslw_399_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [80081010, 00000000, 80000000, 8FFFFFFF]
|
|
|
|
test_vslw_400_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 80000000, 80000000]
|
|
|
|
test_vslw_401_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
|
|
test_vslw_402_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [7F000000, 7F800000, 7F19999A, 7FE66666]
|
|
|
|
test_vslw_403_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [00000000, BFC00000, BF8CCCCD, BFF33333]
|
|
|
|
test_vslw_404_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [FC000000, E0000000, 66666800, 99998000]
|
|
|
|
test_vslw_405_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 9999A000, 66666000]
|
|
|
|
test_vslw_406_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 68000000, 80000000]
|
|
|
|
test_vslw_407_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [BF800000, BFC00000, 80000000, 80000000]
|
|
|
|
test_vslw_408_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [F8000000, FC000000, F8CCCCD0, FF333330]
|
|
|
|
test_vslw_409_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [C0000000, E0000000, C6666680, F9999980]
|
|
|
|
test_vslw_410_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [80000000, C0000000, 8CCCCD00, F3333300]
|
|
|
|
test_vslw_411_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 33340000, CCCC0000]
|
|
|
|
test_vslw_412_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [00000000, 7F800000, F8CCCCD0, F3333300]
|
|
|
|
test_vslw_413_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [BF800000, BFC00000, 9999A000, 99980000]
|
|
|
|
test_vslw_414_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
|
|
test_vslw_415_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [FC000000, E0000000, 66666800, 99998000]
|
|
|
|
test_vslw_416_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, BFC00000, 80000000, 80000000]
|
|
|
|
test_vslw_417_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
|
|
test_vslw_418_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 9999A000, FF999998]
|
|
|
|
test_vslw_419_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, FC666668, F9999980]
|
|
|
|
test_vslw_420_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 40000000, C0000000]
|
|
|
|
test_vslw_421_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 7F19999A, FF999998]
|
|
|
|
test_vslw_422_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, 7F800000, A0000000, FFCCCCCC]
|
|
|
|
test_vslw_423_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [7F000000, 00000000, 80000000, BFF33333]
|
|
|
|
test_vslw_424_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [BF800000, 00000000, 80000000, BFF33333]
|
|
|
|
test_vslw_425_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 80000000, 80000000]
|
|
|
|
test_vslw_426_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
|
|
test_vslw_427_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [82400000, 83400000, 83400000, 83E00000]
|
|
|
|
test_vslw_428_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [00000000, 41A00000, C1A00000, 41F00000]
|
|
|
|
test_vslw_429_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [09000000, D0000000, 00000000, 00000000]
|
|
|
|
test_vslw_430_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_431_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_432_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [C1200000, 41A00000, 00000000, 00000000]
|
|
|
|
test_vslw_433_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [12000000, 1A000000, 1A000000, 1F000000]
|
|
|
|
test_vslw_434_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [90000000, D0000000, D0000000, F8000000]
|
|
|
|
test_vslw_435_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [20000000, A0000000, A0000000, F0000000]
|
|
|
|
test_vslw_436_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_437_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [00000000, 83400000, 1A000000, F0000000]
|
|
|
|
test_vslw_438_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [C1200000, 41A00000, 00000000, 00000000]
|
|
|
|
test_vslw_439_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
|
|
test_vslw_440_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [09000000, D0000000, 00000000, 00000000]
|
|
|
|
test_vslw_441_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 41A00000, 00000000, 00000000]
|
|
|
|
test_vslw_442_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [C1200000, 41A00000, 00000000, 00000000]
|
|
|
|
test_vslw_443_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 0F800000]
|
|
|
|
test_vslw_444_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 0D000000, F8000000]
|
|
|
|
test_vslw_445_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_446_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 83400000, 0F800000]
|
|
|
|
test_vslw_447_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, 83400000, 00000000, 07C00000]
|
|
|
|
test_vslw_448_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [82400000, 00000000, 00000000, 41F00000]
|
|
|
|
test_vslw_449_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [C1200000, 00000000, 00000000, 41F00000]
|
|
|
|
test_vslw_450_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_451_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
|
|
test_vslw_452_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [9B9B9B9A, 9B9B9B9A, 9B9B9B9A, 08020406]
|
|
|
|
test_vslw_453_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [80000000, CDCDCDCD, CDCDCDCD, 04010203]
|
|
|
|
test_vslw_454_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [6E6E6E68, E6E6E680, 6E6E6800, 81018000]
|
|
|
|
test_vslw_455_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [B9B9A000, B9B9A000, B9B9A000, 20406000]
|
|
|
|
test_vslw_456_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [6E680000, E6800000, 68000000, 80000000]
|
|
|
|
test_vslw_457_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, 80000000, 80000000]
|
|
|
|
test_vslw_458_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [DCDCDCD0, DCDCDCD0, DCDCDCD0, 40102030]
|
|
|
|
test_vslw_459_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [E6E6E680, E6E6E680, E6E6E680, 00810180]
|
|
|
|
test_vslw_460_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [CDCDCD00, CDCDCD00, CDCDCD00, 01020300]
|
|
|
|
test_vslw_461_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [37340000, 37340000, 37340000, 080C0000]
|
|
|
|
test_vslw_462_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [CD000000, 9B9B9B9A, DCDCDCD0, 01020300]
|
|
|
|
test_vslw_463_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, B9B9A000, 10180000]
|
|
|
|
test_vslw_464_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
|
|
test_vslw_465_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [6E6E6E68, E6E6E680, 6E6E6800, 81018000]
|
|
|
|
test_vslw_466_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [CDCD0000, CDCDCDCD, 80000000, 80000000]
|
|
|
|
test_vslw_467_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, B9B9A000, 10180000]
|
|
|
|
test_vslw_468_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
|
|
test_vslw_469_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [68000000, 80000000, 6E6E6E68, 00810180]
|
|
|
|
test_vslw_470_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [40000000, 40000000, 40000000, C0000000]
|
|
|
|
test_vslw_471_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [A0000000, 80000000, 9B9B9B9A, 20081018]
|
|
|
|
test_vslw_472_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [40000000, 9B9B9B9A, A0000000, 1004080C]
|
|
|
|
test_vslw_473_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [9B9B9B9A, 80000000, 80000000, 04010203]
|
|
|
|
test_vslw_474_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [CDCDCDCD, 80000000, 80000000, 04010203]
|
|
|
|
test_vslw_475_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 80000000]
|
|
|
|
test_vslw_476_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
|
|
test_vslw_477_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [F1F3F5F6, F9FBFDFE, 00020406, 080A0C0E]
|
|
|
|
test_vslw_478_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [80000000, FCFDFEFF, 00010203, 04050607]
|
|
|
|
test_vslw_479_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [C7CFD7D8, 7EFF7F80, 08101800, 83038000]
|
|
|
|
test_vslw_480_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [3F5F6000, BFDFE000, 20406000, A0C0E000]
|
|
|
|
test_vslw_481_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [D7D80000, 7F800000, 18000000, 80000000]
|
|
|
|
test_vslw_482_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 80000000, 80000000]
|
|
|
|
test_vslw_483_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [8F9FAFB0, CFDFEFF0, 00102030, 40506070]
|
|
|
|
test_vslw_484_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [7CFD7D80, 7EFF7F80, 00810180, 02830380]
|
|
|
|
test_vslw_485_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [F9FAFB00, FDFEFF00, 01020300, 05060700]
|
|
|
|
test_vslw_486_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [EBEC0000, FBFC0000, 080C0000, 181C0000]
|
|
|
|
test_vslw_487_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [FB000000, F9FBFDFE, 00102030, 05060700]
|
|
|
|
test_vslw_488_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 20406000, 30380000]
|
|
|
|
test_vslw_489_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
|
|
test_vslw_490_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [C7CFD7D8, 7EFF7F80, 08101800, 83038000]
|
|
|
|
test_vslw_491_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [FAFB0000, FCFDFEFF, 80000000, 80000000]
|
|
|
|
test_vslw_492_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 20406000, 30380000]
|
|
|
|
test_vslw_493_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
|
|
test_vslw_494_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [3F5F6000, BFDFE000, 20406000, 20283038]
|
|
|
|
test_vslw_495_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [C0000000, C0000000, C0000000, C0000000]
|
|
|
|
test_vslw_496_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [60000000, 80000000, 00020406, 20283038]
|
|
|
|
test_vslw_497_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [C0000000, F9FBFDFE, 60000000, 1014181C]
|
|
|
|
test_vslw_498_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [F1F3F5F6, 80000000, 80000000, 04050607]
|
|
|
|
test_vslw_499_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [F8F9FAFB, 80000000, 80000000, 04050607]
|
|
|
|
test_vslw_500_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 80000000]
|
|
|
|
test_vslw_501_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
|
|
test_vslw_502_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [FDFDFDFC, FDFDFDFC, FDFDFDFC, FDFDFDFC]
|
|
|
|
test_vslw_503_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [00000000, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
|
|
test_vslw_504_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [F7F7F7F0, 7F7F7F00, F7F7F000, 7F7F0000]
|
|
|
|
test_vslw_505_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [DFDFC000, DFDFC000, DFDFC000, DFDFC000]
|
|
|
|
test_vslw_506_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [F7F00000, 7F000000, F0000000, 00000000]
|
|
|
|
test_vslw_507_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, 00000000, 00000000]
|
|
|
|
test_vslw_508_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [EFEFEFE0, EFEFEFE0, EFEFEFE0, EFEFEFE0]
|
|
|
|
test_vslw_509_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [7F7F7F00, 7F7F7F00, 7F7F7F00, 7F7F7F00]
|
|
|
|
test_vslw_510_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [FEFEFE00, FEFEFE00, FEFEFE00, FEFEFE00]
|
|
|
|
test_vslw_511_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [FBF80000, FBF80000, FBF80000, FBF80000]
|
|
|
|
test_vslw_512_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [FE000000, FDFDFDFC, EFEFEFE0, FEFEFE00]
|
|
|
|
test_vslw_513_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, DFDFC000, F7F00000]
|
|
|
|
test_vslw_514_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
|
|
test_vslw_515_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [F7F7F7F0, 7F7F7F00, F7F7F000, 7F7F0000]
|
|
|
|
test_vslw_516_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [FEFE0000, FEFEFEFE, 00000000, 00000000]
|
|
|
|
test_vslw_517_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, DFDFC000, F7F00000]
|
|
|
|
test_vslw_518_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
|
|
test_vslw_519_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [DFDFC000, DFDFC000, DFDFC000, F7F7F7F0]
|
|
|
|
test_vslw_520_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [F0000000, 00000000, F7F7F7F0, 7F7F7F00]
|
|
|
|
test_vslw_521_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [C0000000, 00000000, FDFDFDFC, F7F7F7F0]
|
|
|
|
test_vslw_522_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [80000000, FDFDFDFC, C0000000, FBFBFBF8]
|
|
|
|
test_vslw_523_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [FDFDFDFC, 00000000, 00000000, FEFEFEFE]
|
|
|
|
test_vslw_524_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [FEFEFEFE, 00000000, 00000000, FEFEFEFE]
|
|
|
|
test_vslw_525_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vslw_526_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
|
|
test_vslw_527_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [FFF9FFFA, FFFDFFFE, 00000002, 00040006]
|
|
|
|
test_vslw_528_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [80000000, FFFEFFFF, 00000001, 00020003]
|
|
|
|
test_vslw_529_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [FFE7FFE8, FF7FFF80, 00000800, 00018000]
|
|
|
|
test_vslw_530_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [9FFFA000, DFFFE000, 00002000, 40006000]
|
|
|
|
test_vslw_531_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [FFE80000, FF800000, 08000000, 80000000]
|
|
|
|
test_vslw_532_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 80000000, 80000000]
|
|
|
|
test_vslw_533_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [FFCFFFD0, FFEFFFF0, 00000010, 00200030]
|
|
|
|
test_vslw_534_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [FE7FFE80, FF7FFF80, 00000080, 01000180]
|
|
|
|
test_vslw_535_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [FCFFFD00, FEFFFF00, 00000100, 02000300]
|
|
|
|
test_vslw_536_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [FFF40000, FFFC0000, 00040000, 000C0000]
|
|
|
|
test_vslw_537_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [FD000000, FFFDFFFE, 00000010, 02000300]
|
|
|
|
test_vslw_538_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00002000, 00180000]
|
|
|
|
test_vslw_539_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
|
|
test_vslw_540_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [FFE7FFE8, FF7FFF80, 00000800, 00018000]
|
|
|
|
test_vslw_541_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [FFFD0000, FFFEFFFF, 80000000, 80000000]
|
|
|
|
test_vslw_542_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00002000, 00180000]
|
|
|
|
test_vslw_543_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
|
|
test_vslw_544_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [9FFFA000, DFFFE000, 00002000, 00100018]
|
|
|
|
test_vslw_545_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [E8000000, 80000000, 00000008, 01000180]
|
|
|
|
test_vslw_546_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [40000000, C0000000, 40000000, C0000000]
|
|
|
|
test_vslw_547_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [40000000, FFFDFFFE, 20000000, 0008000C]
|
|
|
|
test_vslw_548_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [FFF9FFFA, 80000000, 80000000, 00020003]
|
|
|
|
test_vslw_549_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [FFFCFFFD, 80000000, 80000000, 00020003]
|
|
|
|
test_vslw_550_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 80000000]
|
|
|
|
test_vslw_551_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
|
|
test_vslw_552_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [FFFBFEFC, 00040102, FFF9FEFA, 00060104]
|
|
|
|
test_vslw_553_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [00000000, 00020081, FFFCFF7D, 00030082]
|
|
|
|
test_vslw_554_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [FFEFFBF0, 01004080, E7FBE800, 80410000]
|
|
|
|
test_vslw_555_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [BFEFC000, 40102000, 9FEFA000, 60104000]
|
|
|
|
test_vslw_556_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [FBF00000, 40800000, E8000000, 00000000]
|
|
|
|
test_vslw_557_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [FFFDFF7E, 00020081, 80000000, 00000000]
|
|
|
|
test_vslw_558_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [FFDFF7E0, 00200810, FFCFF7D0, 00300820]
|
|
|
|
test_vslw_559_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [FEFFBF00, 01004080, FE7FBE80, 01804100]
|
|
|
|
test_vslw_560_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [FDFF7E00, 02008100, FCFF7D00, 03008200]
|
|
|
|
test_vslw_561_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [FDF80000, 02040000, FDF40000, 02080000]
|
|
|
|
test_vslw_562_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [7E000000, 00040102, FFCFF7D0, 03008200]
|
|
|
|
test_vslw_563_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [FFFDFF7E, 00020081, 9FEFA000, 04100000]
|
|
|
|
test_vslw_564_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
|
|
test_vslw_565_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [FFEFFBF0, 01004080, E7FBE800, 80410000]
|
|
|
|
test_vslw_566_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [FF7E0000, 00020081, 80000000, 00000000]
|
|
|
|
test_vslw_567_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [FFFDFF7E, 00020081, 9FEFA000, 04100000]
|
|
|
|
test_vslw_568_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
|
|
test_vslw_569_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [BFEFC000, 40102000, 9FEFA000, 00180410]
|
|
|
|
test_vslw_570_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [F0000000, 80000000, FFE7FBE8, 01804100]
|
|
|
|
test_vslw_571_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [80000000, 40000000, 40000000, 80000000]
|
|
|
|
test_vslw_572_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [C0000000, 80000000, FFF9FEFA, 00180410]
|
|
|
|
test_vslw_573_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [FFFBFEFC, 80000000, 80000000, 00030082]
|
|
|
|
test_vslw_574_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [FFFDFF7E, 80000000, 80000000, 00030082]
|
|
|
|
test_vslw_575_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 80000000, 80000000, 00000000]
|
|
|
|
test_vslw_576_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
|
|
test_vslw_577_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [FFFE0202, E0E1FFFE, FFFFFFFE, 00000000]
|
|
|
|
test_vslw_578_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [80000000, 7070FFFF, FFFFFFFF, 00000000]
|
|
|
|
test_vslw_579_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [FFF80808, 387FFF80, FFFFF800, 00000000]
|
|
|
|
test_vslw_580_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [E0202000, 1FFFE000, FFFFE000, 00000000]
|
|
|
|
test_vslw_581_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [08080000, FF800000, F8000000, 00000000]
|
|
|
|
test_vslw_582_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, 80000000, 00000000]
|
|
|
|
test_vslw_583_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [FFF01010, 070FFFF0, FFFFFFF0, 00000000]
|
|
|
|
test_vslw_584_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [FF808080, 387FFF80, FFFFFF80, 00000000]
|
|
|
|
test_vslw_585_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [FF010100, 70FFFF00, FFFFFF00, 00000000]
|
|
|
|
test_vslw_586_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [04040000, FFFC0000, FFFC0000, 00000000]
|
|
|
|
test_vslw_587_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [01000000, E0E1FFFE, FFFFFFF0, 00000000]
|
|
|
|
test_vslw_588_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFE000, 00000000]
|
|
|
|
test_vslw_589_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
|
|
test_vslw_590_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [FFF80808, 387FFF80, FFFFF800, 00000000]
|
|
|
|
test_vslw_591_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [01010000, 7070FFFF, 80000000, 00000000]
|
|
|
|
test_vslw_592_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFE000, 00000000]
|
|
|
|
test_vslw_593_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
|
|
test_vslw_594_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [E0202000, 1FFFE000, FFFFE000, 00000000]
|
|
|
|
test_vslw_595_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [08000000, 80000000, FFFFFFF8, 00000000]
|
|
|
|
test_vslw_596_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [40000000, C0000000, C0000000, 00000000]
|
|
|
|
test_vslw_597_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [20000000, 80000000, FFFFFFFE, 00000000]
|
|
|
|
test_vslw_598_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [40000000, E0E1FFFE, E0000000, 00000000]
|
|
|
|
test_vslw_599_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [FFFF0101, 80000000, 80000000, 00000000]
|
|
|
|
test_vslw_600_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 00000000]
|
|
|
|
test_vslw_601_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
|
|
test_vslw_602_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [FFFFFF00, 000000FE, FFFDFEFE, 00020100]
|
|
|
|
test_vslw_603_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [00000000, 0000007F, FFFEFF7F, 00010080]
|
|
|
|
test_vslw_604_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [FFFFFC00, 00003F80, F7FBF800, 80400000]
|
|
|
|
test_vslw_605_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [FFF00000, 000FE000, DFEFE000, 20100000]
|
|
|
|
test_vslw_606_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [FC000000, 3F800000, F8000000, 00000000]
|
|
|
|
test_vslw_607_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [FFFFFF80, 0000007F, 80000000, 00000000]
|
|
|
|
test_vslw_608_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [FFFFF800, 000007F0, FFEFF7F0, 00100800]
|
|
|
|
test_vslw_609_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [FFFFC000, 00003F80, FF7FBF80, 00804000]
|
|
|
|
test_vslw_610_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [FFFF8000, 00007F00, FEFF7F00, 01008000]
|
|
|
|
test_vslw_611_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [FE000000, 01FC0000, FDFC0000, 02000000]
|
|
|
|
test_vslw_612_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [80000000, 000000FE, FFEFF7F0, 01008000]
|
|
|
|
test_vslw_613_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [FFFFFF80, 0000007F, DFEFE000, 04000000]
|
|
|
|
test_vslw_614_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
|
|
test_vslw_615_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [FFFFFC00, 00003F80, F7FBF800, 80400000]
|
|
|
|
test_vslw_616_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [FF800000, 0000007F, 80000000, 00000000]
|
|
|
|
test_vslw_617_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [FFFFFF80, 0000007F, DFEFE000, 04000000]
|
|
|
|
test_vslw_618_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
|
|
test_vslw_619_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [FFF00000, 000FE000, DFEFE000, 00080400]
|
|
|
|
test_vslw_620_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [00000000, 80000000, FFF7FBF8, 00804000]
|
|
|
|
test_vslw_621_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000000, C0000000, C0000000, 00000000]
|
|
|
|
test_vslw_622_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 80000000, FFFDFEFE, 00080400]
|
|
|
|
test_vslw_623_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, 000000FE, E0000000, 00040200]
|
|
|
|
test_vslw_624_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [FFFFFF00, 80000000, 80000000, 00010080]
|
|
|
|
test_vslw_625_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 80000000, 80000000, 00000000]
|
|
|
|
test_vslw_626_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
|
|
test_vslw_627_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [FFFFFFFE, FFFFFFFE, FFFFFFFE, FFFFFFFE]
|
|
|
|
test_vslw_628_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [80000000, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
|
|
test_vslw_629_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [FFFFFFF8, FFFFFF80, FFFFF800, FFFF8000]
|
|
|
|
test_vslw_630_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [FFFFE000, FFFFE000, FFFFE000, FFFFE000]
|
|
|
|
test_vslw_631_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [FFF80000, FF800000, F8000000, 80000000]
|
|
|
|
test_vslw_632_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, 80000000, 80000000]
|
|
|
|
test_vslw_633_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [FFFFFFF0, FFFFFFF0, FFFFFFF0, FFFFFFF0]
|
|
|
|
test_vslw_634_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [FFFFFF80, FFFFFF80, FFFFFF80, FFFFFF80]
|
|
|
|
test_vslw_635_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [FFFFFF00, FFFFFF00, FFFFFF00, FFFFFF00]
|
|
|
|
test_vslw_636_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [FFFC0000, FFFC0000, FFFC0000, FFFC0000]
|
|
|
|
test_vslw_637_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [FF000000, FFFFFFFE, FFFFFFF0, FFFFFF00]
|
|
|
|
test_vslw_638_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFE000, FFF80000]
|
|
|
|
test_vslw_639_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
|
|
test_vslw_640_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [FFFFFFF8, FFFFFF80, FFFFF800, FFFF8000]
|
|
|
|
test_vslw_641_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [FFFF0000, FFFFFFFF, 80000000, 80000000]
|
|
|
|
test_vslw_642_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFE000, FFF80000]
|
|
|
|
test_vslw_643_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
|
|
test_vslw_644_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [FFFFE000, FFFFE000, FFFFE000, FFFFFFF8]
|
|
|
|
test_vslw_645_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [F8000000, 80000000, FFFFFFF8, FFFFFF80]
|
|
|
|
test_vslw_646_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [C0000000, C0000000, C0000000, C0000000]
|
|
|
|
test_vslw_647_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [E0000000, 80000000, FFFFFFFE, FFFFFFF8]
|
|
|
|
test_vslw_648_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [C0000000, FFFFFFFE, E0000000, FFFFFFFC]
|
|
|
|
test_vslw_649_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [FFFFFFFE, 80000000, 80000000, FFFFFFFF]
|
|
|
|
test_vslw_650_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vslw v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [FFFFFFFF, 80000000, 80000000, FFFFFFFF]
|
|
|