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Xenia-Canary/src/xenia/cpu/ppc/testing/instr__gen_vsr.s
Dr. Chat 54582cc823 Generated tests from Rick
2019-04-04 18:13:11 -05:00

5851 lines
222 KiB
ArmAsm
Raw Blame History

test_vsr_1_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsr_2_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsr_3_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsr_4_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsr_5_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsr_6_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsr_7_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsr_8_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsr_9_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsr_10_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsr_11_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsr_12_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsr_13_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsr_14_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsr_15_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsr_16_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsr_17_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsr_18_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsr_19_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsr_20_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsr_21_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsr_22_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsr_23_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsr_24_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsr_25_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsr_26_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
test_vsr_27_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [00000000, 02000001, 00000001, 02000001]
test_vsr_28_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [00000000, 10000000, 00000000, 10000000]
test_vsr_29_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsr_30_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [00000000, 10000000, 00000000, 10000000]
test_vsr_31_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [00000001, 00000001, 02000000, 02000000]
test_vsr_32_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [00000000, 10000000, 10000000, 10000000]
test_vsr_33_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [00000000, 02000000, 02000000, 02000000]
test_vsr_34_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
test_vsr_35_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [00000000, 40000000, 40000000, 40000000]
test_vsr_36_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [00000001, 02000000, 80000000, 08000001]
test_vsr_37_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [00000001, 02000001, 02000000, 02000000]
test_vsr_38_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [00000001, 80000001, 80000001, 80000001]
test_vsr_39_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [00000000, 10000000, 02000000, 10000000]
test_vsr_40_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [00000001, 00000001, 02000000, 02000000]
test_vsr_41_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [00000001, 02000001, 02000000, 02000000]
test_vsr_42_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [00000001, 80000001, 80000001, 80000001]
test_vsr_43_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [00000000, 08000000, 08000000, 10000000]
test_vsr_44_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [00000000, 10000000, 00000000, 10000000]
test_vsr_45_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [00000000, 04000000, 04000000, 04000000]
test_vsr_46_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [00000000, 02000000, 00000000, 00000000]
test_vsr_47_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [00000000, 00000000, 02000000, 00000000]
test_vsr_48_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [00000000, 00000000, 02000000, 00000001]
test_vsr_49_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [00000001, 00000000, 02000000, 00000001]
test_vsr_50_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [00000000, 02000000, 02000000, 02000000]
test_vsr_51_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000]
test_vsr_52_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000]
test_vsr_53_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [00003FFF, FFFFFC00, 00000000, 0FFFFC00]
test_vsr_54_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000]
test_vsr_55_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [00003FFF, FFFFFC00, 00000000, 0FFFFC00]
test_vsr_56_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [000001FF, FFFFFE00, 00000000, 01FF0000]
test_vsr_57_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [00000FFF, FFFFF000, 00000000, 0FFFF000]
test_vsr_58_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [000001FF, FFFFFE00, 00000000, 01FFFE00]
test_vsr_59_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000]
test_vsr_60_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [00003FFF, FFFFC000, 00000000, 3FFFC000]
test_vsr_61_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [000003FF, FFFFE000, 00000000, 07FFFE00]
test_vsr_62_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, 01FFE000]
test_vsr_63_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, 7FFF0000]
test_vsr_64_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [00003FFF, FFFFFC00, 00000000, 0FFFFC00]
test_vsr_65_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, 01FFFE00]
test_vsr_66_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, 01FFE000]
test_vsr_67_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, 7FFF0000]
test_vsr_68_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [000007FF, FFFFF800, 00000000, 0FFFC000]
test_vsr_69_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [00003FFF, FFFFFC00, 00000000, 0FFFFC00]
test_vsr_70_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [000003FF, FFFFFC00, 00000000, 03FFFC00]
test_vsr_71_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [000001FF, FFFFFE00, 00000000, FFFF0000]
test_vsr_72_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [000001FF, FFFF0000, 00000000, FFFF0000]
test_vsr_73_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [00007FFF, FFFFFE00, 00000000, FFFF0000]
test_vsr_74_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [000001FF, FFFF0000, 00000000, FFFF0000]
test_vsr_75_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [000001FF, FFFFFE00, 00000000, 01FFFE00]
test_vsr_76_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_vsr_77_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [00010201, 04050603, 08090A05, 0C0D0E07]
test_vsr_78_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [00010204, 06080607, 08090A0B, 16180E0F]
test_vsr_79_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [00000210, 04200630, 08400A50, 0C600E70]
test_vsr_80_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [00004040, 3020140C, 08044241, B060341C]
test_vsr_81_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [00000203, 04050A07, 0E090A14, 16180E1C]
test_vsr_82_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [00001020, 30405060, 708090A0, B0C0D0E0]
test_vsr_83_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [00000204, 06080A0C, 0E101214, 16181A1C]
test_vsr_84_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_vsr_85_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [00004080, C1014181, C2024282, C3034383]
test_vsr_86_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [00000403, 0620A003, 840221A0, 58301A0F]
test_vsr_87_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [00010203, 06050607, 0E809050, 1681A1C1]
test_vsr_88_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [00010203, 82050607, 84090A0B, 860D0E0F]
test_vsr_89_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [00014040, 3020140C, 0E094241, B060341C]
test_vsr_90_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [00010203, 04080607, 0E101214, 16181A1C]
test_vsr_91_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [00010203, 06050607, 0E809050, 1681A1C1]
test_vsr_92_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [00010203, 82050607, 84090A0B, 860D0E0F]
test_vsr_93_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [00000810, 18202830, 38404850, B00643C1]
test_vsr_94_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [00004040, 3020140C, 08044241, B060341C]
test_vsr_95_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [00000408, 0C101418, 1C202428, 2C303438]
test_vsr_96_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [00000210, 06100A0C, 08090A05, 0C030EC1]
test_vsr_97_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [00000208, 04010603, 0E801250, 0C810E83]
test_vsr_98_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [00008101, 04050A0C, 0E101214, 0C0D0E0F]
test_vsr_99_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [00000203, 0405060C, 0E201214, 0C060E0F]
test_vsr_100_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [00000204, 06080A0C, 0E101214, 16181A1C]
test_vsr_101_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D]
test_vsr_102_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [000D0006, 000D0006, 000D0006, 000D0006]
test_vsr_103_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [000D1A00, 1A00000D, 000D000D, 1A00000D]
test_vsr_104_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [00064001, D0003400, 00064001, D0003400]
test_vsr_105_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [00064001, D0003400, 00064001, D0003400]
test_vsr_106_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [00001A0D, 000D1A0D, 1A0D0000, 1A000000]
test_vsr_107_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [0000D000, D000D000, D000D000, D000D000]
test_vsr_108_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [00001A00, 1A001A00, 1A001A00, 1A001A00]
test_vsr_109_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D]
test_vsr_110_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [00034003, 40034003, 40034003, 40034003]
test_vsr_111_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [0000340D, 1A00A006, 8003A000, 68001A0D]
test_vsr_112_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [000D000D, 1A0D000D, 1A00D000, 1A01A001]
test_vsr_113_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [000D000D, 800D000D, 800D000D, 800D000D]
test_vsr_114_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [000D4001, D0003400, 1A0D4001, D0003400]
test_vsr_115_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [000D000D, 0000000D, 1A001A00, 1A001A00]
test_vsr_116_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [000D000D, 1A0D000D, 1A00D000, 1A01A001]
test_vsr_117_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [000D000D, 800D000D, 800D000D, 800D000D]
test_vsr_118_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [00006800, 68006800, 68006800, D0064001]
test_vsr_119_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [00064001, D0003400, 00064001, D0003400]
test_vsr_120_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [00003400, 34003400, 34003400, 34003400]
test_vsr_121_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [00001A00, 1A001A00, 000D0006, 00030001]
test_vsr_122_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [00001A00, 00030006, 1A001A00, 00010003]
test_vsr_123_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [00008006, 000D1A00, 1A001A00, 000D000D]
test_vsr_124_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [00001A0D, 000D0000, 1A001A00, 0006000D]
test_vsr_125_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [00001A00, 1A001A00, 1A001A00, 1A001A00]
test_vsr_126_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
test_vsr_127_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [00112219, 4455663B, 8899AA5D, CCDDEE7F]
test_vsr_128_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [00112244, 66886677, 8899AABB, 7799EEFF]
test_vsr_129_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [00084846, 342255CC, 884C6A57, BC6677DD]
test_vsr_130_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [00002211, 44226633, 8844AA55, CC66EE77]
test_vsr_131_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [00002233, 4455AA77, EF99AA55, 7799EEDD]
test_vsr_132_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [00011223, 34455667, 78899AAB, BCCDDEEF]
test_vsr_133_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [00002244, 6688AACC, EF113355, 7799BBDD]
test_vsr_134_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
test_vsr_135_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [0004488C, D115599D, E2266AAE, F3377BBF]
test_vsr_136_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [00014433, 6622AC3B, C42635AB, DE33BBFF]
test_vsr_137_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [00112233, 66556677, EF899A55, 779BBDDF]
test_vsr_138_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [00112233, A2556677, C499AABB, E6DDEEFF]
test_vsr_139_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [00114846, 342255CC, EF996A57, BC6677DD]
test_vsr_140_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [00112233, 44886677, EF113355, 7799BBDD]
test_vsr_141_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [00112233, 66556677, EF899A55, 779BBDDF]
test_vsr_142_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [00112233, A2556677, C499AABB, E6DDEEFF]
test_vsr_143_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [00008911, 9A22AB33, BC44CD55, BC6E7BDF]
test_vsr_144_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [00084846, 342255CC, 884C6A57, BC6677DD]
test_vsr_145_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [00004488, CD115599, DE2266AA, EF3377BB]
test_vsr_146_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [00012211, 6611AACC, 8899AA5D, CC37EEDF]
test_vsr_147_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [00002288, 4415663B, EF893355, CC9BEEBF]
test_vsr_148_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [00009119, 4455AACC, EF113355, CCDDEEFF]
test_vsr_149_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [00002233, 445566CC, EF223355, CC6EEEFF]
test_vsr_150_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [00002244, 6688AACC, EF113355, 7799BBDD]
test_vsr_151_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
test_vsr_152_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [00FFFF80, 0000FF80, FF00007F, FFFF007F]
test_vsr_153_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [00FFFFFE, 0000FF00, FF0000FF, FFFF00FF]
test_vsr_154_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [007FFFE0, 000003FE, FF80001F, FFFFFC01]
test_vsr_155_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [0007FFF8, 0000FFF8, FFF80007, FFFF0007]
test_vsr_156_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [007FFFE0, 000003FE, FF80001F, FFFFFC01]
test_vsr_157_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [000FFFF0, 00000FF0, 0FF0000F, FFFFF00F]
test_vsr_158_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [0001FFFE, 000001FE, 01FE0001, FFFFFE01]
test_vsr_159_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
test_vsr_160_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [003FFFC0, 00003FC0, 3FC0003F, FFFFC03F]
test_vsr_161_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [000FFF00, 00001F80, 7FC0000F, FFFFFEFF]
test_vsr_162_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [00FFFF00, 0000FF00, 01F00007, FFFFE01F]
test_vsr_163_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [00FFFF00, 0000FF00, 7F0000FF, FFFF00FF]
test_vsr_164_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [00FFFFE0, 000003FE, 0100001F, FFFFFC01]
test_vsr_165_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [00FFFF00, 0000FF00, 01FE0001, FFFFFE01]
test_vsr_166_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [00FFFF00, 0000FF00, 01F00007, FFFFE01F]
test_vsr_167_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [00FFFF00, 0000FF00, 7F0000FF, FFFF00FF]
test_vsr_168_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [0007FFF8, 000007F8, 07F80007, FFFFC01F]
test_vsr_169_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [007FFFE0, 000003FE, FF80001F, FFFFFC01]
test_vsr_170_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [0003FFFC, 000003FC, 03FC0003, FFFFFC03]
test_vsr_171_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [000FFFF8, 000001FE, FF00007F, FFFF001F]
test_vsr_172_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [0007FFFC, 0000FF80, 01F00007, FFFF003F]
test_vsr_173_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [0001FF80, 000001FE, 01FE0001, FFFF00FF]
test_vsr_174_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [0001FF00, 0000FFFE, 01FC0001, FFFF00FF]
test_vsr_175_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [0001FFFE, 000001FE, 01FE0001, FFFFFE01]
test_vsr_176_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404]
test_vsr_177_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [04040402, 04040402, 04040402, 04040402]
test_vsr_178_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [04040808, 08080404, 04040404, 08080404]
test_vsr_179_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [04020180, 40201008, 04020180, 40201008]
test_vsr_180_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [04200420, 04200420, 04200420, 04200420]
test_vsr_181_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [04020180, 40201008, 04020180, 40201008]
test_vsr_182_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [04080804, 04040804, 08040408, 08080408]
test_vsr_183_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [00080808, 08080808, 08080808, 08080808]
test_vsr_184_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404]
test_vsr_185_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101]
test_vsr_186_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [01401004, 08208002, 02018040, 20100804]
test_vsr_187_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [00040404, 08040404, 08404020, 08808080]
test_vsr_188_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [02040404, 02040404, 02040404, 02040404]
test_vsr_189_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [00040180, 40201008, 08040180, 40201008]
test_vsr_190_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [04040404, 04080404, 08080808, 08080808]
test_vsr_191_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [00040404, 08040404, 08404020, 08808080]
test_vsr_192_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [02040404, 02040404, 02040404, 02040404]
test_vsr_193_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [00202020, 20202020, 20202020, 40020180]
test_vsr_194_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [04020180, 40201008, 04020180, 40201008]
test_vsr_195_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [00101010, 10101010, 10101010, 10101010]
test_vsr_196_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [00400820, 08100808, 04040402, 04010480]
test_vsr_197_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [00200810, 04010402, 08400820, 04800401]
test_vsr_198_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [00080202, 04040808, 08080808, 04040404]
test_vsr_199_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [00080804, 04040408, 08100808, 04020404]
test_vsr_200_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [00080808, 08080808, 08080808, 08080808]
test_vsr_201_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707]
test_vsr_202_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [07070783, 07070783, 07070783, 07070783]
test_vsr_203_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [07070E0E, 0E0E0707, 07070707, 0E0E0707]
test_vsr_204_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [0783C1E0, 70381C0E, 0783C1E0, 70381C0E]
test_vsr_205_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [07380738, 07380738, 07380738, 07380738]
test_vsr_206_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [0783C1E0, 70381C0E, 0783C1E0, 70381C0E]
test_vsr_207_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [070E0E07, 07070E07, 0E07070E, 0E0E070E]
test_vsr_208_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [00707070, 70707070, 70707070, 70707070]
test_vsr_209_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707]
test_vsr_210_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [01C1C1C1, C1C1C1C1, C1C1C1C1, C1C1C1C1]
test_vsr_211_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [01701C07, 0E38E083, 83C1E070, 381C0E07]
test_vsr_212_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [00070707, 0E070707, 0E707038, 0EE0E0E0]
test_vsr_213_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [03070707, 83070707, 83070707, 83070707]
test_vsr_214_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [0007C1E0, 70381C0E, 0E07C1E0, 70381C0E]
test_vsr_215_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [07070707, 070E0707, 0E0E0E0E, 0E0E0E0E]
test_vsr_216_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [00070707, 0E070707, 0E707038, 0EE0E0E0]
test_vsr_217_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [03070707, 83070707, 83070707, 83070707]
test_vsr_218_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [00383838, 38383838, 38383838, 7083C1E0]
test_vsr_219_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [0783C1E0, 70381C0E, 0783C1E0, 70381C0E]
test_vsr_220_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [001C1C1C, 1C1C1C1C, 1C1C1C1C, 1C1C1C1C]
test_vsr_221_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [00700E38, 0E1C0E0E, 07070783, 07C107E0]
test_vsr_222_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [00380E1C, 07C10783, 0E700E38, 07E007C1]
test_vsr_223_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [000E8383, 07070E0E, 0E0E0E0E, 07070707]
test_vsr_224_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [000E0E07, 0707070E, 0E1C0E0E, 07830707]
test_vsr_225_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [000E0E0E, 0E0E0E0E, 0E0E0E0E, 0E0E0E0E]
test_vsr_226_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808]
test_vsr_227_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [08080804, 08080804, 08080804, 08080804]
test_vsr_228_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [08081010, 10100808, 08080808, 10100808]
test_vsr_229_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [08040201, 80402010, 08040201, 80402010]
test_vsr_230_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [08400840, 08400840, 08400840, 08400840]
test_vsr_231_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [08040201, 80402010, 08040201, 80402010]
test_vsr_232_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [08101008, 08081008, 10080810, 10100810]
test_vsr_233_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [00808080, 80808080, 80808080, 80808080]
test_vsr_234_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [00101010, 10101010, 10101010, 10101010]
test_vsr_235_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [02020202, 02020202, 02020202, 02020202]
test_vsr_236_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [02802008, 10400104, 04020180, 40201008]
test_vsr_237_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [00080808, 10080808, 10808040, 10010101]
test_vsr_238_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [04080808, 04080808, 04080808, 04080808]
test_vsr_239_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [00080201, 80402010, 10080201, 80402010]
test_vsr_240_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [08080808, 08100808, 10101010, 10101010]
test_vsr_241_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [00080808, 10080808, 10808040, 10010101]
test_vsr_242_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [04080808, 04080808, 04080808, 04080808]
test_vsr_243_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [00404040, 40404040, 40404040, 80040201]
test_vsr_244_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [08040201, 80402010, 08040201, 80402010]
test_vsr_245_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [00202020, 20202020, 20202020, 20202020]
test_vsr_246_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [00801040, 10201010, 08080804, 08020801]
test_vsr_247_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [00401020, 08020804, 10801040, 08010802]
test_vsr_248_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [00100404, 08081010, 10101010, 08080808]
test_vsr_249_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [00101008, 08080810, 10201010, 08040808]
test_vsr_250_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [00101010, 10101010, 10101010, 10101010]
test_vsr_251_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212]
test_vsr_252_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [12121209, 12121209, 12121209, 12121209]
test_vsr_253_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [12122424, 24241212, 12121212, 24241212]
test_vsr_254_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [12098442, 21904824, 12098442, 21904824]
test_vsr_255_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [12901290, 12901290, 12901290, 12901290]
test_vsr_256_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [12098442, 21904824, 12098442, 21904824]
test_vsr_257_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [12242412, 12122412, 24121224, 24241224]
test_vsr_258_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [01212121, 21212121, 21212121, 21212121]
test_vsr_259_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [00242424, 24242424, 24242424, 24242424]
test_vsr_260_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212]
test_vsr_261_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [04214812, 24904209, 09844221, 90482412]
test_vsr_262_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [00121212, 24121212, 24212190, 24424242]
test_vsr_263_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [09121212, 09121212, 09121212, 09121212]
test_vsr_264_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [00128442, 21904824, 24128442, 21904824]
test_vsr_265_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [12121212, 12241212, 24242424, 24242424]
test_vsr_266_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [00121212, 24121212, 24212190, 24424242]
test_vsr_267_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [09121212, 09121212, 09121212, 09121212]
test_vsr_268_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [00909090, 90909090, 90909090, 21098442]
test_vsr_269_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [12098442, 21904824, 12098442, 21904824]
test_vsr_270_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [00484848, 48484848, 48484848, 48484848]
test_vsr_271_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [00212490, 24482424, 12121209, 12841242]
test_vsr_272_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [00902448, 12841209, 24212490, 12421284]
test_vsr_273_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [00240909, 12122424, 24242424, 12121212]
test_vsr_274_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [00242412, 12121224, 24482424, 12091212]
test_vsr_275_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [00242424, 24242424, 24242424, 24242424]
test_vsr_276_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788]
test_vsr_277_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [1234563C, 87654390, 112233A2, 556677C4]
test_vsr_278_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [123468AC, F10E4321, 11223344, 88AA7788]
test_vsr_279_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [121A15CF, 883B9586, 11918C68, 45AB99EF]
test_vsr_280_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [129156B3, 873B4319, 1189339A, 55AB77BC]
test_vsr_281_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [121A15CF, 883B9586, 11918C68, 45AB99EF]
test_vsr_282_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [12246878, 8765CA21, 42223366, 88AA77EF]
test_vsr_283_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [01234567, 88765432, 11122334, 45566778]
test_vsr_284_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [002468AC, F10ECA86, 42224466, 88AACCEF]
test_vsr_285_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788]
test_vsr_286_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [048D159E, 21D950C8, 44488CD1, 15599DE2]
test_vsr_287_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [00345678, F1654321, 4212239A, 88ACCEF1]
test_vsr_288_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [09345678, 43654321, 88223344, 2A667788]
test_vsr_289_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [003415CF, 883B9586, 42228C68, 45AB99EF]
test_vsr_290_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [12345678, 870E4321, 42224466, 88AACCEF]
test_vsr_291_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [00345678, F1654321, 4212239A, 88ACCEF1]
test_vsr_292_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [09345678, 43654321, 88223344, 2A667788]
test_vsr_293_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [0091A2B3, C43B2A19, 0889119A, 45B39DF1]
test_vsr_294_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [121A15CF, 883B9586, 11918C68, 45AB99EF]
test_vsr_295_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [0048D159, E21D950C, 844488CD, 115599DE]
test_vsr_296_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [002368B3, F11DCA86, 112233A2, 555977F1]
test_vsr_297_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [00916859, 87D94390, 4212449A, 55AC77E2]
test_vsr_298_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [00242B3C, 8765CA86, 42224466, 55667788]
test_vsr_299_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [00246878, 87654386, 42444466, 55B37788]
test_vsr_300_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [002468AC, F10ECA86, 42224466, 88AACCEF]
test_vsr_301_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
test_vsr_302_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCC66, 3FF33399]
test_vsr_303_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [3F800000, 007F0000, 3F8CCCCD, 9A7F3333]
test_vsr_304_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [3FC00000, 03FE0000, 3FC63399, D3FFCC66]
test_vsr_305_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [3FFC0000, 3FFE0000, 3FFCCC66, 3FFF3399]
test_vsr_306_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [3FC00000, 03FE0000, 3FC63399, D3FFCC66]
test_vsr_307_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [3F7F0000, 3FC08000, 008CCC99, 9A7F3366]
test_vsr_308_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [03F80000, 03FC0000, 03F8CCCC, D3FF3333]
test_vsr_309_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [007F0000, 007F8000, 007F1999, 9A7FE666]
test_vsr_310_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
test_vsr_311_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [0FE00000, 0FF00000, 0FE33333, 4FFCCCCC]
test_vsr_312_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [0FF80000, 00FE0000, 1FE399CC, 69FFE633]
test_vsr_313_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [1F800000, 1FC00000, 1F8CCCCD, 9FF33333]
test_vsr_314_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [00800000, 03FE0000, 008C3399, D3FFCC66]
test_vsr_315_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [3F800000, 3F7F0000, 007F1999, 9A7FE666]
test_vsr_316_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [00800000, 00C00000, 00F8CC66, 9AFE6666]
test_vsr_317_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [1F800000, 1FC00000, 1F8CCCCD, 9FF33333]
test_vsr_318_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [01FC0000, 01FE0000, 01FC6666, D3F9CC66]
test_vsr_319_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [3FC00000, 03FE0000, 3FC63399, D3FFCC66]
test_vsr_320_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [00FE0000, 00FF0000, 00FE3333, 34FFCCCC]
test_vsr_321_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [00F80000, 00FF8000, 3F8CCC66, 3FFC3366]
test_vsr_322_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [00FC0000, 3FF00000, 00F81966, 3FFE33CC]
test_vsr_323_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [007F0000, 3FC08000, 007F1999, 3FF33333]
test_vsr_324_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [007F0000, 3FC00000, 00FE1999, 3FF93333]
test_vsr_325_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [007F0000, 007F8000, 007F1999, 9A7FE666]
test_vsr_326_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000]
test_vsr_327_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000]
test_vsr_328_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [41204000, 01820000, 41700000, 01820000]
test_vsr_329_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [41900000, 0C098000, 41B80000, 0C0BC000]
test_vsr_330_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [41090000, C1090000, 410B0000, C10B0000]
test_vsr_331_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [41900000, 0C098000, 41B80000, 0C0BC000]
test_vsr_332_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [41824000, C1204000, 00700000, 01820000]
test_vsr_333_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [04120000, 0C120000, 04170000, 0C170000]
test_vsr_334_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [00824000, 01824000, 0082E000, 0182E000]
test_vsr_335_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000]
test_vsr_336_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [10480000, 30480000, 105C0000, 305C0000]
test_vsr_337_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [10128000, 01090000, 205C0000, 0605E000]
test_vsr_338_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [00200000, 01200000, 00170000, 012E0000]
test_vsr_339_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [00200000, 0C098000, 00700000, 0C0BC000]
test_vsr_340_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [41200000, C1820000, 0082E000, 0182E000]
test_vsr_341_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [00200000, 01200000, 00170000, 012E0000]
test_vsr_342_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [20200000, 60200000, 20700000, 60700000]
test_vsr_343_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [02090000, 06090000, 020B8000, 0CB80000]
test_vsr_344_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [41900000, 0C098000, 41B80000, 0C0BC000]
test_vsr_345_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [01048000, 03048000, 0105C000, 0305C000]
test_vsr_346_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [00124000, 01044000, 41700000, C15C0000]
test_vsr_347_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [00094000, C1480000, 0017E000, C12E0000]
test_vsr_348_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [00820000, C1204000, 0082E000, C1700000]
test_vsr_349_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [00824000, C1200000, 0005E000, C1B80000]
test_vsr_350_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [00824000, 01824000, 0082E000, 0182E000]
test_vsr_351_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
test_vsr_352_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [7F800201, 04050603, 7F800A05, 0C0D0E07]
test_vsr_353_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [7F800004, 06080607, 7F800A0B, 16180E0F]
test_vsr_354_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [7FC00040, 3020140C, 7FC00241, B060341C]
test_vsr_355_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [7FFC0210, 04200630, 7FFC0A50, 0C600E70]
test_vsr_356_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [7FC00040, 3020140C, 7FC00241, B060341C]
test_vsr_357_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [7FFF0003, 04050A07, 0E800A14, 16180E1C]
test_vsr_358_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [07F80020, 30405060, 77F800A0, B0C0D0E0]
test_vsr_359_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [00FF0004, 06080A0C, 0EFF0014, 16181A1C]
test_vsr_360_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
test_vsr_361_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [1FE00080, C1014181, DFE00282, C3034383]
test_vsr_362_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [1FF80003, 0620A003, BFE001A0, 58301A0F]
test_vsr_363_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [00800203, 06050607, 0EF80050, 1681A1C1]
test_vsr_364_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [3F800203, 82050607, BF800A0B, 860D0E0F]
test_vsr_365_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [7F800203, 04080607, 0EFF0014, 16181A1C]
test_vsr_366_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [00800203, 06050607, 0EF80050, 1681A1C1]
test_vsr_367_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [3F800203, 82050607, BF800A0B, 860D0E0F]
test_vsr_368_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [03FC0010, 18202830, 3BFC0050, B00643C1]
test_vsr_369_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [7FC00040, 3020140C, 7FC00241, B060341C]
test_vsr_370_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [01FE0008, 0C101418, 1DFE0028, 2C303438]
test_vsr_371_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [00F80010, 06100A0C, 7F800A05, 0C030EC1]
test_vsr_372_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [00FC0008, 04010603, 0EF80050, 0C810E83]
test_vsr_373_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [00FF0101, 04050A0C, 0EFF0014, 0C0D0E0F]
test_vsr_374_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [00FF0003, 0405060C, 0EFE0014, 0C060E0F]
test_vsr_375_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [00FF0004, 06080A0C, 0EFF0014, 16181A1C]
test_vsr_376_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
test_vsr_377_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [80081008, 808F0000, 7FFFFFFF, 8FFFFFFF]
test_vsr_378_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [80081020, 21010000, 7FFFFFFF, FF1FFFFF]
test_vsr_379_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [80040402, 08043C00, 7FFFFFFF, F87FFFFF]
test_vsr_380_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [80001080, 80040000, 7FFFFFFF, 8F7FFFFF]
test_vsr_381_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [80040402, 08043C00, 7FFFFFFF, F87FFFFF]
test_vsr_382_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [80001010, 808F1E00, 00FFFFFF, FF1FFFFF]
test_vsr_383_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [08008101, 0808F000, 07FFFFFF, F8FFFFFF]
test_vsr_384_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [01001020, 21011E00, 00FFFFFF, FF1FFFFF]
test_vsr_385_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
test_vsr_386_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [20020404, 2023C000, 1FFFFFFF, E3FFFFFF]
test_vsr_387_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [20002010, 2104E000, 3FFFFFFF, FC3FFFFF]
test_vsr_388_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [01081010, 218F0000, 00FFFFFF, FFFFFFFF]
test_vsr_389_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [40081010, 408F0000, 3FFFFFFF, C7FFFFFF]
test_vsr_390_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [01080402, 08043C00, 00FFFFFF, F87FFFFF]
test_vsr_391_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [01081010, 218F0000, 00FFFFFF, FFFFFFFF]
test_vsr_392_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [40081010, 408F0000, 3FFFFFFF, C7FFFFFF]
test_vsr_393_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [04004080, 84047800, 03FFFFFF, F8FFFFFF]
test_vsr_394_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [80040402, 08043C00, 7FFFFFFF, F87FFFFF]
test_vsr_395_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [02002040, 42023C00, 01FFFFFF, FE3FFFFF]
test_vsr_396_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [01001080, 21021E00, 7FFFFFFF, 8FFFFFFF]
test_vsr_397_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [01001040, 80230000, 00FFFFFF, 8FFFFFFF]
test_vsr_398_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [01000808, 808F1E00, 00FFFFFF, 8FFFFFFF]
test_vsr_399_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [01001010, 808F0000, 00FFFFFF, 8FFFFFFF]
test_vsr_400_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [01001020, 21011E00, 00FFFFFF, FF1FFFFF]
test_vsr_401_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333]
test_vsr_402_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCC66, BFF33399]
test_vsr_403_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [BF800000, 017F0000, BF8CCCCD, 9B7F3333]
test_vsr_404_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [BFC00000, 0BFE0000, BFC63399, DBFFCC66]
test_vsr_405_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [BFFC0000, BFFE0000, BFFCCC66, BFFF3399]
test_vsr_406_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [BFC00000, 0BFE0000, BFC63399, DBFFCC66]
test_vsr_407_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [BF7F0000, BFC08000, 018CCC99, 9B7F3366]
test_vsr_408_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [0BF80000, 0BFC0000, 0BF8CCCC, DBFF3333]
test_vsr_409_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [017F0000, 017F8000, 017F1999, 9B7FE666]
test_vsr_410_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333]
test_vsr_411_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [2FE00000, 2FF00000, 2FE33333, 6FFCCCCC]
test_vsr_412_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [2FF80000, 01FE0000, 5FE399CC, 6DFFE633]
test_vsr_413_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [01800000, 01C00000, 01F8CC66, 9BFE6666]
test_vsr_414_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [5F800000, 5FC00000, 5F8CCCCD, DFF33333]
test_vsr_415_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [01800000, 0BFE0000, 018C3399, DBFFCC66]
test_vsr_416_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [BF800000, BF7F0000, 017F1999, 9B7FE666]
test_vsr_417_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [5F800000, 5FC00000, 5F8CCCCD, DFF33333]
test_vsr_418_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [05FC0000, 05FE0000, 05FC6666, DBF9CC66]
test_vsr_419_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [BFC00000, 0BFE0000, BFC63399, DBFFCC66]
test_vsr_420_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [02FE0000, 02FF0000, 02FE3333, 36FFCCCC]
test_vsr_421_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [01F80000, 01FF8000, BF8CCC66, BFFC3366]
test_vsr_422_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [01FC0000, BFF00000, 01F81966, BFFE33CC]
test_vsr_423_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [017F0000, BFC08000, 017F1999, BFF33333]
test_vsr_424_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [017F0000, BFC00000, 01FE1999, BFF93333]
test_vsr_425_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [017F0000, 017F8000, 017F1999, 9B7FE666]
test_vsr_426_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000]
test_vsr_427_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000]
test_vsr_428_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [C1204000, 00830000, C1A00000, 00830000]
test_vsr_429_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [C1900000, 040D8000, C1D00000, 040FC000]
test_vsr_430_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [C1090000, 410D0000, C10D0000, 410F0000]
test_vsr_431_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [C1900000, 040D8000, C1D00000, 040FC000]
test_vsr_432_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [C1824000, 41A04000, 01A00000, 00830000]
test_vsr_433_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [0C120000, 041A0000, 0C1A0000, 041F0000]
test_vsr_434_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [01824000, 00834000, 01834000, 0083E000]
test_vsr_435_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000]
test_vsr_436_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [30480000, 10680000, 30680000, 107C0000]
test_vsr_437_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [30128000, 000D0000, 60680000, 0207E000]
test_vsr_438_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [01200000, 00A00000, 011A0000, 003E0000]
test_vsr_439_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [60200000, 20A00000, 60A00000, 20F00000]
test_vsr_440_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [01200000, 040D8000, 01A00000, 040FC000]
test_vsr_441_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [C1200000, 41830000, 01834000, 0083E000]
test_vsr_442_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [01200000, 00A00000, 011A0000, 003E0000]
test_vsr_443_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [06090000, 020D0000, 060D0000, 04F80000]
test_vsr_444_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [C1900000, 040D8000, C1D00000, 040FC000]
test_vsr_445_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [03048000, 01068000, 03068000, 0107C000]
test_vsr_446_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [01124000, 00064000, C1A00000, 417C0000]
test_vsr_447_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [01094000, 41680000, 011A4000, 413E0000]
test_vsr_448_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [01820000, 41A04000, 01834000, 41F00000]
test_vsr_449_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [01824000, 41A00000, 01064000, 41F80000]
test_vsr_450_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [01824000, 00834000, 01834000, 0083E000]
test_vsr_451_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
test_vsr_452_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [CDCDCDE6, CDCDCDE6, CDCDCDE6, 04010201]
test_vsr_453_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [CDCD9B9B, 9B9BCDCD, CDCDCDCD, 9A080203]
test_vsr_454_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [CDE673B9, DC6E379B, CDE673B9, D0200404]
test_vsr_455_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [CD6ECD6E, CD6ECD6E, CD6ECD6E, 04200210]
test_vsr_456_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [CDE673B9, DC6E379B, CDE673B9, D0200404]
test_vsr_457_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [CD9B9BCD, CDCD9BCD, 9BCDCD9B, 9A080204]
test_vsr_458_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [0CDCDCDC, DCDCDCDC, DCDCDCDC, D0401020]
test_vsr_459_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [019B9B9B, 9B9B9B9B, 9B9B9B9B, 9A080204]
test_vsr_460_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
test_vsr_461_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [33737373, 73737373, 73737373, 41004080]
test_vsr_462_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [33DC37CD, 9B6EB9E6, E673B9DC, 68100203]
test_vsr_463_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [01CDCDCD, 9BCDCDCD, 9BDCDC6E, 9A802040]
test_vsr_464_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [66CDCDCD, E6CDCDCD, E6CDCDCD, 82010203]
test_vsr_465_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [01CD73B9, DC6E379B, 9BCD73B9, D0200404]
test_vsr_466_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [CDCDCDCD, CD9BCDCD, 9B9B9B9B, 9A080204]
test_vsr_467_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [01CDCDCD, 9BCDCDCD, 9BDCDC6E, 9A802040]
test_vsr_468_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [66CDCDCD, E6CDCDCD, E6CDCDCD, 82010203]
test_vsr_469_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [CDE673B9, DC6E379B, CDE673B9, D0200404]
test_vsr_470_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [03373737, 37373737, 37373737, 34100408]
test_vsr_471_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [01DC9B6E, 9B379B9B, CDCDCDE6, 04000240]
test_vsr_472_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [016E9B37, CD73CDE6, 9BDC9B6E, 04800280]
test_vsr_473_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [019BE6E6, CDCD9B9B, 9B9B9B9B, 04010203]
test_vsr_474_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [019B9BCD, CDCDCD9B, 9B379B9B, 04000203]
test_vsr_475_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [019B9B9B, 9B9B9B9B, 9B9B9B9B, 9A080204]
test_vsr_476_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
test_vsr_477_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [F8F9FA7D, FCFDFE7F, 00010201, 04050603]
test_vsr_478_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [F8F9F3F5, F7F9FEFF, 00010203, 06080607]
test_vsr_479_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [F87C7E5F, BFE7F7FD, 00004040, 3020140C]
test_vsr_480_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [F8C7FAD7, FCE7FEF7, 00000210, 04200630]
test_vsr_481_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [F87C7E5F, BFE7F7FD, 00004040, 3020140C]
test_vsr_482_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [F8F1F3FB, FCFDFBFF, FE010204, 0608060C]
test_vsr_483_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [0F8F9FAF, BFCFDFEF, F0001020, 30405060]
test_vsr_484_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [01F1F3F5, F7F9FBFD, FE000204, 06080A0C]
test_vsr_485_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
test_vsr_486_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [3E3E7EBE, FF3F7FBF, C0004080, C1014181]
test_vsr_487_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [3E8FE7FB, F7E7BF7F, 80002020, 18100A07]
test_vsr_488_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [01F9FAFB, F7FDFEFF, FE001010, 0680A0C0]
test_vsr_489_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [7CF9FAFB, FEFDFEFF, 80010203, 82050607]
test_vsr_490_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [01F97E5F, BFE7F7FD, FE014040, 3020140C]
test_vsr_491_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [F8F9FAFB, FCF9FEFF, FE000204, 06080A0C]
test_vsr_492_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [01F9FAFB, F7FDFEFF, FE001010, 0680A0C0]
test_vsr_493_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [7CF9FAFB, FEFDFEFF, 80010203, 82050607]
test_vsr_494_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [07C7CFD7, DFE7EFF7, F8000810, 300241C0]
test_vsr_495_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [03E3E7EB, EFF3F7FB, FC000408, 0C101418]
test_vsr_496_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [018FF3D7, F7F3FBFD, 00010201, 040106C0]
test_vsr_497_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [01C7F3EB, FC3FFE7F, FE000210, 04800681]
test_vsr_498_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [01F1FD7D, FCFDFBFD, FE000204, 04050607]
test_vsr_499_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [01F1F3FB, FCFDFEFD, FE000204, 04020607]
test_vsr_500_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [01F1F3F5, F7F9FBFD, FE000204, 06080A0C]
test_vsr_501_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
test_vsr_502_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [FEFEFE7F, FEFEFE7F, FEFEFE7F, FEFEFE7F]
test_vsr_503_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [FEFEFDFD, FDFDFEFE, FEFEFEFE, FDFDFEFE]
test_vsr_504_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FE7FBFDF, EFF7FBFD, FE7FBFDF, EFF7FBFD]
test_vsr_505_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [FEF7FEF7, FEF7FEF7, FEF7FEF7, FEF7FEF7]
test_vsr_506_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [FE7FBFDF, EFF7FBFD, FE7FBFDF, EFF7FBFD]
test_vsr_507_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [FEFDFDFE, FEFEFDFE, FDFEFEFD, FDFDFEFD]
test_vsr_508_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [0FEFEFEF, EFEFEFEF, EFEFEFEF, EFEFEFEF]
test_vsr_509_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [01FDFDFD, FDFDFDFD, FDFDFDFD, FDFDFDFD]
test_vsr_510_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
test_vsr_511_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [3FBFBFBF, BFBFBFBF, BFBFBFBF, BFBFBFBF]
test_vsr_512_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [3FEFFBFE, FDF7DF7F, 7FBFDFEF, F7FBFDFE]
test_vsr_513_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [01FEFEFE, FDFEFEFE, FDEFEFF7, FDDFDFDF]
test_vsr_514_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [7FFEFEFE, 7FFEFEFE, 7FFEFEFE, 7FFEFEFE]
test_vsr_515_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [01FEBFDF, EFF7FBFD, FDFEBFDF, EFF7FBFD]
test_vsr_516_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [FEFEFEFE, FEFDFEFE, FDFDFDFD, FDFDFDFD]
test_vsr_517_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [01FEFEFE, FDFEFEFE, FDEFEFF7, FDDFDFDF]
test_vsr_518_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [7FFEFEFE, 7FFEFEFE, 7FFEFEFE, 7FFEFEFE]
test_vsr_519_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [07F7F7F7, F7F7F7F7, F7F7F7F7, EF7FBFDF]
test_vsr_520_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [FE7FBFDF, EFF7FBFD, FE7FBFDF, EFF7FBFD]
test_vsr_521_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [01EFFDF7, FDFBFDFD, FEFEFE7F, FEBFFEDF]
test_vsr_522_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [01F7FDFB, FEBFFE7F, FDEFFDF7, FEDFFEBF]
test_vsr_523_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [01FD7F7F, FEFEFDFD, FDFDFDFD, FEFEFEFE]
test_vsr_524_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [01FDFDFE, FEFEFEFD, FDFBFDFD, FE7FFEFE]
test_vsr_525_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [01FDFDFD, FDFDFDFD, FDFDFDFD, FDFDFDFD]
test_vsr_526_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
test_vsr_527_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [FFFCFFFE, FFFEFFFF, 00000000, 00020001]
test_vsr_528_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [FFFCF9FF, FBFFFFFF, 00000001, 02000003]
test_vsr_529_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFFE3FFF, DFFFFBFF, 00000000, 10000800]
test_vsr_530_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, 00000000, 00000000]
test_vsr_531_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [FFFE3FFF, DFFFFBFF, 00000000, 10000800]
test_vsr_532_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [FFFFF9FD, FFFEFDFF, FE000000, 02000000]
test_vsr_533_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [0FFFCFFF, DFFFEFFF, F0000000, 10002000]
test_vsr_534_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [01FFF9FF, FBFFFDFF, FE000000, 02000400]
test_vsr_535_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
test_vsr_536_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [3FFF3FFF, 7FFFBFFF, C0000000, 40008000]
test_vsr_537_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [3FFFF3FD, FBFFDFFF, 80000000, 08000403]
test_vsr_538_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [01FCFFFD, FBFEFFFF, FE000000, 02004000]
test_vsr_539_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [7FFCFFFD, FFFEFFFF, 80000001, 80020003]
test_vsr_540_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [01FC3FFF, DFFFFBFF, FE000000, 10000800]
test_vsr_541_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [FFFCFFFD, FFFFFFFF, FE000000, 02000400]
test_vsr_542_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [01FCFFFD, FBFEFFFF, FE000000, 02004000]
test_vsr_543_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [7FFCFFFD, FFFEFFFF, 80000001, 80020003]
test_vsr_544_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [07FFE7FF, EFFFF7FF, F8000000, 10018000]
test_vsr_545_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [FFFE3FFF, DFFFFBFF, 00000000, 10000800]
test_vsr_546_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [03FFF3FF, F7FFFBFF, FC000000, 04000800]
test_vsr_547_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [01FFF9FF, FFFFFFFF, FE000000, 00000000]
test_vsr_548_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [01FF7FFE, FFFEFDFF, FE000000, 00020003]
test_vsr_549_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [01FFF9FD, FFFEFFFF, FE000000, 00010003]
test_vsr_550_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [01FFF9FF, FBFFFDFF, FE000000, 02000400]
test_vsr_551_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
test_vsr_552_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [FFFDFFBF, 00020040, FFFCFFBE, 00030041]
test_vsr_553_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [FFFDFBFE, FC000081, FFFCFF7D, FA000082]
test_vsr_554_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFFE7FEF, E0000801, FFFE3FEF, D0000C01]
test_vsr_555_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [FFFFFFFB, 00000004, FFFFFFFB, 00000004]
test_vsr_556_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [FFFE7FEF, E0000801, FFFE3FEF, D0000C01]
test_vsr_557_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [FFFFFB7E, 00020481, 03FCFFFE, FA000001]
test_vsr_558_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [0FFFDFF7, E0002008, 1FFFCFF7, D0003008]
test_vsr_559_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [01FFFBFE, FC000401, 03FFF9FE, FA000601]
test_vsr_560_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
test_vsr_561_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [3FFF7FDF, 80008020, 7FFF3FDF, 4000C020]
test_vsr_562_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [3FFFF77E, FC004040, FFFF9FF7, E8000682]
test_vsr_563_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [01FDFF7E, FC020081, 03FFCFFB, FA006010]
test_vsr_564_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [7FFDFF7E, 00020081, FFFCFF7D, 80030082]
test_vsr_565_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [01FD7FEF, E0000801, 03FC3FEF, D0000C01]
test_vsr_566_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [FFFDFF7E, 00000081, 03FFF9FE, FA000601]
test_vsr_567_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [01FDFF7E, FC020081, 03FFCFFB, FA006010]
test_vsr_568_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [7FFDFF7E, 00020081, FFFCFF7D, 80030082]
test_vsr_569_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [07FFEFFB, F0001004, 0FFFE7FB, D001C010]
test_vsr_570_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [FFFE7FEF, E0000801, FFFE3FEF, D0000C01]
test_vsr_571_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [03FFF7FD, F8000802, 07FFF3FD, F4000C02]
test_vsr_572_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [01FFFBFB, FC000401, FFFCFFBE, 00000010]
test_vsr_573_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [01FFFFBF, 00020401, 03FFF9FE, 00030082]
test_vsr_574_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [01FFFB7E, 00020001, 03FFF9FE, 00010082]
test_vsr_575_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [01FFFBFE, FC000401, 03FFF9FE, FA000601]
test_vsr_576_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
test_vsr_577_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [FFFF0180, 7070FFFF, FFFFFFFF, 00000000]
test_vsr_578_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [FFFFFE02, 02E0FFFF, FFFFFFFF, FE000000]
test_vsr_579_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFFFC020, 1783C3FF, FFFFFFFF, F0000000]
test_vsr_580_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [FFFF0108, 7083FFFF, FFFFFFFF, 00000000]
test_vsr_581_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [FFFFC020, 1783C3FF, FFFFFFFF, F0000000]
test_vsr_582_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [FFFFFE01, 7070E1FF, FFFFFFFF, FE000000]
test_vsr_583_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [0FFFF010, 17070FFF, FFFFFFFF, F0000000]
test_vsr_584_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [01FFFE02, 02E0E1FF, FFFFFFFF, FE000000]
test_vsr_585_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
test_vsr_586_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [3FFFC040, 5C1C3FFF, FFFFFFFF, C0000000]
test_vsr_587_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [3FFFFC01, 02831FFF, FFFFFFFF, F8000000]
test_vsr_588_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [01FF0101, 0270FFFF, FFFFFFFF, FE000000]
test_vsr_589_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [7FFF0101, B870FFFF, FFFFFFFF, 80000000]
test_vsr_590_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [01FFC020, 1783C3FF, FFFFFFFF, F0000000]
test_vsr_591_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [FFFF0101, 70E0FFFF, FFFFFFFF, FE000000]
test_vsr_592_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [01FF0101, 0270FFFF, FFFFFFFF, FE000000]
test_vsr_593_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [7FFF0101, B870FFFF, FFFFFFFF, 80000000]
test_vsr_594_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [07FFF808, 0B8387FF, FFFFFFFF, F0000000]
test_vsr_595_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [FFFFC020, 1783C3FF, FFFFFFFF, F0000000]
test_vsr_596_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [03FFFC04, 05C1C3FF, FFFFFFFF, FC000000]
test_vsr_597_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [01FFFE08, 02C1E1FF, FFFFFFFF, 00000000]
test_vsr_598_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [01FFFE04, 701CFFFF, FFFFFFFF, 00000000]
test_vsr_599_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [01FFFE01, 7070FFFF, FFFFFFFF, 00000000]
test_vsr_600_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [01FFFE02, 02E0E1FF, FFFFFFFF, FE000000]
test_vsr_601_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
test_vsr_602_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [FFFFFFC0, 0000003F, FFFEFFBF, 00010040]
test_vsr_603_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [FFFFFFFF, 0000007F, FFFEFF7F, FE000080]
test_vsr_604_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFFFFFF0, 00000000, FFFFBFEF, F0000401]
test_vsr_605_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [FFFFFFFC, 00000003, FFFFFFFB, 00000004]
test_vsr_606_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [FFFFFFF0, 00000000, FFFFBFEF, F0000401]
test_vsr_607_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFFFE, FE000001]
test_vsr_608_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [0FFFFFF8, 00000007, FFFFEFF7, F0001008]
test_vsr_609_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [01FFFFFF, 00000000, FFFFFDFE, FE000201]
test_vsr_610_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
test_vsr_611_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [3FFFFFE0, 0000001F, FFFFBFDF, C0004020]
test_vsr_612_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [3FFFFF80, 0000003F, FFFFDFF7, F8000280]
test_vsr_613_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [01FFFF80, 0000007F, FFFFEFFB, FE002010]
test_vsr_614_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [7FFFFF80, 0000007F, FFFEFF7F, 80010080]
test_vsr_615_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [01FFFFF0, 00000000, FFFEBFEF, F0000401]
test_vsr_616_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFFFDFE, FE000201]
test_vsr_617_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [01FFFF80, 0000007F, FFFFEFFB, FE002010]
test_vsr_618_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [7FFFFF80, 0000007F, FFFEFF7F, 80010080]
test_vsr_619_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [07FFFFFC, 00000003, FFFFF7FB, F0004010]
test_vsr_620_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [FFFFFFF0, 00000000, FFFFBFEF, F0000401]
test_vsr_621_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [03FFFFFE, 00000001, FFFFFBFD, FC000402]
test_vsr_622_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [01FFFFFC, 00000000, FFFEFFBF, 00000010]
test_vsr_623_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [01FFFFFE, 0000003F, FFFFFDFB, 00000020]
test_vsr_624_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [01FFFFC0, 00000000, FFFFFDFE, 00010080]
test_vsr_625_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [01FFFFFF, 00000000, FFFFFDFE, FE000201]
test_vsr_626_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vsr_627_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vsr_628_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vsr_629_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vsr_630_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vsr_631_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vsr_632_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vsr_633_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [0FFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vsr_634_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [01FFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vsr_635_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vsr_636_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [3FFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vsr_637_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [3FFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vsr_638_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [01FFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vsr_639_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [7FFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vsr_640_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [01FFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vsr_641_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vsr_642_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [01FFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vsr_643_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [7FFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vsr_644_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [07FFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vsr_645_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vsr_646_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [03FFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vsr_647_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [01FFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vsr_648_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [01FFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vsr_649_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [01FFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vsr_650_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsr v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [01FFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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