125 lines
2.6 KiB
ArmAsm
125 lines
2.6 KiB
ArmAsm
test_adde_1:
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#_ REGISTER_IN r4 1
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#_ REGISTER_IN r5 2
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adde r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 3
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 2
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#_ REGISTER_OUT r6 0
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test_adde_2:
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#_ REGISTER_IN r4 1
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#_ REGISTER_IN r5 2
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xor r3, r3, r3
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not r3, r3
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addic r3, r3, 1 # CA=1
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adde r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 4
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 2
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#_ REGISTER_OUT r6 0
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test_adde_3:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 0
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adde r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0
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#_ REGISTER_OUT r6 0
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test_adde_4:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 0
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xor r3, r3, r3
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not r3, r3
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addic r3, r3, 1 # CA=1
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adde r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0
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#_ REGISTER_OUT r6 1
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test_adde_5:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 1
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adde r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 1
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#_ REGISTER_OUT r6 1
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test_adde_6:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 1
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xor r3, r3, r3
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not r3, r3
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addic r3, r3, 1 # CA=1
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adde r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 1
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 1
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#_ REGISTER_OUT r6 1
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test_adde_7:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 123
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adde r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0x000000000000007A
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 123
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#_ REGISTER_OUT r6 1
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test_adde_8:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 123
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xor r3, r3, r3
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not r3, r3
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addic r3, r3, 1 # CA=1
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adde r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0x000000000000007B
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 123
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#_ REGISTER_OUT r6 1
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test_adde_9:
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#_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
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adde r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE
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#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r6 1
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test_adde_10:
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#_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
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xor r3, r3, r3
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not r3, r3
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addic r3, r3, 1 # CA=1
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adde r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFF
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#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r6 1
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