3717167bbe
Use shuffle_ps instead of broadcastss, broadcastss is slower on many intel and amd processors and encodes to the same number of bytes as shuffle_ps Detect and optimize away PERMUTE with a zero src2 and src3 in constant_propagation_pass instead of in the x64 sequence For constant PERMUTE, do the Xor/And prior to LoadConstantXmm instead of in the generated code Simplified code for PERMUTE Added simplification rule that detects (lzcnt(x) >> log2(bitsizeof_x)) == ( x == 0) Added set_srcN(value, idx) which can be used to set the nth source of an instruction, which makes more sense than having three different functions that only differ by the field they touch Added Value::VisitValueOperands for iterating all Value operands an instruction has. Add BackpropTruncations code to simplification_pass Changed the (void**) dereferences of raw_context that are done to grab thread_state to instead reference PPCContext and the thread_state field. Moved the thread_state field to the tail of PPCContext. Moved membase to the tail of PPCContext, since now it is reloaded very infrequently. Rearranged PPCContext so that the condition registers come first (most accesses to them cant get SSA'd), moved lr and ctr to after gp regs since they are not accessed as much as the main gpregs. This way the most frequently accessed registers will be accessible via a rel8 displacement instead of rel32 (ideally, we would have only certain CRs at the start, but xenia does pointer arithmetic on CR0's offset to get CRn) Use alignas(64) to ensure PPCContext's padding Map PPCContext specially so that the low 32 bits of the context register is 0xE0000000, for the 4k page offset check. Also allocate the page before, so that backends can store their own information that is not relevant to the PPCContext on that page and reference that data in the generated asm via 8-bit signed displ or 32-bit signed displ. Currently this page is not being utilized, but I plan on stashing some data critical to the x86 backend there Changed many wrong avx instructions, they worked but they were not intended for the data they operated on, meaning they transferred domains and caused 1-2 cycle stall each time Added SimdDomain checking/deduction to X64Emitter. Used SimdDomain code to fix a lot of float/int domain stalls Use the low 32 bits of the context register instead of constant 0xE0000000 in ComputeAddress Special path for SELECT_V128 with result of comparison that will use a blend instruction instead of and/or Many HIR optimizations added in simp pass A bunch of other stuff running out of time to write this msg
82 lines
2.5 KiB
C++
82 lines
2.5 KiB
C++
/**
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******************************************************************************
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* Xenia : Xbox 360 Emulator Research Project *
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******************************************************************************
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* Copyright 2013 Ben Vanik. All rights reserved. *
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* Released under the BSD license - see LICENSE in the root for more details. *
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******************************************************************************
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*/
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#ifndef XENIA_CPU_BACKEND_BACKEND_H_
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#define XENIA_CPU_BACKEND_BACKEND_H_
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#include <memory>
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#include "xenia/cpu/backend/machine_info.h"
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#include "xenia/cpu/thread_debug_info.h"
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namespace xe {
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namespace cpu {
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class Breakpoint;
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class Function;
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class GuestFunction;
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class Module;
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class Processor;
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} // namespace cpu
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} // namespace xe
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namespace xe {
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namespace cpu {
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namespace backend {
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class Assembler;
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class CodeCache;
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class Backend {
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public:
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explicit Backend();
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virtual ~Backend();
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Processor* processor() const { return processor_; }
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const MachineInfo* machine_info() const { return &machine_info_; }
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CodeCache* code_cache() const { return code_cache_; }
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virtual bool Initialize(Processor* processor);
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virtual void* AllocThreadData();
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virtual void FreeThreadData(void* thread_data);
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virtual void CommitExecutableRange(uint32_t guest_low,
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uint32_t guest_high) = 0;
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virtual std::unique_ptr<Assembler> CreateAssembler() = 0;
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virtual std::unique_ptr<GuestFunction> CreateGuestFunction(
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Module* module, uint32_t address) = 0;
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// Calculates the next host instruction based on the current thread state and
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// current PC. This will look for branches and other control flow
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// instructions.
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virtual uint64_t CalculateNextHostInstruction(ThreadDebugInfo* thread_info,
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uint64_t current_pc) = 0;
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virtual void InstallBreakpoint(Breakpoint* breakpoint) {}
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virtual void InstallBreakpoint(Breakpoint* breakpoint, Function* fn) {}
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virtual void UninstallBreakpoint(Breakpoint* breakpoint) {}
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// ctx points to the start of a ppccontext, ctx - page_allocation_granularity
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// up until the start of ctx may be used by the backend to store whatever data
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// they want
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virtual void InitializeBackendContext(void* ctx) {}
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protected:
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Processor* processor_ = nullptr;
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MachineInfo machine_info_;
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CodeCache* code_cache_ = nullptr;
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};
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} // namespace backend
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} // namespace cpu
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} // namespace xe
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#endif // XENIA_CPU_BACKEND_BACKEND_H_
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