512 lines
7.6 KiB
ArmAsm
512 lines
7.6 KiB
ArmAsm
test_tdlt_1:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 16
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tdlt r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 16
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test_tdlt_1_constant:
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li r3, 24
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li r4, 16
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tdlt r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 16
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test_tdlt_2:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 0
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tdlt r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 0
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test_tdlt_2_constant:
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li r3, 24
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li r4, 0
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tdlt r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 0
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test_tdle_1:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 16
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tdle r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 16
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test_tdle_1_constant:
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li r3, 24
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li r4, 16
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tdle r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 16
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test_tdle_2:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 0
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tdle r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 0
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test_tdle_2_constant:
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li r3, 24
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li r4, 0
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tdle r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 0
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test_tdeq_1:
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#_ REGISTER_IN r3 0
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#_ REGISTER_IN r4 24
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tdeq r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 24
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test_tdeq_1_constant:
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li r3, 0
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li r4, 24
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tdeq r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 24
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test_tdeq_2:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 0
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tdeq r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 0
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test_tdeq_2_constant:
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li r3, 24
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li r4, 0
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tdeq r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 0
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test_tdge_1:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 48
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tdge r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 48
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test_tdge_1_constant:
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li r3, 24
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li r4, 48
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tdge r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 48
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test_tdge_2:
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#_ REGISTER_IN r3 0
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#_ REGISTER_IN r4 48
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tdge r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 48
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test_tdge_2_constant:
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li r3, 0
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li r4, 48
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tdge r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 48
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test_tdge_3:
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#_ REGISTER_IN r3 -1
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#_ REGISTER_IN r4 0
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tdge r3, r4
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blr
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#_ REGISTER_OUT r3 -1
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#_ REGISTER_OUT r4 0
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test_tdge_3_constant:
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li r3, -1
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li r4, 0
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tdge r3, r4
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blr
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#_ REGISTER_OUT r3 -1
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#_ REGISTER_OUT r4 0
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test_tdgt_1:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 48
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tdgt r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 48
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test_tdgt_1_constant:
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li r3, 24
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li r4, 48
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tdgt r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 48
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test_tdgt_2:
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#_ REGISTER_IN r3 0
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#_ REGISTER_IN r4 48
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tdgt r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 48
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test_tdgt_2_constant:
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li r3, 0
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li r4, 48
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tdgt r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 48
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test_tdgt_3:
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#_ REGISTER_IN r3 -1
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#_ REGISTER_IN r4 0
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tdgt r3, r4
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blr
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#_ REGISTER_OUT r3 -1
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#_ REGISTER_OUT r4 0
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test_tdgt_3_constant:
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li r3, -1
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li r4, 0
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tdgt r3, r4
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blr
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#_ REGISTER_OUT r3 -1
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#_ REGISTER_OUT r4 0
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test_tdnl_1:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 48
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tdnl r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 48
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test_tdnl_1_constant:
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li r3, 24
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li r4, 48
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tdnl r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 48
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test_tdnl_2:
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#_ REGISTER_IN r3 0
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#_ REGISTER_IN r4 48
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tdnl r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 48
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test_tdnl_2_constant:
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li r3, 0
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li r4, 48
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tdnl r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 48
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test_tdnl_3:
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#_ REGISTER_IN r3 -1
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#_ REGISTER_IN r4 0
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tdnl r3, r4
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blr
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#_ REGISTER_OUT r3 -1
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#_ REGISTER_OUT r4 0
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test_tdnl_3_constant:
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li r3, -1
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li r4, 0
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tdnl r3, r4
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blr
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#_ REGISTER_OUT r3 -1
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#_ REGISTER_OUT r4 0
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test_tdne_1:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 24
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tdne r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 24
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test_tdne_1_constant:
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li r3, 24
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li r4, 24
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tdne r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 24
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test_tdne_2:
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#_ REGISTER_IN r3 0
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#_ REGISTER_IN r4 0
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tdne r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 0
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test_tdne_2_constant:
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li r3, 0
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li r4, 0
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tdne r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 0
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test_tdng_1:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 16
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tdng r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 16
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test_tdng_1_constant:
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li r3, 24
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li r4, 16
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tdng r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 16
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test_tdng_2:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 0
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tdng r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 0
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test_tdng_2_constant:
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li r3, 24
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li r4, 0
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tdng r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 0
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test_tdng_3:
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#_ REGISTER_IN r3 0
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#_ REGISTER_IN r4 -1
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tdng r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 -1
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test_tdng_3_constant:
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li r3, 0
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li r4, -1
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tdng r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 -1
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test_tdllt_1:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 16
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tdllt r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 16
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test_tdllt_1_constant:
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li r3, 24
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li r4, 16
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tdllt r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 16
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test_tdllt_2:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 0
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tdllt r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 0
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test_tdllt_2_constant:
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li r3, 24
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li r4, 0
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tdllt r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 0
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test_tdlle_1:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 16
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tdlle r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 16
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test_tdlle_1_constant:
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li r3, 24
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li r4, 16
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tdlle r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 16
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test_tdlle_2:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 0
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tdlle r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 0
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test_tdlle_2_constant:
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li r3, 24
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li r4, 0
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tdlle r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 0
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test_tdlge_1:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 48
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tdlge r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 48
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test_tdlge_1_constant:
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li r3, 24
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li r4, 48
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tdlge r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 48
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test_tdlge_2:
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#_ REGISTER_IN r3 0
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#_ REGISTER_IN r4 48
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tdlge r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 48
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test_tdlge_2_constant:
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li r3, 0
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li r4, 48
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tdlge r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 48
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test_tdlgt_1:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 48
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tdlgt r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 48
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test_tdlgt_1_constant:
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li r3, 24
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li r4, 48
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tdlgt r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 48
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test_tdlgt_2:
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#_ REGISTER_IN r3 0
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#_ REGISTER_IN r4 48
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tdlgt r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 48
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test_tdlgt_2_constant:
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li r3, 0
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li r4, 48
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tdlgt r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 48
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test_tdlnl_1:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 48
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tdlnl r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 48
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test_tdlnl_1_constant:
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li r3, 24
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li r4, 48
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tdlnl r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 48
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test_tdlnl_2:
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#_ REGISTER_IN r3 0
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#_ REGISTER_IN r4 48
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tdlnl r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 48
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test_tdlnl_2_constant:
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li r3, 0
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li r4, 48
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tdlnl r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 48
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test_tdlng_1:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 16
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tdlng r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 16
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test_tdlng_1_constant:
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li r3, 24
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li r4, 16
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tdlng r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 16
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test_tdlng_2:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 0
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tdlng r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 0
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test_tdlng_2_constant:
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li r3, 24
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li r4, 0
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tdlng r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 0
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