0ebc109d4d
Add vector simplification pass, so far it only recognizes whether VECTOR_DENORMFLUSH is useless and optimizes them away Tag restgplr/savegplr/restvmx/savevmx/restfpr/savefpr with useful information, i intend to inline them (they tend to be the most heavily called guest functions)
335 lines
9.1 KiB
C++
335 lines
9.1 KiB
C++
#ifndef XENIA_CPU_BACKEND_X64_X64_AMDFX_EXTENSIONS_H_
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#define XENIA_CPU_BACKEND_X64_X64_AMDFX_EXTENSIONS_H_
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#include <stdio.h>
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#include <string.h>
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#include <string>
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namespace xe {
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namespace cpu {
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namespace backend {
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namespace x64 {
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namespace amdfx {
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enum xopcodemap_e : unsigned char {
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XOPCODE_HAS_IMMBYTE = 0x8,
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XOPCODE_NO_IMMBYTE = 0x9
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};
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// base opcodes, without their size specified
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enum xopcode_e : unsigned char {
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xop_VFRCZPD = 0x81,
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xop_VFRCZPS = 0x80,
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xop_VFRCZSD = 0x83,
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xop_VFRCZSS = 0x82,
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xop_VPCMOV = 0xA2,
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xop_VPCOMB = 0xCC,
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xop_VPCOMD = 0xCE,
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xop_VPCOMQ = 0xCF,
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xop_VPCOMUB = 0xEC,
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xop_VPCOMUD = 0xEE,
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xop_VPCOMUQ = 0xEF,
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xop_VPCOMUW = 0xED,
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xop_VPCOMW = 0xCD,
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xop_VPERMIL2PD = 0x49,
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xop_VPERMIL2PS = 0x48,
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xop_VPHADDBD = 0xC2,
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xop_VPHADDBQ = 0xC3,
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xop_VPHADDBW = 0xC1,
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xop_VPHADDDQ = 0xCB,
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xop_VPHADDUBD = 0xD2,
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xop_VPHADDUBQ = 0xD3,
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xop_VPHADDUBW = 0xD1,
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xop_VPHADDUDQ = 0xDB,
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xop_VPHADDUWD = 0xD6,
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xop_VPHADDUWQ = 0xD7,
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xop_VPHADDWD = 0xC6,
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xop_VPHADDWQ = 0xC7,
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xop_VPHSUBBW = 0xE1,
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xop_VPHSUBDQ = 0xE3,
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xop_VPHSUBWD = 0xE2,
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xop_VPMACSDD = 0x9E,
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xop_VPMACSDQH = 0x9F,
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xop_VPMACSDQL = 0x97,
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xop_VPMACSSDD = 0x8E,
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xop_VPMACSSDQH = 0x8F,
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xop_VPMACSSDQL = 0x87,
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xop_VPMACSSWD = 0x86,
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xop_VPMACSSWW = 0x85,
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xop_VPMACSWD = 0x96,
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xop_VPMACSWW = 0x95,
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xop_VPMADCSSWD = 0xA6,
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xop_VPMADCSWD = 0xB6,
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xop_VPPERM = 0xA3,
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xop_VPROTB = 0x90,
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xop_VPROTBI = 0xC0, // imm version
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xop_VPROTD = 0x92,
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xop_VPROTDI = 0xC2,
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xop_VPROTQ = 0x93,
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xop_VPROTQI = 0xC3,
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xop_VPROTW = 0x91,
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xop_VPROTWI = 0xC1,
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xop_VPSHAB = 0x98,
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xop_VPSHAD = 0x9A,
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xop_VPSHAQ = 0x9B,
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xop_VPSHAW = 0x99,
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xop_VPSHLB = 0x94,
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xop_VPSHLD = 0x96,
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xop_VPSHLQ = 0x97,
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xop_VPSHLW = 0x95,
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};
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enum xop_iop_e : unsigned char {
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XOP_BYTE = 0,
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XOP_WORD = 1,
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XOP_DOUBLEWORD = 2,
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XOP_QUADWORD = 3
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};
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enum xop_fop_e : unsigned char {
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XOP_PS = 0,
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XOP_PD = 1,
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XOP_SS = 2,
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XOP_SD = 3
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};
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class xop_byte1_t {
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public:
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union {
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// informative names
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struct {
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/*
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A five bit field encoding a one- or two-byte opcode prefix.
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*/
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unsigned char opcode_map_select : 5;
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/*
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This bit provides a one-bit extension of either the ModRM.r/m
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field to specify a GPR or XMM register or to the SIB base field to
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specify a GPR. This permits access to 16 registers. In 32-bit protected
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and compatibility modes, this bit is ignored. This bit is the
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bit-inverted equivalent of the REX.B bit and is available only in the
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3-byte prefix format.
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*/
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unsigned char inv_1bit_ext_modrm_or_sib : 1;
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/*
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This bit provides a one bit extension of the SIB.index field in
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64-bit mode, permitting access to 16 YMM/XMM and GPR registers. In
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32-bit protected and compatibility modes, this bit must be set to 1.
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This bit is the bit-inverted equivalent of the REX.X bit
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*/
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unsigned char inv_1bit_ext_sib_index : 1;
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/*
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This bit provides a one bit extension of the ModRM.reg field in
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64-bit mode, permitting access to all 16 YMM/XMM and GPR registers. In
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32-bit protected and compatibility modes, this bit must be set to 1.
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This bit is the bit-inverted equivalent of the REX.R bit.
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*/
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unsigned char inv_1bit_ext_modrm_reg_field : 1;
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};
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// amd manual names
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struct {
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unsigned char mmmmm : 5;
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unsigned char B : 1;
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unsigned char X : 1;
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unsigned char R : 1;
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};
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unsigned char encoded;
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};
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};
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class xop_byte2_t {
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public:
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union {
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struct {
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unsigned char
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implied_66f2f3_ext : 2; // 0 = no implied, 1 = 66, 2 = F3, 3 = F2
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unsigned char vector_length : 1;
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unsigned char source_or_dest_reg_specifier_inverted_1s_compl : 4;
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unsigned char scalar_reg_size_override_special : 1;
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};
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// amd manual names
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struct {
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unsigned char pp : 2; // presumably 0 = no implied, 1 = 66, 2 = F2, 3 =
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// F3
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unsigned char L : 1;
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unsigned char vvvv : 4; // src1 for four operand form
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unsigned char W : 1;
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};
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unsigned char encoded;
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};
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};
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class xop_opcode_byte_t {
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public:
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union {
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struct {
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xop_fop_e float_datatype : 2;
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unsigned char __unused0 : 6;
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};
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struct {
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xop_iop_e int_datatype : 2;
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unsigned char __unused1 : 6;
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};
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struct {
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unsigned char oes : 2;
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unsigned char opcode : 6;
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};
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unsigned char encoded;
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};
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};
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class modrm_byte_t {
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public:
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union {
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struct {
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unsigned char rm : 3;
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unsigned char mod : 5; // 4 opnd form dest reg
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};
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unsigned char encoded;
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};
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};
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#pragma pack(push, 1)
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class xop_t {
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public:
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unsigned char imm_8F; // always 0x8F
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xop_byte1_t byte1;
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xop_byte2_t byte2;
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xop_opcode_byte_t opcode;
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modrm_byte_t modrm;
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unsigned char imm8;
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xop_t() : imm_8F(0x8F) {
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byte1.encoded = 0;
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byte2.encoded = 0;
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opcode.encoded = 0;
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modrm.encoded = 0;
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}
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unsigned AssembledSize() const {
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if (byte1.opcode_map_select == XOPCODE_NO_IMMBYTE) {
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return 5;
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} else {
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return 6;
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}
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}
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template <typename TCall>
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void ForeachByte(TCall&& cb) {
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cb(imm_8F);
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cb(byte1.encoded);
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cb(byte2.encoded);
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cb(opcode.encoded);
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cb(modrm.encoded);
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if (AssembledSize() == 6) {
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cb(imm8);
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}
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}
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};
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#pragma pack(pop)
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static void xop_set_fouroperand_form(xop_t& xop, unsigned xmmidx_dest,
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unsigned xmmidx_src1, unsigned xmmidx_src2,
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unsigned xmmidx_src3, xopcode_e opcode,
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bool has_immbyte = true) {
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xop.opcode.encoded = opcode;
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xop.byte1.encoded = 0xe8;
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if (has_immbyte) {
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xop.byte1.opcode_map_select = XOPCODE_HAS_IMMBYTE;
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} else {
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xop.byte1.opcode_map_select = XOPCODE_NO_IMMBYTE;
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}
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xop.imm8 = xmmidx_src3 << 4;
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xop.modrm.rm = xmmidx_src2 & 0b111;
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xop.byte1.inv_1bit_ext_modrm_reg_field = (xmmidx_dest >> 3) ^ 1;
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xop.byte1.inv_1bit_ext_modrm_or_sib = (xmmidx_src2 >> 3) ^ 1;
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xop.byte2.vvvv = ~xmmidx_src1;
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xop.modrm.encoded |= 0xC0;
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xop.modrm.mod |= xmmidx_dest & 0b111;
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}
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enum class xopcompare_e : uint32_t {
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LT = 0b000,
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LTE = 0b001,
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GT = 0b010,
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GTE = 0b011,
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EQ = 0b100,
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NEQ = 0b101,
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FALSEY = 0b110, // there doesnt seem to be much in the way of documentation
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// for these two
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TRUTHEY = 0b111
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};
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namespace operations {
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#define SIMPLE_FOUROPERAND(funcname, opcode) \
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static xop_t funcname(unsigned destidx, unsigned src1idx, unsigned src2idx, \
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unsigned src3idx) { \
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xop_t result{}; \
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xop_set_fouroperand_form(result, destidx, src1idx, src2idx, src3idx, \
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opcode, true); \
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return result; \
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}
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SIMPLE_FOUROPERAND(vpcmov, xop_VPCMOV)
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SIMPLE_FOUROPERAND(vpperm, xop_VPPERM)
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#define COMPAREFUNC(name, opcode) \
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static xop_t name(unsigned dst, unsigned src1, unsigned src2, \
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xopcompare_e imm8) { \
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xop_t xop; \
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xop_set_fouroperand_form(xop, dst, src1, src2, 0, opcode, true); \
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xop.imm8 = static_cast<uint8_t>(static_cast<uint32_t>(imm8)); \
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return xop; \
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}
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COMPAREFUNC(vpcomb, xop_VPCOMB)
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COMPAREFUNC(vpcomub, xop_VPCOMUB)
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COMPAREFUNC(vpcomw, xop_VPCOMW)
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COMPAREFUNC(vpcomuw, xop_VPCOMUW)
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COMPAREFUNC(vpcomd, xop_VPCOMD)
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COMPAREFUNC(vpcomud, xop_VPCOMUD)
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COMPAREFUNC(vpcomq, xop_VPCOMQ)
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COMPAREFUNC(vpcomuq, xop_VPCOMUQ)
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#define SIMPLE_THREEOPERAND(funcname, opcode) \
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static xop_t funcname(unsigned destidx, unsigned src1idx, \
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unsigned src2idx) { \
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xop_t result{}; \
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xop_set_fouroperand_form(result, destidx, src1idx, src2idx, 0, opcode, \
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false); \
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return result; \
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}
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SIMPLE_THREEOPERAND(vprotb, xop_VPROTB)
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SIMPLE_THREEOPERAND(vprotw, xop_VPROTW)
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SIMPLE_THREEOPERAND(vprotd, xop_VPROTD)
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SIMPLE_THREEOPERAND(vprotq, xop_VPROTQ)
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SIMPLE_THREEOPERAND(vpshab, xop_VPSHAB)
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SIMPLE_THREEOPERAND(vpshaw, xop_VPSHAW)
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SIMPLE_THREEOPERAND(vpshad, xop_VPSHAD)
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SIMPLE_THREEOPERAND(vpshaq, xop_VPSHAQ)
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SIMPLE_THREEOPERAND(vpshlb, xop_VPSHLB)
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SIMPLE_THREEOPERAND(vpshlw, xop_VPSHLW)
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SIMPLE_THREEOPERAND(vpshld, xop_VPSHLD)
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SIMPLE_THREEOPERAND(vpshlq, xop_VPSHLQ)
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#undef SIMPLE_THREEOPERAND
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#undef SIMPLE_FOUROPERAND
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#undef COMPAREFUNC
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} // namespace operations
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} // namespace amdfx
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} // namespace x64
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} // namespace backend
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} // namespace cpu
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} // namespace xe
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#endif // XENIA_CPU_BACKEND_X64_X64_AMDFX_EXTENSIONS_H_
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