164 lines
6.7 KiB
Plaintext
164 lines
6.7 KiB
Plaintext
/**
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******************************************************************************
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* Xenia : Xbox 360 Emulator Research Project *
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******************************************************************************
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* Copyright 2022 Ben Vanik. All rights reserved. *
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* Released under the BSD license - see LICENSE in the root for more details. *
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******************************************************************************
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*/
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#ifndef XENIA_GPU_SHADERS_TEXTURE_LOAD_XESLI_
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#define XENIA_GPU_SHADERS_TEXTURE_LOAD_XESLI_
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#include "endian.xesli"
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#include "texture_address.xesli"
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// 128 threads per group (the maximum wave size supported by DXIL and SPIR-V,
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// and the minimum required number of threads per group on Vulkan), laid out as
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// 4x32 (32 texels along Y per group - one guest tile) - starting with 64x32
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// blocks (2x1 guest tiles) per group for 8bpb / 16bpb, and smaller for larger
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// block sizes. Since the mip tail is packed in 32x / x32 storage, there's no
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// need for the Y group size smaller than 32 - 8x16, for instance, would result
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// in 128x16 blocks per group for 8bpb / 16bpb, and for a 32x32 mip tail, there
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// would be two groups rather than one, for a total of 128x32 blocks - 75% of
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// the work will be wasted rather than 50% with one 64x32-block group.
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#define xesl_localSize_x 4
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#define xesl_localSize_y 32
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#define xesl_localSize_z 1
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xesl_constantBuffer_begin(xe_texture_load_constants, set=2, binding=0, b0,
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space0)
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uint xe_texture_load_is_tiled_3d_endian_scale;
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// Base offset in bytes, resolution-scaled.
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uint xe_texture_load_guest_offset;
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// For tiled textures - row pitch in guest blocks, aligned to 32, unscaled.
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// For linear textures - row pitch in bytes.
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uint xe_texture_load_guest_pitch_aligned;
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// For 3D textures only (ignored otherwise) - aligned to 32, unscaled.
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uint xe_texture_load_guest_z_stride_block_rows_aligned;
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// - std140 vector boundary -
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// If this is a packed mip tail, this is aligned to tile dimensions.
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// Resolution-scaled.
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xesl_uint3 xe_texture_load_size_blocks;
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// Base offset in bytes.
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uint xe_texture_load_host_offset;
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// - std140 vector boundary -
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uint xe_texture_load_host_pitch;
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uint xe_texture_load_height_texels;
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xesl_constantBuffer_end(xe_texture_load_constants)
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#define XE_TEXTURE_LOAD_CONSTANT_BUFFER_BINDING \
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xesl_constantBuffer_binding(xe_texture_load_constants, buffer(0))
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struct XeTextureLoadInfo {
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bool is_tiled;
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bool is_3d;
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uint endian_32;
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xesl_uint2 resolution_scale;
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uint guest_offset;
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uint guest_pitch_aligned;
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uint guest_z_stride_block_rows_aligned;
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xesl_uint3 size_blocks;
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uint host_offset;
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uint host_pitch;
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uint height_texels;
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};
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XeTextureLoadInfo XeTextureLoadGetInfo(
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xesl_function_param_constantBuffer(xe_texture_load_constants)) {
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XeTextureLoadInfo load_info;
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uint is_tiled_3d_endian_scale = xesl_constant(
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xe_texture_load_constants, xe_texture_load_is_tiled_3d_endian_scale);
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#ifdef XE_TEXTURE_LOAD_RESOLUTION_SCALED
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// Only resolved textures can be resolution-scaled, and resolving is only
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// possible to a tiled destination.
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load_info.is_tiled = true;
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#else
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load_info.is_tiled = (is_tiled_3d_endian_scale & 1u) != 0u;
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#endif
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load_info.is_3d = (is_tiled_3d_endian_scale & (1u << 1u)) != 0u;
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load_info.endian_32 = (is_tiled_3d_endian_scale >> 2u) & 3u;
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#ifdef XE_TEXTURE_LOAD_RESOLUTION_SCALED
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load_info.resolution_scale =
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((xesl_uint_x2(is_tiled_3d_endian_scale)) >> xesl_uint2(4u, 6u)) & 3u;
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#else
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load_info.resolution_scale = xesl_uint2(1u, 1u);
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#endif
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load_info.guest_offset =
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xesl_constant(xe_texture_load_constants, xe_texture_load_guest_offset);
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load_info.guest_pitch_aligned = xesl_constant(
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xe_texture_load_constants, xe_texture_load_guest_pitch_aligned);
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load_info.guest_z_stride_block_rows_aligned =
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xesl_constant(xe_texture_load_constants,
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xe_texture_load_guest_z_stride_block_rows_aligned);
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load_info.size_blocks =
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xesl_constant(xe_texture_load_constants, xe_texture_load_size_blocks);
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load_info.host_offset =
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xesl_constant(xe_texture_load_constants, xe_texture_load_host_offset);
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load_info.host_pitch =
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xesl_constant(xe_texture_load_constants, xe_texture_load_host_pitch);
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load_info.height_texels =
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xesl_constant(xe_texture_load_constants, xe_texture_load_height_texels);
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return load_info;
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}
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// bpb and bpb_log2 are separate because bpb may be not a power of 2 (like 96).
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uint XeTextureLoadGuestBlockOffset(XeTextureLoadInfo load_info,
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xesl_uint3 block_index, uint bpb,
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uint bpb_log2) {
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#ifdef XE_TEXTURE_LOAD_RESOLUTION_SCALED
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// Only resolved textures can be resolution-scaled, and resolving is only
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// possible to a tiled destination.
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return
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load_info.guest_offset +
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XeTextureScaledTiledOffset(load_info.is_3d, block_index,
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load_info.guest_pitch_aligned,
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load_info.guest_z_stride_block_rows_aligned,
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bpb_log2, load_info.resolution_scale);
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#else
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int block_offset_guest;
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xesl_dont_flatten if (load_info.is_tiled) {
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xesl_dont_flatten if (load_info.is_3d) {
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block_offset_guest = XeTextureTiledOffset3D(
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xesl_int3(block_index), load_info.guest_pitch_aligned,
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load_info.guest_z_stride_block_rows_aligned, bpb_log2);
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} else {
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block_offset_guest = XeTextureTiledOffset2D(
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xesl_int2(block_index.xy), load_info.guest_pitch_aligned,
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bpb_log2);
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}
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} else {
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block_offset_guest = XeTextureGuestLinearOffset(
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xesl_int3(block_index), load_info.guest_pitch_aligned,
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load_info.guest_z_stride_block_rows_aligned, bpb);
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}
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return uint(int(load_info.guest_offset) + block_offset_guest);
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#endif
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}
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// Offset of the beginning of the odd R32G32/R32G32B32A32 load address from the
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// address of the even load, for power-of-two-sized textures.
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uint XeTextureLoadRightConsecutiveBlocksOffset(XeTextureLoadInfo load_info,
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uint block_x, uint bpb_log2) {
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#ifdef XE_TEXTURE_LOAD_RESOLUTION_SCALED
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return XeTextureScaledRightSubUnitOffsetInConsecutivePair(
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block_x, bpb_log2, load_info.resolution_scale);
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#else
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uint offset;
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uint consecutive_blocks_log2 =
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XeTextureTiledConsecutiveBlocksLog2(bpb_log2);
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xesl_dont_flatten if (load_info.is_tiled) {
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offset = XeTextureTiledOddConsecutiveBlocksOffset(bpb_log2);
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} else {
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offset = 1u << (consecutive_blocks_log2 + bpb_log2);
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}
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return offset;
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#endif
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}
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#endif // XENIA_GPU_SHADERS_TEXTURE_LOAD_XESLI_
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