cb85fe401c
But for normal msvc builds i would put it at around 30-50% Added per-xexmodule caching of information per instruction, can be used to remember what code needs compiling at start up Record what guest addresses wrote mmio and backpropagate that to future runs, eliminating dependence on exception trapping. this makes many games like h3 actually tolerable to run under a debugger fixed a number of errors where temporaries were being passed by reference/pointer Can now be compiled with clang-cl 14.0.1, requires -Werror off though and some other solution/project changes. Added macros wrapping compiler extensions like noinline, forceinline, __expect, and cold. Removed the "global lock" in guest code completely. It does not properly emulate the behavior of mfmsrd/mtmsr and it seriously cripples amd cpus. Removing this yielded around a 3x speedup in Halo Reach for me. Disabled the microprofiler for now. The microprofiler has a huge performance cost associated with it. Developers can re-enable it in the base/profiling header if they really need it Disable the trace writer in release builds. despite just returning after checking if the file was open the trace functions were consuming about 0.60% cpu time total Add IsValidReg, GetRegisterInfo is a huge (about 45k) branching function and using that to check if a register was valid consumed a significant chunk of time Optimized RingBuffer::ReadAndSwap and RingBuffer::read_count. This gave us the largest overall boost in performance. The memcpies were unnecessary and one of them was always a no-op Added simplification rules for multiplicative patterns like (x+x), (x<<1)+x For the most frequently called win32 functions i added code to call their underlying NT implementations, which lets us skip a lot of MS code we don't care about/isnt relevant to our usecases ^this can be toggled off in the platform_win header handle indirect call true with constant function pointer, was occurring in h3 lookup host format swizzle in denser array by default, don't check if a gpu register is unknown, instead just check if its out of range. controlled by a cvar ^looking up whether its known or not took approx 0.3% cpu time Changed some things in /cpu to make the project UNITYBUILD friendly The timer thread was spinning way too much and consuming a ton of cpu, changed it to use a blocking wait instead tagged some conditions as XE_UNLIKELY/LIKELY based on profiler feedback (will only affect clang builds) Shifted around some code in CommandProcessor::WriteRegister based on how frequently it was executed added support for docdecaduple precision floating point so that we can represent our performance gains numerically tons of other stuff im probably forgetting
871 lines
23 KiB
C++
871 lines
23 KiB
C++
/*
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******************************************************************************
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* Xenia : Xbox 360 Emulator Research Project *
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******************************************************************************
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* Copyright 2021 Ben Vanik. All rights reserved. *
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* Released under the BSD license - see LICENSE in the root for more details. *
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******************************************************************************
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*/
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#include "xenia/cpu/ppc/ppc_emit-private.h"
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#include "xenia/base/assert.h"
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#include "xenia/cpu/cpu_flags.h"
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#include "xenia/cpu/ppc/ppc_context.h"
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#include "xenia/cpu/ppc/ppc_frontend.h"
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#include "xenia/cpu/ppc/ppc_hir_builder.h"
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#include <stddef.h>
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namespace xe {
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namespace cpu {
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namespace ppc {
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// TODO(benvanik): remove when enums redefined.
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using namespace xe::cpu::hir;
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using xe::cpu::hir::Label;
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using xe::cpu::hir::Value;
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int InstrEmit_branch(PPCHIRBuilder& f, const char* src, uint64_t cia,
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Value* nia, bool lk, Value* cond = NULL,
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bool expect_true = true, bool nia_is_lr = false) {
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uint32_t call_flags = 0;
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// TODO(benvanik): this may be wrong and overwrite LRs when not desired!
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// The docs say always, though...
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// Note that we do the update before we branch/call as we need it to
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// be correct for returns.
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if (lk) {
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Value* return_address = f.LoadConstantUint64(cia + 4);
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f.SetReturnAddress(return_address);
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f.StoreLR(return_address);
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}
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if (!lk) {
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// If LR is not set this call will never return here.
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call_flags |= CALL_TAIL;
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}
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// TODO(benvanik): set CALL_TAIL if !lk and the last block in the fn.
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// This is almost always a jump to restore gpr.
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if (nia->IsConstant()) {
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// Direct branch to address.
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// If it's a block inside of ourself, setup a fast jump.
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// Unless it's to ourselves directly, in which case it's
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// recursion.
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uint32_t nia_value = nia->AsUint64() & 0xFFFFFFFF;
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bool is_recursion = false;
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if (nia_value == f.function()->address() && lk) {
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is_recursion = true;
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}
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Label* label = is_recursion ? NULL : f.LookupLabel(nia_value);
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if (label) {
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// Branch to label.
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uint32_t branch_flags = 0;
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if (cond) {
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if (expect_true) {
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f.BranchTrue(cond, label, branch_flags);
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} else {
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f.BranchFalse(cond, label, branch_flags);
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}
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} else {
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f.Branch(label, branch_flags);
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}
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} else {
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// Call function.
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auto function = f.LookupFunction(nia_value);
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if (cond) {
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if (!expect_true) {
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cond = f.IsFalse(cond);
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}
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f.CallTrue(cond, function, call_flags);
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} else {
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f.Call(function, call_flags);
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}
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}
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} else {
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// Indirect branch to pointer.
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// TODO(benvanik): runtime recursion detection?
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// TODO(benvanik): run a DFA pass to see if we can detect whether this is
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// a normal function return that is pulling the LR from the stack that
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// it set in the prolog. If so, we can omit the dynamic check!
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//// Dynamic test when branching to LR, which is usually used for the return.
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//// We only do this if LK=0 as returns wouldn't set LR.
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//// Ideally it's a return and we can just do a simple ret and be done.
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//// If it's not, we fall through to the full indirection logic.
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// if (!lk && reg == kXEPPCRegLR) {
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// // The return block will spill registers for us.
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// // TODO(benvanik): 'lr_mismatch' debug info.
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// // Note: we need to test on *only* the 32-bit target, as the target ptr may
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// // have garbage in the upper 32 bits.
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// c.cmp(target.r32(), c.getGpArg(1).r32());
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// // TODO(benvanik): evaluate hint here.
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// c.je(e.GetReturnLabel(), kCondHintLikely);
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//}
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#if 0
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// This breaks longjump, as that uses blr with a non-return lr.
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// It'd be nice to move SET_RETURN_ADDRESS semantics up into context
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// so that we can just use this.
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if (!lk && nia_is_lr) {
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// Return (most likely).
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// TODO(benvanik): test? ReturnCheck()?
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if (cond) {
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if (!expect_true) {
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cond = f.IsFalse(cond);
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}
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f.ReturnTrue(cond);
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} else {
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f.Return();
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}
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} else {
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#else
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{
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#endif
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// Jump to pointer.
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bool likely_return = !lk && nia_is_lr;
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if (likely_return) {
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call_flags |= CALL_POSSIBLE_RETURN;
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}
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if (cond) {
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if (!expect_true) {
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cond = f.IsFalse(cond);
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}
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f.CallIndirectTrue(cond, nia, call_flags);
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} else {
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f.CallIndirect(nia, call_flags);
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}
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}
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}
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return 0;
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} // namespace ppc
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int InstrEmit_bx(PPCHIRBuilder& f, const InstrData& i) {
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// if AA then
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// NIA <- EXTS(LI || 0b00)
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// else
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// NIA <- CIA + EXTS(LI || 0b00)
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// if LK then
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// LR <- CIA + 4
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uint32_t nia;
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if (i.I.AA) {
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nia = (uint32_t)XEEXTS26(i.I.LI << 2);
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} else {
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nia = (uint32_t)(i.address + XEEXTS26(i.I.LI << 2));
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}
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return InstrEmit_branch(f, "bx", i.address, f.LoadConstantUint32(nia),
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i.I.LK);
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}
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int InstrEmit_bcx(PPCHIRBuilder& f, const InstrData& i) {
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// if ¬BO[2] then
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// CTR <- CTR - 1
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// ctr_ok <- BO[2] | ((CTR[0:63] != 0) XOR BO[3])
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// cond_ok <- BO[0] | (CR[BI+32] ≡ BO[1])
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// if ctr_ok & cond_ok then
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// if AA then
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// NIA <- EXTS(BD || 0b00)
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// else
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// NIA <- CIA + EXTS(BD || 0b00)
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// if LK then
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// LR <- CIA + 4
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// NOTE: the condition bits are reversed!
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// 01234 (docs)
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// 43210 (real)
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Value* ctr_ok = NULL;
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if (select_bits(i.B.BO, 2, 2)) {
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// Ignore ctr.
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} else {
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// Decrement counter.
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Value* ctr = f.LoadCTR();
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ctr = f.Sub(ctr, f.LoadConstantUint64(1));
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f.StoreCTR(ctr);
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// Ctr check.
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ctr = f.Truncate(ctr, INT32_TYPE);
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// TODO(benvanik): could do something similar to cond and avoid the
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// is_true/branch_true pairing.
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if (select_bits(i.B.BO, 1, 1)) {
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ctr_ok = f.IsFalse(ctr);
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} else {
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ctr_ok = f.IsTrue(ctr);
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}
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}
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Value* cond_ok = NULL;
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bool not_cond_ok = false;
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if (select_bits(i.B.BO, 4, 4)) {
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// Ignore cond.
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} else {
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Value* cr = f.LoadCRField(i.B.BI >> 2, i.B.BI & 3);
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cond_ok = cr;
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if (select_bits(i.B.BO, 3, 3)) {
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// Expect true.
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not_cond_ok = false;
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} else {
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// Expect false.
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not_cond_ok = true;
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}
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}
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// We do a bit of optimization here to make the llvm assembly easier to read.
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Value* ok = NULL;
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bool expect_true = true;
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if (ctr_ok && cond_ok) {
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if (not_cond_ok) {
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cond_ok = f.IsFalse(cond_ok);
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}
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ok = f.And(ctr_ok, cond_ok);
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} else if (ctr_ok) {
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ok = ctr_ok;
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} else if (cond_ok) {
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ok = cond_ok;
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expect_true = !not_cond_ok;
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}
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uint32_t nia;
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if (i.B.AA) {
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nia = (uint32_t)XEEXTS16(i.B.BD << 2);
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} else {
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nia = (uint32_t)(i.address + XEEXTS16(i.B.BD << 2));
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}
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return InstrEmit_branch(f, "bcx", i.address, f.LoadConstantUint32(nia),
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i.B.LK, ok, expect_true);
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}
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int InstrEmit_bcctrx(PPCHIRBuilder& f, const InstrData& i) {
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// cond_ok <- BO[0] | (CR[BI+32] ≡ BO[1])
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// if cond_ok then
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// NIA <- CTR[0:61] || 0b00
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// if LK then
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// LR <- CIA + 4
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// NOTE: the condition bits are reversed!
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// 01234 (docs)
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// 43210 (real)
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Value* cond_ok = NULL;
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bool not_cond_ok = false;
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if (select_bits(i.XL.BO, 4, 4)) {
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// Ignore cond.
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} else {
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Value* cr = f.LoadCRField(i.XL.BI >> 2, i.XL.BI & 3);
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cond_ok = cr;
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if (select_bits(i.XL.BO, 3, 3)) {
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// Expect true.
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not_cond_ok = false;
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} else {
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// Expect false.
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not_cond_ok = true;
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}
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}
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bool expect_true = !not_cond_ok;
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return InstrEmit_branch(f, "bcctrx", i.address, f.LoadCTR(), i.XL.LK, cond_ok,
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expect_true);
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}
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int InstrEmit_bclrx(PPCHIRBuilder& f, const InstrData& i) {
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// if ¬BO[2] then
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// CTR <- CTR - 1
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// ctr_ok <- BO[2] | ((CTR[0:63] != 0) XOR BO[3]
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// cond_ok <- BO[0] | (CR[BI+32] ≡ BO[1])
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// if ctr_ok & cond_ok then
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// NIA <- LR[0:61] || 0b00
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// if LK then
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// LR <- CIA + 4
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// NOTE: the condition bits are reversed!
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// 01234 (docs)
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// 43210 (real)
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Value* ctr_ok = NULL;
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if (select_bits(i.XL.BO, 2, 2)) {
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// Ignore ctr.
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} else {
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// Decrement counter.
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Value* ctr = f.LoadCTR();
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ctr = f.Sub(ctr, f.LoadConstantUint64(1));
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f.StoreCTR(ctr);
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// Ctr check.
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ctr = f.Truncate(ctr, INT32_TYPE);
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// TODO(benvanik): could do something similar to cond and avoid the
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// is_true/branch_true pairing.
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if (select_bits(i.XL.BO, 1, 1)) {
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ctr_ok = f.IsFalse(ctr);
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} else {
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ctr_ok = f.IsTrue(ctr);
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}
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}
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Value* cond_ok = NULL;
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bool not_cond_ok = false;
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if (select_bits(i.XL.BO, 4, 4)) {
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// Ignore cond.
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} else {
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Value* cr = f.LoadCRField(i.XL.BI >> 2, i.XL.BI & 3);
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cond_ok = cr;
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if (select_bits(i.XL.BO, 3, 3)) {
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// Expect true.
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not_cond_ok = false;
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} else {
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// Expect false.
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not_cond_ok = true;
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}
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}
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// We do a bit of optimization here to make the llvm assembly easier to read.
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Value* ok = NULL;
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bool expect_true = true;
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if (ctr_ok && cond_ok) {
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if (not_cond_ok) {
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cond_ok = f.IsFalse(cond_ok);
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}
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ok = f.And(ctr_ok, cond_ok);
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} else if (ctr_ok) {
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ok = ctr_ok;
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} else if (cond_ok) {
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ok = cond_ok;
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expect_true = !not_cond_ok;
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}
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return InstrEmit_branch(f, "bclrx", i.address, f.LoadLR(), i.XL.LK, ok,
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expect_true, true);
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}
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// Condition register logical (A-23)
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int InstrEmit_crand(PPCHIRBuilder& f, const InstrData& i) {
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// CR[bt] <- CR[ba] & CR[bb] bt=bo, ba=bi, bb=bb
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Value* ba = f.LoadCRField(i.XL.BI >> 2, i.XL.BI & 3);
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Value* bb = f.LoadCRField(i.XL.BB >> 2, i.XL.BB & 3);
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Value* bt = f.And(ba, bb);
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f.StoreCRField(i.XL.BO >> 2, i.XL.BO & 3, bt);
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return 0;
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}
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int InstrEmit_crandc(PPCHIRBuilder& f, const InstrData& i) {
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// CR[bt] <- CR[ba] & ¬CR[bb] bt=bo, ba=bi, bb=bb
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Value* ba = f.LoadCRField(i.XL.BI >> 2, i.XL.BI & 3);
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Value* bb = f.LoadCRField(i.XL.BB >> 2, i.XL.BB & 3);
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Value* bt = f.And(ba, f.And(f.Not(bb), f.LoadConstantInt8(0x01)));
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f.StoreCRField(i.XL.BO >> 2, i.XL.BO & 3, bt);
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return 0;
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}
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int InstrEmit_creqv(PPCHIRBuilder& f, const InstrData& i) {
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// CR[bt] <- CR[ba] == CR[bb] bt=bo, ba=bi, bb=bb
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Value* ba = f.LoadCRField(i.XL.BI >> 2, i.XL.BI & 3);
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Value* bb = f.LoadCRField(i.XL.BB >> 2, i.XL.BB & 3);
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Value* bt = f.CompareEQ(ba, bb);
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f.StoreCRField(i.XL.BO >> 2, i.XL.BO & 3, bt);
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return 0;
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}
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int InstrEmit_crnand(PPCHIRBuilder& f, const InstrData& i) {
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// CR[bt] <- ¬(CR[ba] & CR[bb]) bt=bo, ba=bi, bb=bb
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Value* ba = f.LoadCRField(i.XL.BI >> 2, i.XL.BI & 3);
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Value* bb = f.LoadCRField(i.XL.BB >> 2, i.XL.BB & 3);
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Value* bt = f.And(f.Not(f.And(ba, bb)), f.LoadConstantInt8(0x01));
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f.StoreCRField(i.XL.BO >> 2, i.XL.BO & 3, bt);
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return 0;
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}
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int InstrEmit_crnor(PPCHIRBuilder& f, const InstrData& i) {
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// CR[bt] <- ¬(CR[ba] | CR[bb]) bt=bo, ba=bi, bb=bb
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Value* ba = f.LoadCRField(i.XL.BI >> 2, i.XL.BI & 3);
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Value* bb = f.LoadCRField(i.XL.BB >> 2, i.XL.BB & 3);
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Value* bt = f.And(f.Not(f.Or(ba, bb)), f.LoadConstantInt8(0x01));
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f.StoreCRField(i.XL.BO >> 2, i.XL.BO & 3, bt);
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return 0;
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}
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int InstrEmit_cror(PPCHIRBuilder& f, const InstrData& i) {
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// CR[bt] <- CR[ba] | CR[bb] bt=bo, ba=bi, bb=bb
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Value* ba = f.LoadCRField(i.XL.BI >> 2, i.XL.BI & 3);
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Value* bb = f.LoadCRField(i.XL.BB >> 2, i.XL.BB & 3);
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Value* bt = f.Or(ba, bb);
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f.StoreCRField(i.XL.BO >> 2, i.XL.BO & 3, bt);
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return 0;
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}
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int InstrEmit_crorc(PPCHIRBuilder& f, const InstrData& i) {
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// CR[bt] <- CR[ba] | ¬CR[bb] bt=bo, ba=bi, bb=bb
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Value* ba = f.LoadCRField(i.XL.BI >> 2, i.XL.BI & 3);
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Value* bb = f.LoadCRField(i.XL.BB >> 2, i.XL.BB & 3);
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Value* bt = f.Or(ba, f.And(f.Not(bb), f.LoadConstantInt8(0x01)));
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f.StoreCRField(i.XL.BO >> 2, i.XL.BO & 3, bt);
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return 0;
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}
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int InstrEmit_crxor(PPCHIRBuilder& f, const InstrData& i) {
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// CR[bt] <- CR[ba] xor CR[bb] bt=bo, ba=bi, bb=bb
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Value* ba = f.LoadCRField(i.XL.BI >> 2, i.XL.BI & 3);
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Value* bb = f.LoadCRField(i.XL.BB >> 2, i.XL.BB & 3);
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Value* bt = f.Xor(ba, bb);
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f.StoreCRField(i.XL.BO >> 2, i.XL.BO & 3, bt);
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return 0;
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}
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int InstrEmit_mcrf(PPCHIRBuilder& f, const InstrData& i) {
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uint32_t crfd = i.XL.BO >> 2;
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Value* bi = f.LoadCR(i.XL.BI >> 2);
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f.StoreCR(crfd, bi);
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f.UpdateCR(crfd, bi);
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return 0;
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}
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|
// System linkage (A-24)
|
|
|
|
int InstrEmit_sc(PPCHIRBuilder& f, const InstrData& i) {
|
|
// Game code should only ever use LEV=0.
|
|
// LEV=2 is to signify 'call import' from Xenia.
|
|
// TODO(gibbed): syscalls!
|
|
if (i.SC.LEV == 0) {
|
|
f.CallExtern(f.builtins()->syscall_handler);
|
|
return 0;
|
|
}
|
|
if (i.SC.LEV == 2) {
|
|
f.CallExtern(f.function());
|
|
return 0;
|
|
}
|
|
XEINSTRNOTIMPLEMENTED();
|
|
return 1;
|
|
}
|
|
|
|
// Trap (A-25)
|
|
|
|
constexpr uint32_t TRAP_SLT = 1 << 4, TRAP_SGT = 1 << 3, TRAP_EQ = 1 << 2,
|
|
TRAP_ULT = 1 << 1, TRAP_UGT = 1;
|
|
|
|
int InstrEmit_trap(PPCHIRBuilder& f, const InstrData& i, Value* va, Value* vb,
|
|
uint32_t TO) {
|
|
// if (a < b) & TO[0] then TRAP
|
|
// if (a > b) & TO[1] then TRAP
|
|
// if (a = b) & TO[2] then TRAP
|
|
// if (a <u b) & TO[3] then TRAP
|
|
// if (a >u b) & TO[4] then TRAP
|
|
// Bits swapped:
|
|
// 01234
|
|
// 43210
|
|
if (!TO) {
|
|
return 0;
|
|
}
|
|
Value* v = nullptr;
|
|
|
|
switch (TO) {
|
|
case TRAP_SLT | TRAP_EQ: {
|
|
v = f.CompareSLE(va, vb);
|
|
break;
|
|
}
|
|
case TRAP_SGT | TRAP_EQ: {
|
|
v = f.CompareSGE(va, vb);
|
|
break;
|
|
}
|
|
case TRAP_ULT | TRAP_EQ: {
|
|
v = f.CompareULE(va, vb);
|
|
break;
|
|
}
|
|
case TRAP_UGT | TRAP_EQ: {
|
|
v = f.CompareUGE(va, vb);
|
|
break;
|
|
}
|
|
case TRAP_SGT | TRAP_SLT:
|
|
case TRAP_UGT | TRAP_ULT: { // used anywhere?
|
|
v = f.CompareNE(va, vb);
|
|
break;
|
|
}
|
|
default: {
|
|
// if (TO == )
|
|
if (TO & TRAP_SLT) {
|
|
// a < b
|
|
auto cmp = f.CompareSLT(va, vb);
|
|
v = v ? f.Or(v, cmp) : cmp;
|
|
}
|
|
if (TO & TRAP_SGT) {
|
|
// a > b
|
|
auto cmp = f.CompareSGT(va, vb);
|
|
v = v ? f.Or(v, cmp) : cmp;
|
|
}
|
|
if (TO & TRAP_EQ) {
|
|
// a = b
|
|
auto cmp = f.CompareEQ(va, vb);
|
|
v = v ? f.Or(v, cmp) : cmp;
|
|
}
|
|
if (TO & TRAP_ULT) {
|
|
// a <u b
|
|
auto cmp = f.CompareULT(va, vb);
|
|
v = v ? f.Or(v, cmp) : cmp;
|
|
}
|
|
if (TO & TRAP_UGT) {
|
|
// a >u b
|
|
auto cmp = f.CompareUGT(va, vb);
|
|
v = v ? f.Or(v, cmp) : cmp;
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
if (v) {
|
|
f.TrapTrue(v);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int InstrEmit_td(PPCHIRBuilder& f, const InstrData& i) {
|
|
// a <- (RA)
|
|
// b <- (RB)
|
|
// if (a < b) & TO[0] then TRAP
|
|
// if (a > b) & TO[1] then TRAP
|
|
// if (a = b) & TO[2] then TRAP
|
|
// if (a <u b) & TO[3] then TRAP
|
|
// if (a >u b) & TO[4] then TRAP
|
|
Value* ra = f.LoadGPR(i.X.RA);
|
|
Value* rb = f.LoadGPR(i.X.RB);
|
|
return InstrEmit_trap(f, i, ra, rb, i.X.RT);
|
|
}
|
|
|
|
int InstrEmit_tdi(PPCHIRBuilder& f, const InstrData& i) {
|
|
// a <- (RA)
|
|
// if (a < EXTS(SI)) & TO[0] then TRAP
|
|
// if (a > EXTS(SI)) & TO[1] then TRAP
|
|
// if (a = EXTS(SI)) & TO[2] then TRAP
|
|
// if (a <u EXTS(SI)) & TO[3] then TRAP
|
|
// if (a >u EXTS(SI)) & TO[4] then TRAP
|
|
Value* ra = f.LoadGPR(i.D.RA);
|
|
Value* rb = f.LoadConstantInt64(XEEXTS16(i.D.DS));
|
|
return InstrEmit_trap(f, i, ra, rb, i.D.RT);
|
|
}
|
|
|
|
int InstrEmit_tw(PPCHIRBuilder& f, const InstrData& i) {
|
|
// a <- EXTS((RA)[32:63])
|
|
// b <- EXTS((RB)[32:63])
|
|
// if (a < b) & TO[0] then TRAP
|
|
// if (a > b) & TO[1] then TRAP
|
|
// if (a = b) & TO[2] then TRAP
|
|
// if (a <u b) & TO[3] then TRAP
|
|
// if (a >u b) & TO[4] then TRAP
|
|
Value* ra =
|
|
f.SignExtend(f.Truncate(f.LoadGPR(i.X.RA), INT32_TYPE), INT64_TYPE);
|
|
Value* rb =
|
|
f.SignExtend(f.Truncate(f.LoadGPR(i.X.RB), INT32_TYPE), INT64_TYPE);
|
|
return InstrEmit_trap(f, i, ra, rb, i.X.RT);
|
|
}
|
|
|
|
int InstrEmit_twi(PPCHIRBuilder& f, const InstrData& i) {
|
|
// a <- EXTS((RA)[32:63])
|
|
// if (a < EXTS(SI)) & TO[0] then TRAP
|
|
// if (a > EXTS(SI)) & TO[1] then TRAP
|
|
// if (a = EXTS(SI)) & TO[2] then TRAP
|
|
// if (a <u EXTS(SI)) & TO[3] then TRAP
|
|
// if (a >u EXTS(SI)) & TO[4] then TRAP
|
|
if (i.D.RA == 0 && i.D.RT == 0x1F) {
|
|
// This is a special trap. Probably.
|
|
uint16_t type = (uint16_t)XEEXTS16(i.D.DS);
|
|
f.Trap(type);
|
|
return 0;
|
|
}
|
|
Value* ra =
|
|
f.SignExtend(f.Truncate(f.LoadGPR(i.D.RA), INT32_TYPE), INT64_TYPE);
|
|
Value* rb = f.LoadConstantInt64(XEEXTS16(i.D.DS));
|
|
return InstrEmit_trap(f, i, ra, rb, i.D.RT);
|
|
}
|
|
|
|
// Processor control (A-26)
|
|
|
|
int InstrEmit_mfcr(PPCHIRBuilder& f, const InstrData& i) {
|
|
// mfocrf RT,FXM
|
|
// RT <- undefined
|
|
// count <- 0
|
|
// do i = 0 to 7
|
|
// if FXMi = 1 then
|
|
// n <- i
|
|
// count <- count + 1
|
|
// if count = 1 then
|
|
// RT4un + 32:4un + 35 <- CR4un + 32 : 4un + 35
|
|
|
|
// TODO(benvanik): optimize mfcr sequences.
|
|
// Often look something like this:
|
|
// mfocrf r11, cr6
|
|
// not r10, r11
|
|
// extrwi r3, r10, 1, 26
|
|
// Could recognize this and only load the appropriate CR bit.
|
|
|
|
Value* v;
|
|
if (i.XFX.spr & (1 << 9)) {
|
|
uint32_t bits = (i.XFX.spr & 0x1FF) >> 1;
|
|
int count = 0;
|
|
int cri = 0;
|
|
for (int b = 0; b <= 7; ++b) {
|
|
if (bits & (1 << b)) {
|
|
cri = 7 - b;
|
|
++count;
|
|
}
|
|
}
|
|
if (count == 1) {
|
|
v = f.LoadCR(cri);
|
|
} else {
|
|
v = f.LoadZeroInt64();
|
|
}
|
|
} else {
|
|
v = f.LoadCR();
|
|
}
|
|
f.StoreGPR(i.XFX.RT, v);
|
|
return 0;
|
|
}
|
|
|
|
int InstrEmit_mfspr(PPCHIRBuilder& f, const InstrData& i) {
|
|
// n <- spr[5:9] || spr[0:4]
|
|
// if length(SPR(n)) = 64 then
|
|
// RT <- SPR(n)
|
|
// else
|
|
// RT <- i32.0 || SPR(n)
|
|
Value* v;
|
|
const uint32_t n = ((i.XFX.spr & 0x1F) << 5) | ((i.XFX.spr >> 5) & 0x1F);
|
|
switch (n) {
|
|
case 1:
|
|
// XER
|
|
v = f.LoadXER();
|
|
break;
|
|
case 8:
|
|
// LR
|
|
v = f.LoadLR();
|
|
break;
|
|
case 9:
|
|
// CTR
|
|
v = f.LoadCTR();
|
|
break;
|
|
case 256:
|
|
// VRSAVE
|
|
v = f.LoadZeroInt64();
|
|
break;
|
|
case 268:
|
|
// TB
|
|
v = f.LoadClock();
|
|
break;
|
|
case 269:
|
|
// TBU
|
|
v = f.Shr(f.LoadClock(), 32);
|
|
break;
|
|
case 287:
|
|
// [ Processor Version Register (PVR) ]
|
|
// PVR is a 32 bit, read-only register within the supervisor level.
|
|
// Bits 0 to 15 are the version number.
|
|
// Bits 16 to 31 are the revision number.
|
|
// Known Values: 0x710600?, 0x710700, 0x710800 (Corona?);
|
|
// Note: Some XEXs (such as mfgbootlauncher.xex) may check for a value
|
|
// that's less than 0x710700.
|
|
v = f.LoadConstantUint64(cvars::pvr);
|
|
break;
|
|
default:
|
|
XEINSTRNOTIMPLEMENTED();
|
|
return 1;
|
|
}
|
|
f.StoreGPR(i.XFX.RT, v);
|
|
return 0;
|
|
}
|
|
|
|
int InstrEmit_mftb(PPCHIRBuilder& f, const InstrData& i) {
|
|
Value* time = f.LoadClock();
|
|
const uint32_t n = ((i.XFX.spr & 0x1F) << 5) | ((i.XFX.spr >> 5) & 0x1F);
|
|
if (n == 268) {
|
|
// TB - full bits.
|
|
} else {
|
|
// TBU - upper bits only.
|
|
time = f.Shr(time, 32);
|
|
}
|
|
f.StoreGPR(i.XFX.RT, time);
|
|
return 0;
|
|
}
|
|
|
|
int InstrEmit_mtcrf(PPCHIRBuilder& f, const InstrData& i) {
|
|
// mtocrf FXM,RS
|
|
// count <- 0
|
|
// do i = 0 to 7
|
|
// if FXMi = 1 then
|
|
// n <- i
|
|
// count <- count + 1
|
|
// if count = 1 then
|
|
// CR4un + 32 : 4un + 35 <- RS4un + 32:4un + 35
|
|
|
|
Value* v = f.LoadGPR(i.XFX.RT);
|
|
if (i.XFX.spr & (1 << 9)) {
|
|
uint32_t bits = (i.XFX.spr & 0x1FF) >> 1;
|
|
int count = 0;
|
|
int cri = 0;
|
|
for (int b = 0; b <= 7; ++b) {
|
|
if (bits & (1 << b)) {
|
|
cri = 7 - b;
|
|
++count;
|
|
}
|
|
}
|
|
if (count == 1) {
|
|
f.StoreCR(cri, v);
|
|
} else {
|
|
// Invalid; store zero to CR.
|
|
f.StoreCR(f.LoadZeroInt64());
|
|
}
|
|
} else {
|
|
uint32_t bits = (i.XFX.spr & 0x1FF) >> 1;
|
|
for (int b = 0; b <= 7; ++b) {
|
|
if (bits & (1 << b)) {
|
|
int cri = 7 - b;
|
|
f.StoreCR(cri, v);
|
|
}
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int InstrEmit_mtspr(PPCHIRBuilder& f, const InstrData& i) {
|
|
// n <- spr[5:9] || spr[0:4]
|
|
// if length(SPR(n)) = 64 then
|
|
// SPR(n) <- (RS)
|
|
// else
|
|
// SPR(n) <- (RS)[32:63]
|
|
|
|
Value* rt = f.LoadGPR(i.XFX.RT);
|
|
|
|
const uint32_t n = ((i.XFX.spr & 0x1F) << 5) | ((i.XFX.spr >> 5) & 0x1F);
|
|
switch (n) {
|
|
case 1:
|
|
// XER
|
|
f.StoreXER(rt);
|
|
break;
|
|
case 8:
|
|
// LR
|
|
f.StoreLR(rt);
|
|
break;
|
|
case 9:
|
|
// CTR
|
|
f.StoreCTR(rt);
|
|
break;
|
|
case 256:
|
|
// VRSAVE
|
|
break;
|
|
default:
|
|
XEINSTRNOTIMPLEMENTED();
|
|
return 1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
// MSR is used for toggling interrupts (among other things).
|
|
// We track it here for taking a global processor lock, as lots of lockfree
|
|
// code requires it. Sequences of mtmsr/lwar/stcw/mtmsr come up a lot, and
|
|
// without the lock here threads can livelock.
|
|
|
|
int InstrEmit_mfmsr(PPCHIRBuilder& f, const InstrData& i) {
|
|
// bit 48 = EE; interrupt enabled
|
|
// bit 62 = RI; recoverable interrupt
|
|
// return 8000h if unlocked (interrupts enabled), else 0
|
|
f.MemoryBarrier();
|
|
if (cvars::disable_global_lock || true) {
|
|
f.StoreGPR(i.X.RT, f.LoadConstantUint64(0));
|
|
|
|
} else {
|
|
f.CallExtern(f.builtins()->check_global_lock);
|
|
f.StoreGPR(i.X.RT,
|
|
f.LoadContext(offsetof(PPCContext, scratch), INT64_TYPE));
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int InstrEmit_mtmsr(PPCHIRBuilder& f, const InstrData& i) {
|
|
if (i.X.RA & 0x01) {
|
|
// L = 1
|
|
// iff storing from r13
|
|
f.MemoryBarrier();
|
|
f.StoreContext(
|
|
offsetof(PPCContext, scratch),
|
|
f.ZeroExtend(f.ZeroExtend(f.LoadGPR(i.X.RT), INT64_TYPE), INT64_TYPE));
|
|
#if 0
|
|
if (i.X.RT == 13) {
|
|
// iff storing from r13 we are taking a lock (disable interrupts).
|
|
if (!cvars::disable_global_lock) {
|
|
f.CallExtern(f.builtins()->enter_global_lock);
|
|
}
|
|
} else {
|
|
// Otherwise we are restoring interrupts (probably).
|
|
if (!cvars::disable_global_lock) {
|
|
f.CallExtern(f.builtins()->leave_global_lock);
|
|
}
|
|
}
|
|
#endif
|
|
return 0;
|
|
} else {
|
|
// L = 0
|
|
XEINSTRNOTIMPLEMENTED();
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
int InstrEmit_mtmsrd(PPCHIRBuilder& f, const InstrData& i) {
|
|
if (i.X.RA & 0x01) {
|
|
// L = 1
|
|
f.MemoryBarrier();
|
|
f.StoreContext(offsetof(PPCContext, scratch),
|
|
f.ZeroExtend(f.LoadGPR(i.X.RT), INT64_TYPE));
|
|
#if 0
|
|
if (i.X.RT == 13) {
|
|
// iff storing from r13 we are taking a lock (disable interrupts).
|
|
if (!cvars::disable_global_lock) {
|
|
f.CallExtern(f.builtins()->enter_global_lock);
|
|
}
|
|
} else {
|
|
// Otherwise we are restoring interrupts (probably).
|
|
if (!cvars::disable_global_lock) {
|
|
f.CallExtern(f.builtins()->leave_global_lock);
|
|
}
|
|
}
|
|
#endif
|
|
return 0;
|
|
} else {
|
|
// L = 0
|
|
XEINSTRNOTIMPLEMENTED();
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
void RegisterEmitCategoryControl() {
|
|
XEREGISTERINSTR(bx);
|
|
XEREGISTERINSTR(bcx);
|
|
XEREGISTERINSTR(bcctrx);
|
|
XEREGISTERINSTR(bclrx);
|
|
XEREGISTERINSTR(crand);
|
|
XEREGISTERINSTR(crandc);
|
|
XEREGISTERINSTR(creqv);
|
|
XEREGISTERINSTR(crnand);
|
|
XEREGISTERINSTR(crnor);
|
|
XEREGISTERINSTR(cror);
|
|
XEREGISTERINSTR(crorc);
|
|
XEREGISTERINSTR(crxor);
|
|
XEREGISTERINSTR(mcrf);
|
|
XEREGISTERINSTR(sc);
|
|
XEREGISTERINSTR(td);
|
|
XEREGISTERINSTR(tdi);
|
|
XEREGISTERINSTR(tw);
|
|
XEREGISTERINSTR(twi);
|
|
XEREGISTERINSTR(mfcr);
|
|
XEREGISTERINSTR(mfspr);
|
|
XEREGISTERINSTR(mftb);
|
|
XEREGISTERINSTR(mtcrf);
|
|
XEREGISTERINSTR(mtspr);
|
|
XEREGISTERINSTR(mfmsr);
|
|
XEREGISTERINSTR(mtmsr);
|
|
XEREGISTERINSTR(mtmsrd);
|
|
}
|
|
|
|
} // namespace ppc
|
|
} // namespace cpu
|
|
} // namespace xe
|